This patch series enables ECC edac support for Calxeda ECX-2000 (Midway). The ECX-2000 memory controller is similar to Highbank but has different register bases for error and interrupt registers.
Testing the driver uncovered a bug in the interrupt initialization. So there is also a fix for this for all the Highbank edac drivers. The interrupt was enabled too early which caused a crash if there are interrupts pending (ECC errors) during driver initialization.
Also some improvements and unification of edac log messages I found useful.
-Robert
Rob Herring (1): ARM: dts: calxeda: move memory-controller node out of ecx-common.dtsi
Robert Richter (4): edac, highbank: Fix interrupt setup of mem and l2 controller edac, highbank: Add Calxeda ECX-2000 support edac, highbank: Improve and unify naming edac: Unify reporting of device info for device, mc and pci
.../devicetree/bindings/arm/calxeda/mem-ctrlr.txt | 4 +- arch/arm/boot/dts/ecx-2000.dts | 6 + arch/arm/boot/dts/ecx-common.dtsi | 6 - arch/arm/boot/dts/highbank.dts | 6 + drivers/edac/edac_device.c | 9 +- drivers/edac/edac_mc.c | 6 +- drivers/edac/edac_pci.c | 8 +- drivers/edac/highbank_l2_edac.c | 33 +++--- drivers/edac/highbank_mc_edac.c | 128 +++++++++++++-------- 9 files changed, 127 insertions(+), 79 deletions(-)