From: Mark Brown <broonie(a)linaro.org>
Within a DAPM sequence we normally don't care about when exactly a register
write has completed so long as they happen in the order we requested. This
means that we can issue most of the writes we do asynchronously which
should maximise the ability of the underlying frameworks to keep the
hardware busy, providing a small performance improvement on some systems.
We currently ensure that all writes are completed both when changing to a
different device and when calling into the regulator and clock frameworks.
This should ensure that the previous ordering is maintained.
We also ensure that writes are completed prior to calling into widget
event functions since some event functions implement delays. This
should be improved in future so that widgets can disable this sync in
order to add extra writes.
Signed-off-by: Mark Brown <broonie(a)linaro.org>
xvdfvsd
---
sound/soc/soc-dapm.c | 24 ++++++++++++++++++++++--
1 file changed, 22 insertions(+), 2 deletions(-)
diff --git a/sound/soc/soc-dapm.c b/sound/soc/soc-dapm.c
index 25b9554..905e4c5 100644
--- a/sound/soc/soc-dapm.c
+++ b/sound/soc/soc-dapm.c
@@ -409,6 +409,12 @@ static inline void soc_widget_unlock(struct snd_soc_dapm_widget *w)
mutex_unlock(&w->platform->mutex);
}
+static void soc_dapm_async_complete(struct snd_soc_dapm_context *dapm)
+{
+ if (dapm->codec && dapm->codec->using_regmap)
+ regmap_async_complete(dapm->codec->control_data);
+}
+
static int soc_widget_update_bits_locked(struct snd_soc_dapm_widget *w,
unsigned short reg, unsigned int mask, unsigned int value)
{
@@ -417,8 +423,9 @@ static int soc_widget_update_bits_locked(struct snd_soc_dapm_widget *w,
int ret;
if (w->codec && w->codec->using_regmap) {
- ret = regmap_update_bits_check(w->codec->control_data,
- reg, mask, value, &change);
+ ret = regmap_update_bits_check_async(w->codec->control_data,
+ reg, mask, value,
+ &change);
if (ret != 0)
return ret;
} else {
@@ -1201,6 +1208,8 @@ int dapm_regulator_event(struct snd_soc_dapm_widget *w,
{
int ret;
+ soc_dapm_async_complete(w->dapm);
+
if (SND_SOC_DAPM_EVENT_ON(event)) {
if (w->on_val & SND_SOC_DAPM_REGULATOR_BYPASS) {
ret = regulator_allow_bypass(w->regulator, false);
@@ -1234,6 +1243,8 @@ int dapm_clock_event(struct snd_soc_dapm_widget *w,
if (!w->clk)
return -EIO;
+ soc_dapm_async_complete(w->dapm);
+
#ifdef CONFIG_HAVE_CLK
if (SND_SOC_DAPM_EVENT_ON(event)) {
return clk_prepare_enable(w->clk);
@@ -1426,6 +1437,7 @@ static void dapm_seq_check_event(struct snd_soc_card *card,
if (w->event && (w->event_flags & event)) {
pop_dbg(w->dapm->dev, card->pop_time, "pop test : %s %s\n",
w->name, ev_name);
+ soc_dapm_async_complete(w->dapm);
trace_snd_soc_dapm_widget_event_start(w, event);
ret = w->event(w, NULL, event);
trace_snd_soc_dapm_widget_event_done(w, event);
@@ -1498,6 +1510,7 @@ static void dapm_seq_run(struct snd_soc_card *card,
struct list_head *list, int event, bool power_up)
{
struct snd_soc_dapm_widget *w, *n;
+ struct snd_soc_dapm_context *d;
LIST_HEAD(pending);
int cur_sort = -1;
int cur_subseq = -1;
@@ -1528,6 +1541,9 @@ static void dapm_seq_run(struct snd_soc_card *card,
cur_subseq);
}
+ if (cur_dapm && w->dapm != cur_dapm)
+ soc_dapm_async_complete(cur_dapm);
+
INIT_LIST_HEAD(&pending);
cur_sort = -1;
cur_subseq = INT_MIN;
@@ -1586,6 +1602,10 @@ static void dapm_seq_run(struct snd_soc_card *card,
cur_dapm->seq_notifier(cur_dapm,
i, cur_subseq);
}
+
+ list_for_each_entry(d, &card->dapm_list, list) {
+ soc_dapm_async_complete(d);
+ }
}
static void dapm_widget_update(struct snd_soc_card *card)
--
1.8.4.rc3
On Mon, Oct 07, 2013 at 09:37:19PM -0700, Victor Kamensky wrote:
> In big endian mode mcpm_entry_point is first function
> that called on secondaries CPU. First it should switch
> CPU into big endian code.
>
> Signed-off-by: Victor Kamensky <victor.kamensky(a)linaro.org>
Providing Nico's also OK with it, I don't see a problem with this.
Minor cosmetic nit: please line up the ) after be with the others.
Not the end of the world, though.
Reviewed-by: Dave Martin <Dave.Martin(a)arm.com>
Cheers
---Dave
> ---
> arch/arm/common/mcpm_head.S | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm/common/mcpm_head.S b/arch/arm/common/mcpm_head.S
> index 39c96df..4f88f5e 100644
> --- a/arch/arm/common/mcpm_head.S
> +++ b/arch/arm/common/mcpm_head.S
> @@ -15,6 +15,7 @@
>
> #include <linux/linkage.h>
> #include <asm/mcpm.h>
> +#include <asm/assembler.h>
>
> #include "vlock.h"
>
> @@ -47,6 +48,7 @@
>
> ENTRY(mcpm_entry_point)
>
> + ARM_BE8(setend be)
> THUMB( adr r12, BSYM(1f) )
> THUMB( bx r12 )
> THUMB( .thumb )
> --
> 1.8.1.4
>
>
> _______________________________________________
> linaro-kernel mailing list
> linaro-kernel(a)lists.linaro.org
> http://lists.linaro.org/mailman/listinfo/linaro-kernel
From: Mark Brown <broonie(a)linaro.org>
Since it is quite common for single register raw or async writes to be
generated by rbtree cache syncs or firmware downloads and essentially all
hardware will be faster with only a single transfer optimise this case by
copying single values into the internal scratch buffer before sending.
Signed-off-by: Mark Brown <broonie(a)linaro.org>
---
drivers/base/regmap/regmap.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/base/regmap/regmap.c b/drivers/base/regmap/regmap.c
index 5754513..4866ae5 100644
--- a/drivers/base/regmap/regmap.c
+++ b/drivers/base/regmap/regmap.c
@@ -1118,6 +1118,16 @@ int _regmap_raw_write(struct regmap *map, unsigned int reg,
u8[0] |= map->write_flag_mask;
+ /*
+ * Essentially all I/O mechanisms will be faster with a single
+ * buffer to write. Since register syncs often generate raw
+ * writes of single registers optimise that case.
+ */
+ if (val != work_val && val_len == map->format.val_bytes) {
+ memcpy(work_val, val, map->format.val_bytes);
+ val = work_val;
+ }
+
if (async && map->bus->async_write) {
struct regmap_async *async;
--
1.8.4.rc3
On ARM the debug info is not present in the .eh_frame sections but
in .debug_frame instead, in dwarf format.
This patch set uses libunwind to load and parse the dwarf debug info from
the .debug_frame section if no .eh_frame_hdr section is found; also it
sets the hooks in the perf_regs and libunwind code for ARMv7.
Dependencies:
. if present, libunwind >= 1.1 is needed to prevent a segfault when
parsing the dwarf info,
. libunwind needs to be configured with --enable-debug-frame. Note:
--enable-debug-frame is automatically selected on ARM.
The generated perf binary has been tested on ARMv7 (OMAP4, Marvell
Armada XP) and x86_64, using the following commands:
perf record -g [dwarf] -- <binary>
perf report --sort symbol --call-graph --stdio
Jean Pihet (2):
perf tools: Check libunwind for availability of dwarf parsing feature
perf: parse the .debug_frame section in case .eh_frame is not present
Will Deacon (2):
ARM: perf: add support for perf registers API
ARM: perf: wire up perf_regs and unwind support for ARM
arch/arm/Kconfig | 2 +
arch/arm/include/uapi/asm/Kbuild | 1 +
arch/arm/include/uapi/asm/perf_regs.h | 23 ++++++++++
arch/arm/kernel/Makefile | 1 +
arch/arm/kernel/perf_regs.c | 30 +++++++++++++
tools/perf/arch/arm/Makefile | 3 ++
tools/perf/arch/arm/include/perf_regs.h | 54 ++++++++++++++++++++++++
tools/perf/arch/arm/util/unwind.c | 48 +++++++++++++++++++++
tools/perf/config/Makefile | 13 ++++--
tools/perf/config/feature-tests.mak | 21 ++++++++-
tools/perf/util/unwind.c | 75 ++++++++++++++++++++++++++-------
11 files changed, 251 insertions(+), 20 deletions(-)
create mode 100644 arch/arm/include/uapi/asm/perf_regs.h
create mode 100644 arch/arm/kernel/perf_regs.c
create mode 100644 tools/perf/arch/arm/include/perf_regs.h
create mode 100644 tools/perf/arch/arm/util/unwind.c
--
1.7.11.7