This patchset adds support for using Big Endian mode of AArch64 CPUs
All patches have been tested on APM X-Gene Storm SOC.
The Big Endian toolchain used for development can be found at:
http://cbuild.validation.linaro.org/snapshots/big_endian
We have tested both 32bit BE and 64bit BE root filesystems with these
patches.
The 64bit BE root filesystem was build manually using busybox-1.21.1 and
above mentioned toolchain.
The 32bit BE root filesystem was readily available from Linaro releases
located at: http://snapshots.linaro.org/openembedded/images
Ankit Jindal (4):
ARM64: Add Kconfig option to enable Big Endian kernel
ARM64: Include appropriate byteorder for Big Endian
ARM64: Big Endian fixes for kernel booting
ARM64: Support for 32-bit big endian userspace
arch/arm64/Kconfig | 2 ++
arch/arm64/Makefile | 7 +++++++
arch/arm64/include/asm/assembler.h | 7 +++++++
arch/arm64/include/asm/processor.h | 3 +++
arch/arm64/include/uapi/asm/byteorder.h | 4 ++++
arch/arm64/kernel/head.S | 34 +++++++++++++++++++++++++++++++
arch/arm64/kernel/setup.c | 19 +++++++++++++----
arch/arm64/kernel/signal32.c | 4 ++++
arch/arm64/kernel/smp_spin_table.c | 5 +++--
arch/arm64/mm/Kconfig | 7 +++++++
arch/arm64/mm/proc.S | 2 +-
11 files changed, 87 insertions(+), 7 deletions(-)
create mode 100644 arch/arm64/mm/Kconfig
--
1.7.9.5
Hi All,
This is version 2 of cci big endian fix. Idea of this
way of fixing was suggested by Ben Dooks [1]. Compared to
previous solution this one does not use ifdefs and looks
much cleaner.
This was tested on TC2 both LE and BE, CONFIG_ARM_CCI
was enabled.
[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2013-October/203248.h…
Thanks,
Victor
Victor Kamensky (1):
ARM: cci driver need big endian fixes in asm code
drivers/bus/arm-cci.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
--
1.8.1.4
This patch series enables ECC edac support for Calxeda ECX-2000
(Midway). The ECX-2000 memory controller is similar to Highbank but
has different register bases for error and interrupt registers.
Testing the driver uncovered a bug in the interrupt initialization.
So there is also a fix for this for all the Highbank edac drivers. The
interrupt was enabled too early which caused a crash if there are
interrupts pending (ECC errors) during driver initialization.
Also some improvements and unification of edac log messages I found
useful.
-Robert
Rob Herring (1):
ARM: dts: calxeda: move memory-controller node out of ecx-common.dtsi
Robert Richter (4):
edac, highbank: Fix interrupt setup of mem and l2 controller
edac, highbank: Add Calxeda ECX-2000 support
edac, highbank: Improve and unify naming
edac: Unify reporting of device info for device, mc and pci
.../devicetree/bindings/arm/calxeda/mem-ctrlr.txt | 4 +-
arch/arm/boot/dts/ecx-2000.dts | 6 +
arch/arm/boot/dts/ecx-common.dtsi | 6 -
arch/arm/boot/dts/highbank.dts | 6 +
drivers/edac/edac_device.c | 9 +-
drivers/edac/edac_mc.c | 6 +-
drivers/edac/edac_pci.c | 8 +-
drivers/edac/highbank_l2_edac.c | 33 +++---
drivers/edac/highbank_mc_edac.c | 128 +++++++++++++--------
9 files changed, 127 insertions(+), 79 deletions(-)
--
1.8.4.rc3