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mainline boot: 31 pass, 0 fail (v3.13-rc4-36-g941ef73)

by Kevin's boot bot

Automated DT boot report for various ARM defconfigs. Tree/Branch: mainline Git describe: v3.13-rc4-36-g941ef73 Full Report =========== omap2plus_defconfig ------------------- am335x-boneblack PASS: 0 min 27.9 sec omap3-beagle-xm PASS: 0 min 50.8 sec am335x-bone PASS: 0 min 26.7 sec omap4-panda PASS: 1 min 3.4 sec omap4-panda-es PASS: 1 min 4.5 sec omap3-tobi,3730storm PASS: 0 min 23.5 sec omap3-tobi,3530overo PASS: 0 min 21.8 sec tegra_defconfig --------------- tegra30-beaver PASS: 0 min 16.9 sec imx_v6_v7_defconfig ------------------- imx6dl-wandboard,wand-dual PASS: 0 min 17.1 sec imx6dl-wandboard,wand-solo PASS: 0 min 18.2 sec imx6q-wandboard PASS: 0 min 16.6 sec sunxi_defconfig --------------- sun7i-a20-cubieboard2 PASS: 0 min 12.1 sec mvebu_defconfig --------------- armada-xp-openblocks-ax3-4 PASS: 0 min 21.9 sec armada-370-mirabox PASS: 0 min 21.1 sec multi_v7_defconfig ------------------ ste-snowball PASS: 0 min 32.0 sec tegra30-beaver PASS: 0 min 14.2 sec am335x-boneblack PASS: 0 min 24.7 sec omap3-beagle-xm PASS: 0 min 51.5 sec sun7i-a20-cubieboard2 PASS: 0 min 13.1 sec armada-370-mirabox PASS: 0 min 20.6 sec omap4-panda PASS: 1 min 0.1 sec omap4-panda-es PASS: 1 min 1.9 sec armada-xp-openblocks-ax3-4 PASS: 0 min 22.9 sec imx6dl-wandboard,wand-solo PASS: 0 min 17.6 sec am335x-bone PASS: 0 min 33.5 sec imx6q-wandboard PASS: 0 min 15.8 sec omap3-tobi,3730storm PASS: 0 min 22.9 sec imx6dl-wandboard,wand-dual PASS: 0 min 17.9 sec omap3-tobi,3530overo PASS: 0 min 20.1 sec u8500_defconfig --------------- ste-snowball PASS: 0 min 27.9 sec sama5_defconfig --------------- sama5d35ek PASS: 0 min 17.3 sec

11 years, 5 months

mainline boot: 31 pass, 0 fail (v3.13-rc4-21-g0eda402)

by Kevin's boot bot

Automated DT boot report for various ARM defconfigs. Tree/Branch: mainline Git describe: v3.13-rc4-21-g0eda402 Full Report =========== omap2plus_defconfig ------------------- am335x-boneblack PASS: 0 min 27.9 sec omap3-beagle-xm PASS: 0 min 52.5 sec am335x-bone PASS: 0 min 26.6 sec omap4-panda PASS: 1 min 4.4 sec omap4-panda-es PASS: 1 min 6.0 sec omap3-tobi,3730storm PASS: 0 min 23.6 sec omap3-tobi,3530overo PASS: 0 min 21.8 sec tegra_defconfig --------------- tegra30-beaver PASS: 0 min 17.1 sec imx_v6_v7_defconfig ------------------- imx6dl-wandboard,wand-dual PASS: 0 min 16.9 sec imx6dl-wandboard,wand-solo PASS: 0 min 18.4 sec imx6q-wandboard PASS: 0 min 16.5 sec sunxi_defconfig --------------- sun7i-a20-cubieboard2 PASS: 0 min 12.1 sec mvebu_defconfig --------------- armada-xp-openblocks-ax3-4 PASS: 0 min 21.9 sec armada-370-mirabox PASS: 0 min 20.0 sec multi_v7_defconfig ------------------ ste-snowball PASS: 0 min 29.0 sec tegra30-beaver PASS: 0 min 16.8 sec am335x-boneblack PASS: 0 min 29.7 sec omap3-beagle-xm PASS: 0 min 51.9 sec sun7i-a20-cubieboard2 PASS: 0 min 13.1 sec armada-370-mirabox PASS: 0 min 20.7 sec omap4-panda PASS: 1 min 0.9 sec omap4-panda-es PASS: 1 min 4.3 sec armada-xp-openblocks-ax3-4 PASS: 0 min 23.0 sec imx6dl-wandboard,wand-solo PASS: 0 min 17.6 sec am335x-bone PASS: 0 min 23.5 sec imx6q-wandboard PASS: 0 min 16.8 sec omap3-tobi,3730storm PASS: 0 min 22.7 sec imx6dl-wandboard,wand-dual PASS: 0 min 17.8 sec omap3-tobi,3530overo PASS: 0 min 20.2 sec u8500_defconfig --------------- ste-snowball PASS: 0 min 30.6 sec sama5_defconfig --------------- sama5d35ek PASS: 0 min 17.4 sec

11 years, 5 months

[PATCH v4] ARM64 breakpoint and single step exception hooks

by Sandeepa Prabhu

This patch adds support for breakpoint and single-step exception hooks. v3 version of this patch is published and reviewed with arm64 kdgb and kprobes patch series [1] and [2] [1] http://lwn.net/Articles/570648/ [2] https://lwn.net/Articles/571063/ Changes v3 -> v4: -Incorporated review comments: http://lists.infradead.org/pipermail/linux-arm-kernel/2013-October/207372.h… -Removed unnecessary comments -Added comments for breakpoint re-entrancy & rw locks - Rebased on top of git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64.git Branch:upstream commit ID: dc1ccc48159d63eca5089e507c82c7d22ef60839 (Linux 3.13-rc2) - CCing Jason Wessel, since arm64 kgdb patchset is dependant on this. Sandeepa Prabhu (1): arm64: support single-step and breakpoint handler hooks arch/arm64/include/asm/debug-monitors.h | 21 ++++++++ arch/arm64/kernel/debug-monitors.c | 88 ++++++++++++++++++++++++++++++++- arch/arm64/kernel/entry.S | 2 + 3 files changed, 110 insertions(+), 1 deletion(-) -- 1.8.1.2

11 years, 5 months

[PATCH 1/6] arm64: Add asm/cpu.h

by Mark Brown

From: Hanjun Guo <hanjun.guo(a)linaro.org> In order to implement both topology and ACPI support we need to define per-CPU data. Signed-off-by: Graeme Gregory <graeme.gregory(a)linaro.org> Signed-off-by: Hanjun Guo <hanjun.guo(a)linaro.org> Signed-off-by: Mark Brown <broonie(a)linaro.org> --- arch/arm64/include/asm/cpu.h | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 arch/arm64/include/asm/cpu.h diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h new file mode 100644 index 000000000000..d67ff011d361 --- /dev/null +++ b/arch/arm64/include/asm/cpu.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2004-2005 ARM Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __ASM_ARM64_CPU_H +#define __ASM_ARM64_CPU_H + +#include <linux/percpu.h> +#include <linux/cpu.h> +#include <linux/topology.h> + +struct cpuinfo_arm { + struct cpu cpu; + u64 cpuid; +#ifdef CONFIG_SMP + unsigned int loops_per_jiffy; +#endif +}; + +DECLARE_PER_CPU(struct cpuinfo_arm, cpu_data); + +#endif -- 1.8.5.1

11 years, 5 months

[PATCH 2/3] ARM64: perf: wire up perf_regs and unwind support

by jean.pihet＠linaro.org

From: Jean Pihet <jean.pihet(a)linaro.org> This patch hooks in the perf_regs and libunwind code for ARM64. The tools/perf/arch/arm64 is created; it contains the arch specific code for DWARF unwinding. Signed-off-by: Jean Pihet <jean.pihet(a)linaro.org> Cc: Will Deacon <will.deacon(a)arm.com> --- tools/perf/arch/arm64/Makefile | 7 +++ tools/perf/arch/arm64/include/perf_regs.h | 88 +++++++++++++++++++++++++++++++ tools/perf/arch/arm64/util/dwarf-regs.c | 81 ++++++++++++++++++++++++++++ tools/perf/arch/arm64/util/unwind.c | 82 ++++++++++++++++++++++++++++ tools/perf/config/Makefile | 8 ++- 5 files changed, 265 insertions(+), 1 deletion(-) create mode 100644 tools/perf/arch/arm64/Makefile create mode 100644 tools/perf/arch/arm64/include/perf_regs.h create mode 100644 tools/perf/arch/arm64/util/dwarf-regs.c create mode 100644 tools/perf/arch/arm64/util/unwind.c diff --git a/tools/perf/arch/arm64/Makefile b/tools/perf/arch/arm64/Makefile new file mode 100644 index 0000000..fe9b61e --- /dev/null +++ b/tools/perf/arch/arm64/Makefile @@ -0,0 +1,7 @@ +ifndef NO_DWARF +PERF_HAVE_DWARF_REGS := 1 +LIB_OBJS += $(OUTPUT)arch/$(ARCH)/util/dwarf-regs.o +endif +ifndef NO_LIBUNWIND +LIB_OBJS += $(OUTPUT)arch/$(ARCH)/util/unwind.o +endif diff --git a/tools/perf/arch/arm64/include/perf_regs.h b/tools/perf/arch/arm64/include/perf_regs.h new file mode 100644 index 0000000..a8a9683 --- /dev/null +++ b/tools/perf/arch/arm64/include/perf_regs.h @@ -0,0 +1,88 @@ +#ifndef ARCH_PERF_REGS_H +#define ARCH_PERF_REGS_H + +#include <stdlib.h> +#include "../../util/types.h" +#include <asm/perf_regs.h> + +#define PERF_REGS_MASK ((1ULL << PERF_REG_ARM_MAX) - 1) +#define PERF_REG_IP PERF_REG_ARM_PC +#define PERF_REG_SP PERF_REG_ARM_SP + +static inline const char *perf_reg_name(int id) +{ + switch (id) { + case PERF_REG_ARM_X0: + return "x0"; + case PERF_REG_ARM_X1: + return "x1"; + case PERF_REG_ARM_X2: + return "x2"; + case PERF_REG_ARM_X3: + return "x3"; + case PERF_REG_ARM_X4: + return "x4"; + case PERF_REG_ARM_X5: + return "x5"; + case PERF_REG_ARM_X6: + return "x6"; + case PERF_REG_ARM_X7: + return "x7"; + case PERF_REG_ARM_X8: + return "x8"; + case PERF_REG_ARM_X9: + return "x9"; + case PERF_REG_ARM_X10: + return "x10"; + case PERF_REG_ARM_X11: + return "x11"; + case PERF_REG_ARM_X12: + return "x12"; + case PERF_REG_ARM_X13: + return "x13"; + case PERF_REG_ARM_X14: + return "x14"; + case PERF_REG_ARM_X15: + return "x15"; + case PERF_REG_ARM_X16: + return "x16"; + case PERF_REG_ARM_X17: + return "x17"; + case PERF_REG_ARM_X18: + return "x18"; + case PERF_REG_ARM_X19: + return "x19"; + case PERF_REG_ARM_X20: + return "x20"; + case PERF_REG_ARM_X21: + return "x21"; + case PERF_REG_ARM_X22: + return "x22"; + case PERF_REG_ARM_X23: + return "x23"; + case PERF_REG_ARM_X24: + return "x24"; + case PERF_REG_ARM_X25: + return "x25"; + case PERF_REG_ARM_X26: + return "x26"; + case PERF_REG_ARM_X27: + return "x27"; + case PERF_REG_ARM_X28: + return "x28"; + case PERF_REG_ARM_FP: + return "fp"; + case PERF_REG_ARM_SP: + return "sp"; + case PERF_REG_ARM_LR: + return "lr"; + case PERF_REG_ARM_PC: + return "pc"; + default: + return NULL; + } + + return NULL; +} + +#endif /* ARCH_PERF_REGS_H */ diff --git a/tools/perf/arch/arm64/util/dwarf-regs.c b/tools/perf/arch/arm64/util/dwarf-regs.c new file mode 100644 index 0000000..23d319e --- /dev/null +++ b/tools/perf/arch/arm64/util/dwarf-regs.c @@ -0,0 +1,81 @@ +/* + * Mapping of DWARF debug register numbers into register names. + * + * Copyright (C) 2010 Will Deacon, ARM Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <stddef.h> +#include <dwarf-regs.h> + +struct pt_regs_dwarfnum { + const char *name; + unsigned int dwarfnum; +}; + +#define STR(s) #s +#define REG_DWARFNUM_NAME(r, num) {.name = r, .dwarfnum = num} +#define GPR_DWARFNUM_NAME(num) \ + {.name = STR(%r##num), .dwarfnum = num} +#define REG_DWARFNUM_END {.name = NULL, .dwarfnum = 0} + +/* + * Reference: + * http://infocenter.arm.com/help/topic/com.arm.doc.ihi0057b/IHI0057B_aadwarf6… + */ +static const struct pt_regs_dwarfnum regdwarfnum_table[] = { + GPR_DWARFNUM_NAME(0), + GPR_DWARFNUM_NAME(1), + GPR_DWARFNUM_NAME(2), + GPR_DWARFNUM_NAME(3), + GPR_DWARFNUM_NAME(4), + GPR_DWARFNUM_NAME(5), + GPR_DWARFNUM_NAME(6), + GPR_DWARFNUM_NAME(7), + GPR_DWARFNUM_NAME(8), + GPR_DWARFNUM_NAME(9), + GPR_DWARFNUM_NAME(10), + GPR_DWARFNUM_NAME(11), + GPR_DWARFNUM_NAME(12), + GPR_DWARFNUM_NAME(13), + GPR_DWARFNUM_NAME(14), + GPR_DWARFNUM_NAME(15), + GPR_DWARFNUM_NAME(16), + GPR_DWARFNUM_NAME(17), + GPR_DWARFNUM_NAME(18), + GPR_DWARFNUM_NAME(19), + GPR_DWARFNUM_NAME(20), + GPR_DWARFNUM_NAME(21), + GPR_DWARFNUM_NAME(22), + GPR_DWARFNUM_NAME(23), + GPR_DWARFNUM_NAME(24), + GPR_DWARFNUM_NAME(25), + GPR_DWARFNUM_NAME(26), + GPR_DWARFNUM_NAME(27), + GPR_DWARFNUM_NAME(28), + REG_DWARFNUM_NAME("%fp", 29), + REG_DWARFNUM_NAME("%lr", 30), + REG_DWARFNUM_NAME("%sp", 31), + REG_DWARFNUM_NAME("%pc", 32), + REG_DWARFNUM_END, +}; + +/** + * get_arch_regstr() - lookup register name from it's DWARF register number + * @n: the DWARF register number + * + * get_arch_regstr() returns the name of the register in struct + * regdwarfnum_table from it's DWARF register number. If the register is not + * found in the table, this returns NULL; + */ +const char *get_arch_regstr(unsigned int n) +{ + const struct pt_regs_dwarfnum *roff; + for (roff = regdwarfnum_table; roff->name != NULL; roff++) + if (roff->dwarfnum == n) + return roff->name; + return NULL; +} diff --git a/tools/perf/arch/arm64/util/unwind.c b/tools/perf/arch/arm64/util/unwind.c new file mode 100644 index 0000000..490bd5b --- /dev/null +++ b/tools/perf/arch/arm64/util/unwind.c @@ -0,0 +1,82 @@ + +#include <errno.h> +#include <libunwind.h> +#include "perf_regs.h" +#include "../../util/unwind.h" + +int unwind__arch_reg_id(int regnum) +{ + switch (regnum) { + case UNW_AARCH64_X0: + return PERF_REG_ARM_X0; + case UNW_AARCH64_X1: + return PERF_REG_ARM_X1; + case UNW_AARCH64_X2: + return PERF_REG_ARM_X2; + case UNW_AARCH64_X3: + return PERF_REG_ARM_X3; + case UNW_AARCH64_X4: + return PERF_REG_ARM_X4; + case UNW_AARCH64_X5: + return PERF_REG_ARM_X5; + case UNW_AARCH64_X6: + return PERF_REG_ARM_X6; + case UNW_AARCH64_X7: + return PERF_REG_ARM_X7; + case UNW_AARCH64_X8: + return PERF_REG_ARM_X8; + case UNW_AARCH64_X9: + return PERF_REG_ARM_X9; + case UNW_AARCH64_X10: + return PERF_REG_ARM_X10; + case UNW_AARCH64_X11: + return PERF_REG_ARM_X11; + case UNW_AARCH64_X12: + return PERF_REG_ARM_X12; + case UNW_AARCH64_X13: + return PERF_REG_ARM_X13; + case UNW_AARCH64_X14: + return PERF_REG_ARM_X14; + case UNW_AARCH64_X15: + return PERF_REG_ARM_X15; + case UNW_AARCH64_X16: + return PERF_REG_ARM_X16; + case UNW_AARCH64_X17: + return PERF_REG_ARM_X17; + case UNW_AARCH64_X18: + return PERF_REG_ARM_X18; + case UNW_AARCH64_X19: + return PERF_REG_ARM_X19; + case UNW_AARCH64_X20: + return PERF_REG_ARM_X20; + case UNW_AARCH64_X21: + return PERF_REG_ARM_X21; + case UNW_AARCH64_X22: + return PERF_REG_ARM_X22; + case UNW_AARCH64_X23: + return PERF_REG_ARM_X23; + case UNW_AARCH64_X24: + return PERF_REG_ARM_X24; + case UNW_AARCH64_X25: + return PERF_REG_ARM_X25; + case UNW_AARCH64_X26: + return PERF_REG_ARM_X26; + case UNW_AARCH64_X27: + return PERF_REG_ARM_X27; + case UNW_AARCH64_X28: + return PERF_REG_ARM_X28; + case UNW_AARCH64_X29: + return PERF_REG_ARM_FP; + case UNW_AARCH64_X30: + return PERF_REG_ARM_LR; + case UNW_AARCH64_SP: + return PERF_REG_ARM_SP; + case UNW_AARCH64_PC: + return PERF_REG_ARM_PC; + default: + pr_err("unwind: invalid reg id %d\n", regnum); + return -EINVAL; + } + + return -EINVAL; +} diff --git a/tools/perf/config/Makefile b/tools/perf/config/Makefile index f7d11a8..658295c 100644 --- a/tools/perf/config/Makefile +++ b/tools/perf/config/Makefile @@ -31,11 +31,17 @@ ifeq ($(ARCH),x86_64) endif NO_PERF_REGS := 0 endif + ifeq ($(ARCH),arm) NO_PERF_REGS := 0 LIBUNWIND_LIBS = -lunwind -lunwind-arm endif +ifeq ($(ARCH),arm64) + NO_PERF_REGS := 0 + LIBUNWIND_LIBS = -lunwind -lunwind-aarch64 +endif + ifeq ($(NO_PERF_REGS),0) CFLAGS += -DHAVE_PERF_REGS_SUPPORT endif @@ -329,7 +335,7 @@ ifndef NO_LIBUNWIND msg := $(warning No libunwind found, disabling post unwind support. Please install libunwind-dev[el] >= 1.1); NO_LIBUNWIND := 1 else - ifeq ($(ARCH),arm) + ifeq ($(ARCH),$(filter $(ARCH),arm arm64)) $(call feature_check,libunwind-debug-frame) ifneq ($(feature-libunwind-debug-frame), 1) msg := $(warning No debug_frame support found in libunwind); -- 1.7.11.7

11 years, 5 months

[PATCH 1/3] ARM64: perf: add support for perf registers API

by jean.pihet＠linaro.org

From: Jean Pihet <jean.pihet(a)linaro.org> This patch implements the functions required for the perf registers API, allowing the perf tool to interface kernel register dumps with libunwind in order to provide userspace backtracing. Compat mode is also supported. Only the general purpose user space registers are exported, i.e.: PERF_REG_ARM_X0, ... PERF_REG_ARM_X28, PERF_REG_ARM_FP, PERF_REG_ARM_LR, PERF_REG_ARM_SP, PERF_REG_ARM_PC and not the PERF_REG_ARM_V* registers. Signed-off-by: Jean Pihet <jean.pihet(a)linaro.org> Cc: Will Deacon <will.deacon(a)arm.com> --- arch/arm64/Kconfig | 2 ++ arch/arm64/include/asm/ptrace.h | 1 + arch/arm64/include/uapi/asm/Kbuild | 1 + arch/arm64/include/uapi/asm/perf_regs.h | 40 ++++++++++++++++++++++++++++ arch/arm64/kernel/Makefile | 1 + arch/arm64/kernel/perf_regs.c | 46 +++++++++++++++++++++++++++++++++ 6 files changed, 91 insertions(+) create mode 100644 arch/arm64/include/uapi/asm/perf_regs.h create mode 100644 arch/arm64/kernel/perf_regs.c diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 88c8b6c1..f8609dc 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -28,6 +28,8 @@ config ARM64 select HAVE_HW_BREAKPOINT if PERF_EVENTS select HAVE_MEMBLOCK select HAVE_PERF_EVENTS + select HAVE_PERF_REGS + select HAVE_PERF_USER_STACK_DUMP select IRQ_DOMAIN select MODULES_USE_ELF_RELA select NO_BOOTMEM diff --git a/arch/arm64/include/asm/ptrace.h b/arch/arm64/include/asm/ptrace.h index 0e7fa49..fbb0020 100644 --- a/arch/arm64/include/asm/ptrace.h +++ b/arch/arm64/include/asm/ptrace.h @@ -68,6 +68,7 @@ /* Architecturally defined mapping between AArch32 and AArch64 registers */ #define compat_usr(x) regs[(x)] +#define compat_fp regs[11] #define compat_sp regs[13] #define compat_lr regs[14] #define compat_sp_hyp regs[15] diff --git a/arch/arm64/include/uapi/asm/Kbuild b/arch/arm64/include/uapi/asm/Kbuild index e4b78bd..942376d 100644 --- a/arch/arm64/include/uapi/asm/Kbuild +++ b/arch/arm64/include/uapi/asm/Kbuild @@ -9,6 +9,7 @@ header-y += byteorder.h header-y += fcntl.h header-y += hwcap.h header-y += kvm_para.h +header-y += perf_regs.h header-y += param.h header-y += ptrace.h header-y += setup.h diff --git a/arch/arm64/include/uapi/asm/perf_regs.h b/arch/arm64/include/uapi/asm/perf_regs.h new file mode 100644 index 0000000..06bf360 --- /dev/null +++ b/arch/arm64/include/uapi/asm/perf_regs.h @@ -0,0 +1,40 @@ +#ifndef _ASM_ARM_PERF_REGS_H +#define _ASM_ARM_PERF_REGS_H + +enum perf_event_arm_regs { + PERF_REG_ARM_X0, + PERF_REG_ARM_X1, + PERF_REG_ARM_X2, + PERF_REG_ARM_X3, + PERF_REG_ARM_X4, + PERF_REG_ARM_X5, + PERF_REG_ARM_X6, + PERF_REG_ARM_X7, + PERF_REG_ARM_X8, + PERF_REG_ARM_X9, + PERF_REG_ARM_X10, + PERF_REG_ARM_X11, + PERF_REG_ARM_X12, + PERF_REG_ARM_X13, + PERF_REG_ARM_X14, + PERF_REG_ARM_X15, + PERF_REG_ARM_X16, + PERF_REG_ARM_X17, + PERF_REG_ARM_X18, + PERF_REG_ARM_X19, + PERF_REG_ARM_X20, + PERF_REG_ARM_X21, + PERF_REG_ARM_X22, + PERF_REG_ARM_X23, + PERF_REG_ARM_X24, + PERF_REG_ARM_X25, + PERF_REG_ARM_X26, + PERF_REG_ARM_X27, + PERF_REG_ARM_X28, + PERF_REG_ARM_FP, + PERF_REG_ARM_LR, + PERF_REG_ARM_SP, + PERF_REG_ARM_PC, + PERF_REG_ARM_MAX, +}; +#endif /* _ASM_ARM_PERF_REGS_H */ diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile index 5ba2fd4..dffdd93 100644 --- a/arch/arm64/kernel/Makefile +++ b/arch/arm64/kernel/Makefile @@ -15,6 +15,7 @@ arm64-obj-$(CONFIG_COMPAT) += sys32.o kuser32.o signal32.o \ sys_compat.o arm64-obj-$(CONFIG_MODULES) += arm64ksyms.o module.o arm64-obj-$(CONFIG_SMP) += smp.o smp_spin_table.o +arm64-obj-$(CONFIG_PERF_EVENTS) += perf_regs.o arm64-obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o arm64-obj-$(CONFIG_HAVE_HW_BREAKPOINT)+= hw_breakpoint.o arm64-obj-$(CONFIG_EARLY_PRINTK) += early_printk.o diff --git a/arch/arm64/kernel/perf_regs.c b/arch/arm64/kernel/perf_regs.c new file mode 100644 index 0000000..d5c8fd7 --- /dev/null +++ b/arch/arm64/kernel/perf_regs.c @@ -0,0 +1,46 @@ +#include <linux/errno.h> +#include <linux/kernel.h> +#include <linux/perf_event.h> +#include <linux/bug.h> +#include <asm/perf_regs.h> +#include <asm/ptrace.h> + +u64 perf_reg_value(struct pt_regs *regs, int idx) +{ + if (WARN_ON_ONCE((u32)idx >= PERF_REG_ARM_MAX)) + return 0; + + /* + * Compat (i.e. 32 bit) mode: + * - PC has been set in the pt_regs struct in kernel_entry, + * - Handle FP, SP and LR here. + */ + if (compat_user_mode(regs)) { + if ((u32)idx == PERF_REG_ARM_FP) + return regs->compat_fp; + if ((u32)idx == PERF_REG_ARM_SP) + return regs->compat_sp; + if ((u32)idx == PERF_REG_ARM_LR) + return regs->compat_lr; + } + + return regs->regs[idx]; +} + +#define REG_RESERVED (~((1ULL << PERF_REG_ARM_MAX) - 1)) + +int perf_reg_validate(u64 mask) +{ + if (!mask || mask & REG_RESERVED) + return -EINVAL; + + return 0; +} + +u64 perf_reg_abi(struct task_struct *task) +{ + if (test_tsk_thread_flag(task, TIF_32BIT)) + return PERF_SAMPLE_REGS_ABI_32; + else + return PERF_SAMPLE_REGS_ABI_64; +} -- 1.7.11.7

11 years, 5 months

next boot: 31 pass, 0 fail (next-20131217)

by Kevin's boot bot

Automated DT boot report for various ARM defconfigs. Tree/Branch: next Git describe: next-20131217 Full Report =========== omap2plus_defconfig ------------------- am335x-boneblack PASS: 0 min 28.0 sec omap3-beagle-xm PASS: 0 min 53.8 sec am335x-bone PASS: 0 min 26.8 sec omap4-panda PASS: 1 min 4.6 sec omap4-panda-es PASS: 1 min 2.2 sec omap3-tobi,3730storm PASS: 0 min 24.6 sec omap3-tobi,3530overo PASS: 0 min 22.6 sec tegra_defconfig --------------- tegra30-beaver PASS: 0 min 17.0 sec imx_v6_v7_defconfig ------------------- imx6dl-wandboard,wand-dual PASS: 0 min 16.9 sec imx6dl-wandboard,wand-solo PASS: 0 min 20.4 sec imx6q-wandboard PASS: 0 min 15.5 sec sunxi_defconfig --------------- sun7i-a20-cubieboard2 PASS: 0 min 12.2 sec mvebu_defconfig --------------- armada-xp-openblocks-ax3-4 PASS: 0 min 22.1 sec armada-370-mirabox PASS: 0 min 20.5 sec multi_v7_defconfig ------------------ ste-snowball PASS: 0 min 33.4 sec tegra30-beaver PASS: 0 min 16.6 sec am335x-boneblack PASS: 0 min 24.8 sec omap3-beagle-xm PASS: 0 min 47.9 sec sun7i-a20-cubieboard2 PASS: 0 min 13.2 sec armada-370-mirabox PASS: 0 min 20.7 sec omap4-panda PASS: 1 min 8.1 sec omap4-panda-es PASS: 1 min 2.2 sec armada-xp-openblocks-ax3-4 PASS: 0 min 23.1 sec imx6dl-wandboard,wand-solo PASS: 0 min 16.6 sec am335x-bone PASS: 0 min 24.6 sec imx6q-wandboard PASS: 0 min 15.9 sec omap3-tobi,3730storm PASS: 0 min 22.9 sec imx6dl-wandboard,wand-dual PASS: 0 min 17.0 sec omap3-tobi,3530overo PASS: 0 min 20.5 sec u8500_defconfig --------------- ste-snowball PASS: 0 min 28.3 sec sama5_defconfig --------------- sama5d35ek PASS: 0 min 17.6 sec

11 years, 5 months

[PATCH] ACPI: explicitly initialize a value to silence compiler warning

by al.stone＠linaro.org

From: Al Stone <al.stone(a)linaro.org> In acpi_processor_resume(), the variable resumed_bm_rld is being used without being initialized, so initialize it. Signed-off-by: Al Stone <al.stone(a)linaro.org> --- drivers/acpi/processor_idle.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/acpi/processor_idle.c b/drivers/acpi/processor_idle.c index 597cdab..86d11a6 100644 --- a/drivers/acpi/processor_idle.c +++ b/drivers/acpi/processor_idle.c @@ -213,7 +213,7 @@ static int acpi_processor_suspend(void) static void acpi_processor_resume(void) { - u32 resumed_bm_rld; + u32 resumed_bm_rld = 0; acpi_read_bit_register(ACPI_BITREG_BUS_MASTER_RLD, &resumed_bm_rld); if (resumed_bm_rld == saved_bm_rld) -- 1.8.3.1

11 years, 5 months

[PATCH 00/10] Support VGIC save/restore using device control API

by Christoffer Dall

Implement save/restore of the VGIC state using the newer KVM Device Control API. This requries some number of changes to existing code in addition to actually supporting save/restore of the necessary state. The first patches (01-03) support creating the VGIC using the Device Control API. This change is necessary because there are no other suitable KVM APIs that we can leverage to access the VGIC state from user space and the device control API was crafted exactly for this purpose. Subsequent patches add the missing infrastructure and user space API pieces necessary to actually save and restore the VGIC state. The GIC v2.0 architecture specification already specifies registers that can be used to save and restore the complete VGIC state for suspend/resume purposes on real hardware, and we can reuse this interface for the VGIC. The API is therefore based on the memory-mapped register accesses defined in the specs. See the individual patches for details. The patches are based on kvm-arm-next with the arch timers save/restore patches applied: git://git.linaro.org/people/cdall/linux-kvm-arm.git timer-migrate-v4 This patch series based on the above can be cloned from: git://git.linaro.org/people/cdall/linux-kvm-arm.git vgic-migrate-v4 User space patches for QEMU have also been posted on the list, but an updated version is underway. Tested on Versatile Express TC2. Changelogs in the individual patches. Christoffer Dall (10): ARM: KVM: Allow creating the VGIC after VCPUs KVM: arm-vgic: Support KVM_CREATE_DEVICE for VGIC KVM: arm-vgic: Set base addr through device API irqchip: arm-gic: Define additional MMIO offsets and masks KVM: arm-vgic: Make vgic mmio functions more generic arm/arm64: kvm: Set vcpu->cpu to -1 on vcpu_put KVM: arm-vgic: Add vgic reg access from dev attr KVM: arm-vgic: Support unqueueing of LRs to the dist KVM: arm-vgic: Add GICD_SPENDSGIR and GICD_CPENDSGIR handlers KVM: arm-vgic: Support CPU interface reg access Documentation/virtual/kvm/api.txt | 7 +- Documentation/virtual/kvm/devices/arm-vgic.txt | 73 ++++ arch/arm/include/uapi/asm/kvm.h | 8 + arch/arm/kvm/arm.c | 17 +- include/kvm/arm_vgic.h | 2 +- include/linux/irqchip/arm-gic.h | 12 + include/linux/kvm_host.h | 1 + include/uapi/linux/kvm.h | 1 + virt/kvm/arm/vgic.c | 581 +++++++++++++++++++++++-- virt/kvm/kvm_main.c | 6 +- 10 files changed, 670 insertions(+), 38 deletions(-) create mode 100644 Documentation/virtual/kvm/devices/arm-vgic.txt -- 1.8.4.3

11 years, 5 months

[PATCH 3/3] ARM64: perf: add support for frame pointer unwinding in compat mode

by jean.pihet＠linaro.org

From: Jean Pihet <jean.pihet(a)linaro.org> When profiling a 32-bit application, user space callchain unwinding using the frame pointer is performed in compat mode. The code is taken over from the AARCH32 code and adapted to work on AARCH64. Signed-off-by: Jean Pihet <jean.pihet(a)linaro.org> --- arch/arm64/kernel/perf_event.c | 75 +++++++++++++++++++++++++++++++++++++----- 1 file changed, 67 insertions(+), 8 deletions(-) diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index 0e63c98..ac055be 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -1300,8 +1300,8 @@ early_initcall(init_hw_perf_events); * Callchain handling code. */ struct frame_tail { - struct frame_tail __user *fp; - unsigned long lr; + struct frame_tail __user *fp; + unsigned long lr; } __attribute__((packed)); /* @@ -1338,22 +1338,80 @@ user_backtrace(struct frame_tail __user *tail, return buftail.fp; } +/* + * The registers we're interested in are at the end of the variable + * length saved register structure. The fp points at the end of this + * structure so the address of this struct is: + * (struct compat_frame_tail *)(xxx->fp)-1 + * + * This code has been adapted from the ARM OProfile support. + */ +struct compat_frame_tail { + compat_uptr_t fp; // Is a (struct compat_frame_tail *) in compat mode + u32 sp; + u32 lr; +} __attribute__((packed)); + +static struct compat_frame_tail __user * +compat_user_backtrace(struct compat_frame_tail __user *tail, + struct perf_callchain_entry *entry) +{ + struct compat_frame_tail buftail; + unsigned long err; + + /* Also check accessibility of one struct frame_tail beyond */ + if (!access_ok(VERIFY_READ, tail, sizeof(buftail))) + return NULL; + + pagefault_disable(); + err = __copy_from_user_inatomic(&buftail, tail, sizeof(buftail)); + pagefault_enable(); + + if (err) + return NULL; + + perf_callchain_store(entry, buftail.lr); + + /* + * Frame pointers should strictly progress back up the stack + * (towards higher addresses). + */ + if (tail + 1 >= (struct compat_frame_tail __user *) + compat_ptr(buftail.fp)) + return NULL; + + return (struct compat_frame_tail __user *)compat_ptr(buftail.fp) - 1; +} + void perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) { - struct frame_tail __user *tail; - if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { /* We don't support guest os callchain now */ return; } perf_callchain_store(entry, regs->pc); - tail = (struct frame_tail __user *)regs->regs[29]; - while (entry->nr < PERF_MAX_STACK_DEPTH && - tail && !((unsigned long)tail & 0xf)) - tail = user_backtrace(tail, entry); + if (!compat_user_mode(regs)) { + /* AARCH64 mode */ + struct frame_tail __user *tail; + + tail = (struct frame_tail __user *)regs->regs[29]; + + while (entry->nr < PERF_MAX_STACK_DEPTH && + tail && !((unsigned long)tail & 0xf)) + tail = user_backtrace(tail, entry); + } else { + /* AARCH32 compat mode */ + struct compat_frame_tail __user *tail; + + tail = (struct compat_frame_tail __user *)regs->compat_fp - 1; + + while ((entry->nr < PERF_MAX_STACK_DEPTH) && + tail && !((unsigned long)tail & 0x3)) + tail = compat_user_backtrace(tail, entry); + } } /* @@ -1381,6 +1439,7 @@ void perf_callchain_kernel(struct perf_callchain_entry *entry, frame.fp = regs->regs[29]; frame.sp = regs->sp; frame.pc = regs->pc; + walk_stackframe(&frame, callchain_trace, entry); } -- 1.7.11.7

11 years, 5 months

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