- A few trivial renames requested by Catalin
- Pass cluster_id around by value outside of parse_cluster
arm64: topology: Implement basic CPU topology support
arm64: topology: Add support for topology DT bindings
arm64: topology: Tell the scheduler about the relative
arm64: topology: Provide relative power numbers for cores
Mark & Catalin,
Could you like to review the merge conflict patch, which at:
git://git.linaro.org/kernel/linux-linaro-stable.git linux-linaro-lsk-test
===
commit 450cdfa9c5713551ab1438ab210679868b52a994
Merge: bf78886 8b4ed85
Author: Alex Shi <alex.shi(a)linaro.org>
Date: Fri Jan 10 10:50:57 2014 +0800
Merge remote-tracking branch 'stable/linux-3.10.y' into linux-linaro-lsk
Conflicts:
arch/arm64/kernel/smp.c
Signed-off-by: Alex Shi <alex.shi(a)linaro.org>
diff --cc arch/arm64/kernel/smp.c
index 5e9d274,9c93e12..87340fd
--- a/arch/arm64/kernel/smp.c
+++ b/arch/arm64/kernel/smp.c
@@@ -150,17 -187,17 +150,10 @@@ asmlinkage void __cpuinit secondary_sta
preempt_disable();
trace_hardirqs_off();
- /*
- * Let the primary processor know we're out of the
- * pen, then head off into the C entry point
- */
- write_pen_release(INVALID_HWID);
+ if (cpu_ops[cpu]->cpu_postboot)
+ cpu_ops[cpu]->cpu_postboot();
-- /*
- * Enable local interrupts.
- */
- notify_cpu_starting(cpu);
- local_irq_enable();
- local_fiq_enable();
-
- * Synchronise with the boot thread.
- */
- raw_spin_lock(&boot_lock);
- raw_spin_unlock(&boot_lock);
+ smp_store_cpu_info(cpu);
/*
* OK, now it's safe to let the boot CPU continue. Wait for
From: Victor Kamensky <victor.kamensky(a)linaro.org>
If kernel operates in BE mode on device that has LE bootloader/ROM code,
we need to switch CPU to operate in BE mode before it will start to
access BE data. Generic secondary_startup function that is called from
OMAP specific secondary startup code will do the switch, but we need
to do it earlier because OMAP's secondary_startup code works with BE data.
Signed-off-by: Victor Kamensky <victor.kamensky(a)linaro.org>
Signed-off-by: Taras Kondratiuk <taras.kondratiuk(a)linaro.org>
---
This is a part of RFC series [1].
Based on v3.13-rc8.
[1] http://www.spinics.net/lists/linux-omap/msg99927.html
arch/arm/mach-omap2/omap-headsmp.S | 13 +++++++++++++
arch/arm/mach-omap2/sleep44xx.S | 6 ++++++
2 files changed, 19 insertions(+)
diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S
index 75e9295..75c98d4 100644
--- a/arch/arm/mach-omap2/omap-headsmp.S
+++ b/arch/arm/mach-omap2/omap-headsmp.S
@@ -17,6 +17,7 @@
#include <linux/linkage.h>
#include <linux/init.h>
+#include <asm/assembler.h>
#include "omap44xx.h"
@@ -58,6 +59,12 @@ hold: ldr r12,=0x103
bne hold
/*
+ * ROM code operates in little endian mode, when we get control we
+ * need to switch it back to big endian mode.
+ */
+ARM_BE8(setend be)
+
+ /*
* we've been released from the wait loop,secondary_stack
* should now contain the SVC stack for this core
*/
@@ -75,6 +82,12 @@ hold_2: ldr r12,=0x103
bne hold_2
/*
+ * ROM code operates in little endian mode, when we get control we
+ * need to switch it back to big endian mode.
+ */
+ARM_BE8(setend be)
+
+ /*
* GIC distributor control register has changed between
* CortexA9 r1pX and r2pX. The Control Register secure
* banked version is now composed of 2 bits:
diff --git a/arch/arm/mach-omap2/sleep44xx.S b/arch/arm/mach-omap2/sleep44xx.S
index 9086ce0..e556c8b 100644
--- a/arch/arm/mach-omap2/sleep44xx.S
+++ b/arch/arm/mach-omap2/sleep44xx.S
@@ -249,6 +249,12 @@ ENDPROC(omap4_finish_suspend)
*/
ENTRY(omap4_cpu_resume)
/*
+ * ROM code operates in little endian mode, when we get control we
+ * need to switch it back to big endian mode.
+ */
+ARM_BE8(setend be)
+
+ /*
* Configure ACTRL and enable NS SMP bit access on CPU1 on HS device.
* OMAP44XX EMU/HS devices - CPU0 SMP bit access is enabled in PPA
* init and for CPU1, a secure PPA API provided. CPU0 must be ON
--
1.7.9.5
This patchset does a cleanup on the parameters passed from the function
'trigger_load_balance' to the underneath functions.
The cpu is passed as parameter to the different functions as well as the struct
rq but this one contains already the cpu information. Moreover, in the call
stack for these functions, we have the struct rq retrieved from the cpu, and then
the cpu retrieve from the struct rq, etc ...
The patchset unifies all these functions to have a struct rq parameter and
removes the pointless parameters.
-static inline int find_new_ilb(int call_cpu)
+static inline int find_new_ilb(void)
-static void nohz_balancer_kick(int cpu)
+static void nohz_balancer_kick(void)
-static void rebalance_domains(int cpu, enum cpu_idle_type idle)
+static void rebalance_domains(struct rq *rq, enum cpu_idle_type idle)
-static void nohz_idle_balance(int this_cpu, enum cpu_idle_type idle)
+static void nohz_idle_balance(struct rq *this_rq, enum cpu_idle_type idle)
-static inline int nohz_kick_needed(struct rq *rq, int cpu)
+static inline int nohz_kick_needed(struct rq *rq)
-static inline int on_null_domain(int cpu)
+static inline int on_null_domain(struct rq *rq)
Changelog:
V2:
- added missing patch 1/8
- added acked-by from Preeti U Murthy for patch 4 and 5
Daniel Lezcano (8):
sched: reduce trigger_load_balance parameters
sched: reduce nohz_kick_needed parameters
sched: pass struct rq to on_null_domain function
sched: remove unused parameter for find_new_ilb
sched: remove unused parameter in nohz_balancer_kick function
sched: pass struct rq to rebalance_domains function
sched: pass struct rq to nohz_idle_balance function
sched: factor out on_null_domain check in trigger_load_balance
function
kernel/sched/core.c | 2 +-
kernel/sched/fair.c | 45 +++++++++++++++++++++++----------------------
kernel/sched/sched.h | 2 +-
3 files changed, 25 insertions(+), 24 deletions(-)
--
1.7.9.5
On 28 December 2013 00:14, Greg KH <gregkh(a)linuxfoundation.org> wrote:
> On Fri, Dec 27, 2013 at 03:47:31PM +0530, Tushar Behera wrote:
>> On 27 December 2013 12:08, Greg KH <gregkh(a)linuxfoundation.org> wrote:
>> > On Fri, Dec 27, 2013 at 12:00:20PM +0530, Tushar Behera wrote:
>> >> On 27 December 2013 10:48, Greg KH <gregkh(a)linuxfoundation.org> wrote:
>> >> > On Fri, Dec 27, 2013 at 10:37:28AM +0530, Tushar Behera wrote:
>>
>> [ ... ]
>>
>> >> >> @@ -951,8 +949,6 @@ static struct uart_driver s3c24xx_uart_drv = {
>> >> >> .nr = CONFIG_SERIAL_SAMSUNG_UARTS,
>> >> >> .cons = S3C24XX_SERIAL_CONSOLE,
>> >> >> .dev_name = S3C24XX_SERIAL_NAME,
>> >> >> - .major = S3C24XX_SERIAL_MAJOR,
>> >> >> - .minor = S3C24XX_SERIAL_MINOR,
>> >> >
>> >> > Doesn't this break existing systems and configurations that are
>> >> > expecting 204:64 as the location of this serial port?
>> >> >
>> >>
>> >> I tested this on Exynos4210-Origen, Exynos5250-Arndale board, it works
>> >> fine there. I haven't tested on any older boards.
>> >
>> > How did it work? You are relying on some userspace tools to do this
>> > properly, right? What about systems without those specific tools?
>> >
>>
>> Enabling CONFIG_DEVTMPFS, all the /dev/ttySAC<n> nodes are generated
>> and the appropriate console is specified through command line
>> argument.
>
> But what about systems that rely on a hard-coded /dev?
>
> Look, I'm all for making everyone use devtmpfs, but just changing
> major:minor numbers for drivers isn't ok, as you are changing the
> userspace ABI for the device.
>
> Please realize what you are asking for here, I really don't think you
> grasp it given that you didn't ask any of the maintainers of this driver
> about the change in the first place.
>
> Please get approval for this patch from others within Linaro before
> sending it out again. Linaro has a process in place for this type of
> thing, please use it, otherwise it makes people like me really grumpy
> and upset and causes me to yell at people at their conferences.
>
> greg k-h
Asking for opinion about this ... Without this patch, I can't get
serial console to come up on Exynos platforms when amba-pl011 driver
enabled. But Greg is particularly not at all happy with this patch.
Any comments with respect to fixing this issue would be highly
appreciated.
Attaching the complete patch for reference.
--
Tushar Behera
Reworked initial Ben's series for big endian support [1].
Dropped patches that are not directly related to kprobes.
Current set of patches is enough to have functional BE kprobes.
One ARM kprobe test fails on Cortex-A15 boards (TC2 and Keystone2 EVM),
while it passes on Pandaboard. The issue is not related to this series
and already present in v3.13-rc7. I'll try to look into it later.
v1..v2: Fixed coprocessor instruction building for ARM tests in the patch
"ARM: kprobes-test: use <asm/opcodes.h> for ARM instruction building"
Based on v3.13-rc7.
[1] http://www.spinics.net/lists/arm-kernel/msg285210.html
Ben Dooks (4):
ARM: kprobes: fix instruction fetch order with <asm/opcodes.h>
ARM: kprobes-test: use <asm/opcodes.h> for instruction accesses
ARM: kprobes-test: use <asm/opcodes.h> for ARM instruction building
ARM: kprobes-test: use <asm/opcodes.h> for Thumb instruction building
Taras Kondratiuk (1):
ARM: kprobes-test: Workaround GAS .align bug
arch/arm/kernel/kprobes-common.c | 19 +-
arch/arm/kernel/kprobes-test-arm.c | 603 +++++++++++++++++-----------------
arch/arm/kernel/kprobes-test-thumb.c | 447 ++++++++++++-------------
arch/arm/kernel/kprobes-test.c | 13 +-
arch/arm/kernel/kprobes-test.h | 2 +-
arch/arm/kernel/kprobes-thumb.c | 20 +-
arch/arm/kernel/kprobes.c | 9 +-
7 files changed, 562 insertions(+), 551 deletions(-)
--
1.7.9.5