This patch set trys to make ACPI core running on ARM64.
1. Why ACPI is needed ?
ACPI provides standard interfaces for power managment, themal
control, device enumeration and configuration and etc. So ACPI
can make OS and hardware decoupling and make people upgrade
software or hardware more easily.
ACPI is more than that. It can provide standard error report
interface called ACPI Platform Error Interface (APEI) for
RAS features, and provide standard interface for dynamic
system device reconfigurations such as CPU/memory/computer
node hot-add and hot-remove, this is especially useful
for servers.
2. Does ACPI run propably on ARM64 ?
ACPI spec 5.0 introduces hardware reduced mode, GICC/GICD,
GTDT for arch timer and etc for Socs.
This makes it possible to run ACPI on ARM/ARM64. Some
company already did that (UEFI+ACPI) on ARM platforms.
ACPI spec for ARM/ARM64 is still need to be improved and
people are working on that, but for now, we can run ACPI
propably except for some new features such as PSCI and
GICv3.
3. What we did in this patch set
patch 1-8(Hanjun Guo) will make ACPI core running on ARM64 and
make the compilation is ok on ARM64.
patch 9-12 will enumeration cpus presented by MADT table.
since PSCI is not available for ACPI 5.0, we use spin-table
method for SMP initialization.
patch 13-16 will initialize GIC in the system. ACPI only
support one GIC and only report information about GICC and
GICD, so there will some limitations for GICv3 and GICH
for GICv2 for virtualization.
patch 17-19 and patch from Amit will finish the arch timer
initialization. We get informatiom from GTDT
(Generic Timer Description Table) to initialize arch timer
and introduce a macro CLOCKSOURCE_ACPI_DECLARE to do the
same job as CLOCKSOURCE_OF_DECLARE to make it scalable for
other timers.
All the ACPI tables are available with BSD license at:
git://git.linaro.org/arm/acpi/acpi-asl.git
Changs since last RFC version:
1) Introduce some PCI functions when PCI is enabled
2) Select ACPI_REDUCED_HARDWARE_ONLY if ACPI is enabled
3) Remove ACPI based CPU hotplug code
4) Use spin-table method for SMP initialization
5) Add macro CLOCKSOURCE_ACPI_DECLARE for ACPI timer init
6) Address lots of comments and suggestions in last RFC version
7) Remove RFC tag and make all the patches seperated as two
parts, one is "ACPI: Some patches to prepare for running ACPI
on !x86 and !ia64", and another is this one.
8) Rebased on 3.13-rc8.
Amit Daniel Kachhap (1):
clocksource / acpi: Add macro CLOCKSOURCE_ACPI_DECLARE
Hanjun Guo (19):
ARM64 / ACPI: Make PCI optional for ACPI on ARM64
ARM64 : Add dummy asm/cpu.h
ARM64 / ACPI: Introduce the skeleton of _PDC related for ARM64
ARM64 / ACPI: Introduce arm_core.c and its related head file
ARM64 / ACPI: Introduce lowlevel suspend function
ARM64 / ACPI: Introduce some PCI functions when PCI is enabled
ARM64 / ACPI: Enable ARM64 in Kconfig
ARM64 / ACPI: Select ACPI_REDUCED_HARDWARE_ONLY if ACPI is enabled on
ARM64
ARM64 / ACPI: Implement core functions for parsing MADT table
ARM64 / ACPI: Enumerate possible/present CPU set and map logical cpu
id to APIC id
ARM64 / ACPI: Get the enable method for SMP initialization
ARM64 / ACPI: Use Parked Address in GIC structure for spin table SMP
initialisation
ARM64 / ACPI: Define ACPI_IRQ_MODEL_GIC needed for arm
Irqchip / gic: Set as default domain so we can access from ACPI
ACPI / ARM64: Update acpi_register_gsi to register with the core IRQ
subsystem
ACPI / GIC: Initialize GIC using the information in MADT
clocksource / arch_timer: Use ACPI GTDT table to initialize arch
timer
clocksource / ACPI: Introduce clocksource_acpi_init() using
CLOCKSOURCE_ACPI_DECLARE
ARM64 / clocksource: Use clocksource_acpi_init()
arch/arm64/Kconfig | 3 +
arch/arm64/Makefile | 1 +
arch/arm64/include/asm/acpi.h | 112 +++++++
arch/arm64/include/asm/cpu.h | 25 ++
arch/arm64/include/asm/cpu_ops.h | 1 +
arch/arm64/include/asm/pci.h | 20 ++
arch/arm64/include/asm/processor.h | 2 +
arch/arm64/include/asm/smp.h | 2 +-
arch/arm64/kernel/cpu_ops.c | 2 +-
arch/arm64/kernel/irq.c | 6 +
arch/arm64/kernel/process.c | 3 +
arch/arm64/kernel/setup.c | 6 +
arch/arm64/kernel/smp.c | 42 ++-
arch/arm64/kernel/smp_spin_table.c | 12 +-
arch/arm64/kernel/time.c | 6 +
arch/arm64/pci/Makefile | 1 +
arch/arm64/pci/pci.c | 33 ++
drivers/acpi/Kconfig | 11 +-
drivers/acpi/Makefile | 4 +-
drivers/acpi/bus.c | 3 +
drivers/acpi/internal.h | 7 +
drivers/acpi/osl.c | 3 +-
drivers/acpi/plat/Makefile | 1 +
drivers/acpi/plat/arm-core.c | 599 ++++++++++++++++++++++++++++++++++
drivers/acpi/tables.c | 21 ++
drivers/clocksource/Makefile | 1 +
drivers/clocksource/arm_arch_timer.c | 101 +++++-
drivers/clocksource/clksrc-acpi.c | 36 ++
drivers/irqchip/irq-gic.c | 7 +
include/asm-generic/vmlinux.lds.h | 10 +
include/linux/acpi.h | 7 +
include/linux/clocksource.h | 15 +
include/linux/pci.h | 33 +-
33 files changed, 1099 insertions(+), 37 deletions(-)
create mode 100644 arch/arm64/include/asm/acpi.h
create mode 100644 arch/arm64/include/asm/cpu.h
create mode 100644 arch/arm64/include/asm/pci.h
create mode 100644 arch/arm64/pci/Makefile
create mode 100644 arch/arm64/pci/pci.c
create mode 100644 drivers/acpi/plat/Makefile
create mode 100644 drivers/acpi/plat/arm-core.c
create mode 100644 drivers/clocksource/clksrc-acpi.c
--
1.7.9.5
From: Mark Brown <broonie(a)linaro.org>
This will help support future enhancements in the way we negotiate
parameters in the core.
Signed-off-by: Mark Brown <broonie(a)linaro.org>
---
sound/soc/codecs/pcm1681.c | 15 ++++++++++-----
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/sound/soc/codecs/pcm1681.c b/sound/soc/codecs/pcm1681.c
index 73f9c3630e2c..e427544183d7 100644
--- a/sound/soc/codecs/pcm1681.c
+++ b/sound/soc/codecs/pcm1681.c
@@ -172,16 +172,21 @@ static int pcm1681_hw_params(struct snd_pcm_substream *substream,
struct snd_soc_codec *codec = dai->codec;
struct pcm1681_private *priv = snd_soc_codec_get_drvdata(codec);
int val = 0, ret;
- int pcm_format = params_format(params);
priv->rate = params_rate(params);
switch (priv->format & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_RIGHT_J:
- if (pcm_format == SNDRV_PCM_FORMAT_S24_LE)
- val = 0x00;
- else if (pcm_format == SNDRV_PCM_FORMAT_S16_LE)
- val = 0x03;
+ switch (params_width(params)) {
+ case 24:
+ val = 0;
+ break;
+ case 16:
+ val = 3;
+ break;
+ default:
+ return -EINVAL;
+ }
break;
case SND_SOC_DAIFMT_I2S:
val = 0x04;
--
1.8.5.3
From: Mark Brown <broonie(a)linaro.org>
There is no meaningful code sharing between the PIO and DMA variants
(just the timeout calculation) so in order to make the code easier to
work with split the two cases.
Looking at the code it is not clear how the PIO version works for large
transmits, greater than FIFO size is only handled for RX.
Signed-off-by: Mark Brown <broonie(a)linaro.org>
---
drivers/spi/spi-s3c64xx.c | 166 +++++++++++++++++++++++++---------------------
1 file changed, 89 insertions(+), 77 deletions(-)
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index 19113538f5c6..b9ba7a3e7741 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -677,101 +677,110 @@ static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd,
return RX_FIFO_LVL(status, sdd);
}
-static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,
- struct spi_transfer *xfer, int dma_mode)
+static int wait_for_dma(struct s3c64xx_spi_driver_data *sdd,
+ struct spi_transfer *xfer)
{
void __iomem *regs = sdd->regs;
unsigned long val;
+ u32 status;
int ms;
/* millisecs to xfer 'len' bytes @ 'cur_speed' */
ms = xfer->len * 8 * 1000 / sdd->cur_speed;
ms += 10; /* some tolerance */
- if (dma_mode) {
- val = msecs_to_jiffies(ms) + 10;
- val = wait_for_completion_timeout(&sdd->xfer_completion, val);
- } else {
- u32 status;
- val = msecs_to_loops(ms);
- do {
+ val = msecs_to_jiffies(ms) + 10;
+ val = wait_for_completion_timeout(&sdd->xfer_completion, val);
+
+ /*
+ * If the previous xfer was completed within timeout, then
+ * proceed further else return -EIO.
+ * DmaTx returns after simply writing data in the FIFO,
+ * w/o waiting for real transmission on the bus to finish.
+ * DmaRx returns only after Dma read data from FIFO which
+ * needs bus transmission to finish, so we don't worry if
+ * Xfer involved Rx(with or without Tx).
+ */
+ if (val && !xfer->rx_buf) {
+ val = msecs_to_loops(10);
+ status = readl(regs + S3C64XX_SPI_STATUS);
+ while ((TX_FIFO_LVL(status, sdd)
+ || !S3C64XX_SPI_ST_TX_DONE(status, sdd))
+ && --val) {
+ cpu_relax();
status = readl(regs + S3C64XX_SPI_STATUS);
- } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
+ }
+
}
- if (dma_mode) {
- u32 status;
-
- /*
- * If the previous xfer was completed within timeout, then
- * proceed further else return -EIO.
- * DmaTx returns after simply writing data in the FIFO,
- * w/o waiting for real transmission on the bus to finish.
- * DmaRx returns only after Dma read data from FIFO which
- * needs bus transmission to finish, so we don't worry if
- * Xfer involved Rx(with or without Tx).
- */
- if (val && !xfer->rx_buf) {
- val = msecs_to_loops(10);
- status = readl(regs + S3C64XX_SPI_STATUS);
- while ((TX_FIFO_LVL(status, sdd)
- || !S3C64XX_SPI_ST_TX_DONE(status, sdd))
- && --val) {
- cpu_relax();
- status = readl(regs + S3C64XX_SPI_STATUS);
- }
+ /* If timed out while checking rx/tx status return error */
+ if (!val)
+ return -EIO;
- }
+ return 0;
+}
- /* If timed out while checking rx/tx status return error */
- if (!val)
- return -EIO;
- } else {
- int loops;
- u32 cpy_len;
- u8 *buf;
-
- /* If it was only Tx */
- if (!xfer->rx_buf) {
- sdd->state &= ~TXBUSY;
- return 0;
- }
+static int wait_for_pio(struct s3c64xx_spi_driver_data *sdd,
+ struct spi_transfer *xfer)
+{
+ void __iomem *regs = sdd->regs;
+ unsigned long val;
+ u32 status;
+ int loops;
+ u32 cpy_len;
+ u8 *buf;
+ int ms;
- /*
- * If the receive length is bigger than the controller fifo
- * size, calculate the loops and read the fifo as many times.
- * loops = length / max fifo size (calculated by using the
- * fifo mask).
- * For any size less than the fifo size the below code is
- * executed atleast once.
- */
- loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1);
- buf = xfer->rx_buf;
- do {
- /* wait for data to be received in the fifo */
- cpy_len = s3c64xx_spi_wait_for_timeout(sdd,
- (loops ? ms : 0));
+ /* millisecs to xfer 'len' bytes @ 'cur_speed' */
+ ms = xfer->len * 8 * 1000 / sdd->cur_speed;
+ ms += 10; /* some tolerance */
- switch (sdd->cur_bpw) {
- case 32:
- ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
- buf, cpy_len / 4);
- break;
- case 16:
- ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
- buf, cpy_len / 2);
- break;
- default:
- ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
- buf, cpy_len);
- break;
- }
+ val = msecs_to_loops(ms);
+ do {
+ status = readl(regs + S3C64XX_SPI_STATUS);
+ } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
- buf = buf + cpy_len;
- } while (loops--);
- sdd->state &= ~RXBUSY;
+
+ /* If it was only Tx */
+ if (!xfer->rx_buf) {
+ sdd->state &= ~TXBUSY;
+ return 0;
}
+ /*
+ * If the receive length is bigger than the controller fifo
+ * size, calculate the loops and read the fifo as many times.
+ * loops = length / max fifo size (calculated by using the
+ * fifo mask).
+ * For any size less than the fifo size the below code is
+ * executed atleast once.
+ */
+ loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1);
+ buf = xfer->rx_buf;
+ do {
+ /* wait for data to be received in the fifo */
+ cpy_len = s3c64xx_spi_wait_for_timeout(sdd,
+ (loops ? ms : 0));
+
+ switch (sdd->cur_bpw) {
+ case 32:
+ ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
+ buf, cpy_len / 4);
+ break;
+ case 16:
+ ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
+ buf, cpy_len / 2);
+ break;
+ default:
+ ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
+ buf, cpy_len);
+ break;
+ }
+
+ buf = buf + cpy_len;
+ } while (loops--);
+ sdd->state &= ~RXBUSY;
+
return 0;
}
@@ -928,7 +937,10 @@ static int s3c64xx_spi_transfer_one(struct spi_master *master,
spin_unlock_irqrestore(&sdd->lock, flags);
- status = wait_for_xfer(sdd, xfer, use_dma);
+ if (use_dma)
+ status = wait_for_dma(sdd, xfer);
+ else
+ status = wait_for_pio(sdd, xfer);
if (status) {
dev_err(&spi->dev, "I/O Error: rx-%d tx-%d res:rx-%c tx-%c len-%d\n",
--
1.8.5.3