Add AARCH64 specific support. This includes the following:
- AARCH64 perf registers definition and hooks,
- compat mode registers use, i.e. profiling a 32-bit binary on
a 64-bit system,
- unwinding using the dwarf information from the .debug_frame
section of the ELF binary,
- unwinding using the frame pointer information; in 64-bit and
compat modes.
Notes:
- the tools/perf change is submitted separately on LKML,
- support for unwinding using the dwarf information in compat
mode requires some changes to the libunwind code. Those changes
have been submitted on the libunwind ML and are in discussion.
Tested on ARMv7, ARMv8 and x86_64 platforms. The compat mode has been
tested on ARMv8 using statically built 32-bit binaries.
Jean Pihet (3):
ARM64: perf: add support for perf registers API
ARM64: perf: add support for frame pointer unwinding in compat mode
ARM64: perf: support dwarf unwinding in compat mode
arch/arm64/Kconfig | 2 +
arch/arm64/include/asm/compat.h | 2 +-
arch/arm64/include/asm/ptrace.h | 3 +-
arch/arm64/include/uapi/asm/Kbuild | 1 +
arch/arm64/include/uapi/asm/perf_regs.h | 40 ++++++++++++++++++
arch/arm64/kernel/Makefile | 1 +
arch/arm64/kernel/perf_event.c | 75 +++++++++++++++++++++++++++++----
arch/arm64/kernel/perf_regs.c | 44 +++++++++++++++++++
8 files changed, 158 insertions(+), 10 deletions(-)
create mode 100644 arch/arm64/include/uapi/asm/perf_regs.h
create mode 100644 arch/arm64/kernel/perf_regs.c
--
1.7.11.7
From: Mark Brown <broonie(a)linaro.org>
regmap should handle any byte ordering issues required, it is looking for
a byte stream from the bus, so don't set 16 bits per word. This is likely
to have tested out OK due to use of an unmerged SPI controller driver.
Signed-off-by: Mark Brown <broonie(a)linaro.org>
---
sound/soc/codecs/tlv320aic23-spi.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/sound/soc/codecs/tlv320aic23-spi.c b/sound/soc/codecs/tlv320aic23-spi.c
index 585aea436c6a..3b387e41d75d 100644
--- a/sound/soc/codecs/tlv320aic23-spi.c
+++ b/sound/soc/codecs/tlv320aic23-spi.c
@@ -25,7 +25,6 @@ static int aic23_spi_probe(struct spi_device *spi)
dev_dbg(&spi->dev, "probing tlv320aic23 spi device\n");
- spi->bits_per_word = 16;
spi->mode = SPI_MODE_0;
ret = spi_setup(spi);
if (ret < 0)
--
1.9.0
From: Mark Brown <broonie(a)linaro.org>
Probably due to rebasing over the lengthy time it took to get the patch
merged commit addea9ef055b (cpufreq: enable ARM drivers on arm64) added
a duplicate Power management options section. Add CPUfreq to the CPU
power management section and remove a duplicate include of the main
power section.
Signed-off-by: Mark Brown <broonie(a)linaro.org>
---
arch/arm64/Kconfig | 6 ------
1 file changed, 6 deletions(-)
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index a3c40d65128b..2474c24dc229 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -318,12 +318,6 @@ menu "CPU Power Management"
source "drivers/cpuidle/Kconfig"
-endmenu
-
-menu "Power management options"
-
-source "kernel/power/Kconfig"
-
source "drivers/cpufreq/Kconfig"
endmenu
--
1.9.0
Adding libdw DWARF post unwind support, which is part
of elfutils-devel/libdw-dev package from version 0.158.
Also includes the test suite for dwarf unwinding, by adding the
arch specific test code and the perf_regs_load function.
Jean Pihet (3):
perf tests: Introduce perf_regs_load function on ARM
perf tests: Add dwarf unwind test on ARM
perf tools: Add libdw DWARF post unwind support for ARM
tools/perf/Makefile.perf | 2 +-
tools/perf/arch/arm/Makefile | 7 ++++
tools/perf/arch/arm/include/perf_regs.h | 5 +++
tools/perf/arch/arm/tests/dwarf-unwind.c | 59 ++++++++++++++++++++++++++++++++
tools/perf/arch/arm/tests/regs_load.S | 51 +++++++++++++++++++++++++++
tools/perf/arch/arm/util/unwind-libdw.c | 36 +++++++++++++++++++
tools/perf/tests/builtin-test.c | 2 +-
tools/perf/tests/tests.h | 2 +-
8 files changed, 161 insertions(+), 3 deletions(-)
create mode 100644 tools/perf/arch/arm/tests/dwarf-unwind.c
create mode 100644 tools/perf/arch/arm/tests/regs_load.S
create mode 100644 tools/perf/arch/arm/util/unwind-libdw.c
---
- Rebased on latest acme/perf/core git tree,
- Tested on quad-core ARMv7 machine
--
1.7.11.7
The cpu_load decays on time according past cpu load of rq. The sched_avg
also decays tasks' load on time. Now we has 2 kind decay for cpu_load.
That is a kind of redundancy. And increase the system load by decay
calculation. This patch try to remove the cpu_load decay.
There are 5 load_idx used for cpu_load in sched_domain. busy_idx and
idle_idx are not zero usually, but newidle_idx, wake_idx and forkexec_idx
are all zero on every arch. A shortcut to remove cpu_Load decay in the first
patch. just one line patch for this change. Then I try to clean up code
followed by this change.
V4,
1, rebase on latest tip/master
2, replace target_load by biased_load as Morten's suggestion
V3,
1, correct the wake_affine bias. Thanks for Morten's reminder!
2, replace source_load by weighted_cpuload for better function name meaning.
V2,
1, This version do some tuning on load bias of target load.
2, Got further to remove the cpu_load in rq.
3, Revert the patch 'Limit sd->*_idx range on sysctl' since no needs
Any testing/comments are appreciated.
This patch rebase on latest tip/master.
The git tree for this patchset at:
git@github.com:alexshi/power-scheduling.git noload
Thanks
Alex
[PATCH 01/11] sched: shortcut to remove load_idx
[PATCH 02/11] sched: remove rq->cpu_load[load_idx] array
[PATCH 03/11] sched: clean up cpu_load update
[PATCH 04/11] sched: unify imbalance bias for target group
[PATCH 05/11] sched: rewrite update_cpu_load_nohz
[PATCH 06/11] sched: clean up source_load/target_load
[PATCH 07/11] sched: replace source_load by weighted_cpuload
[PATCH 08/11] sched: replace target_load by biased_load
[PATCH 09/11] sched: remove rq->cpu_load and rq->nr_load_updates
[PATCH 10/11] sched: rename update_*_cpu_load
[PATCH 11/11] sched: clean up task_hot function
