Configs ARM_PATCH_PHYS_VIRT and AUTO_ZRELADDR are enabled as default
to S3C64XX platform
Introduction of PHYS_VIRT config as default would enable phy-to-virt and
virt-to-phy translation function at boot and module loading time
and enforce dynamic reallocation of memory. AUTO_ZRELADDR config would
enable calculation of kernel load address at run time.
PHYS_VIRT config is mutually exclusive to XIP_KERNEL, XIP_KERNEL is used in
systems with NOR flash devices, and ZRELADDR config is mutually exclusive
to ZBOOT_ROM.
CFT::Call For Testing
Requesting maintainers of S3C64XX platforms to evaluate the changes on the
board and comment, as I dont have the board for testing and also requesting
an ACK the changes.
Signed-off-by: panchaxari <panchaxari.prasannamurthy(a)linaro.org>
Cc: Mark Brown <broonie(a)linaro.org>
Cc: Tomasz Figa <tomasz.figa(a)gmail.com>
Cc: Ben Dooks <ben-linux(a)fluff.org>
Cc: Kukjin Kim <kgene.kim(a)samsung.com>
Cc: Russell King <linux(a)arm.linux.org.uk>
Cc: Linus Walleij <linus.walleij(a)linaro.org>
Cc: linux-arm-kernel(a)lists.infradead.org
Cc: linux-samsung-soc(a)vger.kernel.org
Cc: linux-kernel(a)vger.kernel.org
---
This is basically a Samsung SOC with ARM1176JZF-S instruction set, and has
an operating frquency of 667MHz, it also has 64bit AXI bus. It supports
WinCE, Linux, Android and Ubuntu.
This platform has two variants of CPU, S3C6400 and S3C6410.
This SOC is an Integrated system for Mobile Internet Device, Notebook,
handheld/3G mobile devices.
Supports various types of ROM for booting (NOR/NAND Flash, OneNand, SD-card
and others).
Below lkml link is a quoting by Russell which clears the concept of PHYS_VIRT
and ZRELADDR
---------------------------------------------------
https://lkml.org/lkml/2011/10/14/434
-------------------------------------------------
---
arch/arm/Kconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 7c6247b..ec1faea 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -731,7 +731,9 @@ config ARCH_S3C64XX
bool "Samsung S3C64XX"
select ARCH_HAS_CPUFREQ
select ARCH_REQUIRE_GPIOLIB
+ select ARM_PATCH_PHYS_VIRT
select ARM_VIC
+ select AUTO_ZRELADDR
select CLKDEV_LOOKUP
select CLKSRC_SAMSUNG_PWM
select COMMON_CLK
--
1.7.10.4
ARM_PATCH_PHYS_VIRT and AUTO_ZRELADDR have been enabled as default configs
to S5PC100 platform
Introduction of PHYS_VIRT config as default would enable phy-to-virt and
virt-to-phy translation function at boot and module loading time
and enforce dynamic reallocation of memory. AUTO_ZRELADDR config would
enable calculation of kernel load address at run time.
PHYS_VIRT config is mutually exclusive to XIP_KERNEL, XIP_KERNEL is used in
systems with NOR flash devices, and ZRELADDR config is mutually exclusive
to ZBOOT_ROM.
CFT::Call For Testing
Requesting maintainers of S5PC100 platforms to evaluate the changes on the board
and comment, as I dont have the board for testing and also requesting an ACK.
Signed-off-by: panchaxari <panchaxari.prasannamurthy(a)linaro.org>
Cc: Kukjin Kim <kgene.kim(a)samsung.com>
Cc: Tomasz Figa <tomasz.figa(a)gmail.com>
Cc: Sylwester Nawrocki <s.nawrocki(a)samsung.com>
Cc: Heiko Stuebner <heiko(a)sntech.de>
Cc: Russell King <linux(a)arm.linux.org.uk>
Cc: Linus Walleij <linus.walleij(a)linaro.org>
Cc: linux-arm-kernel(a)lists.infradead.org
Cc: linux-samsung-soc(a)vger.kernel.org
Cc: linux-kernel(a)vger.kernel.org
---
arch/arm/Kconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 8986335..ec1faea 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -778,7 +778,9 @@ config ARCH_S5P64X0
config ARCH_S5PC100
bool "Samsung S5PC100"
+ select ARM_PATCH_PHYS_VIRT
select ARCH_REQUIRE_GPIOLIB
+ select AUTO_ZRELADDR
select CLKDEV_LOOKUP
select CLKSRC_SAMSUNG_PWM
select CPU_V7
--
1.7.10.4
ARM_PATCH_PHYS_VIRT and AUTO_ZRELADDR have been enabled as default configs
to S5P64X0 platforms.
Introduction of PHYS_VIRT config as default would enable phy-to-virt and
virt-to-phy translation function at boot and module loading time
and enforce dynamic reallocation of memory. AUTO_ZRELADDR config would
enable calculation of kernel load address at run time.
PHYS_VIRT config is mutually exclusive to XIP_KERNEL, XIP_KERNEL is used in
systems with NOR flash devices, and ZRELADDR config is mutually exclusive
to ZBOOT_ROM.
CFT::Call For Testing
Requesting maintainers of S5P64X0 platforms to evaluate the changes on the
board and comment, as I dont have the board for testing and also requesting
an ACK
Signed-off-by: panchaxari <panchaxari.prasannamurthy(a)linaro.org>
Cc: Kukjin Kim <kgene.kim(a)samsung.com>
Cc: Tomasz Figa <tomasz.figa(a)gmail.com>
Cc: Sylwester Nawrocki <s.nawrocki(a)samsung.com>
Cc: Heiko Stuebner <heiko(a)sntech.de>
Cc: Russell King <linux(a)arm.linux.org.uk>
Cc: Linus Walleij <linus.walleij(a)linaro.org>
Cc: linux-arm-kernel(a)lists.infradead.org
Cc: linux-samsung-soc(a)vger.kernel.org
Cc: linux-kernel(a)vger.kernel.org
---
The samsung S5P64X0 vega has an average performing CPU with max speed 667 Mhz.
This SOC has two variants S5P6440 and S5P6450. It has one core based on
ARM1176JZF-S instruction set, and has 16KB data and instruction cache each.
SOC has a memory subsystem with support to NAND Flash interface with x8 data
bus, with 1/4/8/12/16 bit hardware ECC circuit and 4KB Page mode. It has
Mobile DDR interface with x16 or x32 data bus, and DDR2 interface with x16 or
x32 data bus it also supports eMMC4.4.
Below lkml link is a quoting by Russell which clears the concept of PHYS_VIRT
and ZRELADDR
-------------------------------------------------
https://lkml.org/lkml/2011/10/14/434
-------------------------------------------------
---
arch/arm/Kconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 934e26c..8986335 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -759,6 +759,8 @@ config ARCH_S3C64XX
config ARCH_S5P64X0
bool "Samsung S5P6440 S5P6450"
+ select ARM_PATCH_PHYS_VIRT
+ select AUTO_ZRELADDR
select CLKDEV_LOOKUP
select CLKSRC_SAMSUNG_PWM
select CPU_V6
--
1.7.10.4
From: Al Stone <al.stone(a)linaro.org>
This series of patches starts with Hanjun's patch to create a kernel
config item for CONFIG_ACPI_REDUCED_HARDWARE [0]. Building on that, I
then reviewed all of the code that touched any of several fields in the
FADT that the OSPM is supposed to ignore when ACPI is in Hardware Reduced
mode [1]. Any time there was a use of one of the fields to be ignored,
I evaluated whether or not the code was implementing Hardware Reduced
mode correctly. Similarly, for each the flags in the FADT flags field
that are to be ignored in Hardware Reduced mode, the kernel code was again
scanned for proper usage. The remainder of the patches are to fix all of
the situations I could find where the kernel would not behave correctly
in this ACPI mode.
These seem to work just fine on the RTSM model for ARMv7, both with and
without ACPI enabled, and with and without ACPI_REDUCED_HARDWARE enabled;
similarly for the FVP model for ARMv8. The patches for ACPI on ARM
hardware have been submitted elsewhere but they presume that reduced HW
mode is functioning correctly. In the meantime, there's no way I can think
of to test all possible scenarios so feedback would be greatly appreciated.
[0] List at https://wiki.linaro.org/LEG/Engineering/Kernel/ACPI/AcpiReducedHw#Section_5…
[1] Please see the ACPI Specification v5.0 for details on Hardware Reduced
mode (sections 3.11.1, 4.1, 5.2.9, at a minimum).
Changes for v3:
-- Modified enabling ACPI_REDUCED_HARDWARE in ACPICA when using
kernel config item CONFIG_ACPI_REDUCED_HARDWARE; now consistent
with ACPICA code base where needed
-- Enable X86 for CONFIG_ACPI_REDUCED_HARDWARE
-- Minimize bus master reload patching
-- Remove unneeded patch for dmi_check_system() (was 4/6)
-- Correct the patch for removing unneeded map/unmap of FADT fields
Changes for v2:
-- Remove patch that was outside of reduced HW mode changes
-- Simplify CONFIG_ACPI_REDUCED_HARDWARE in Kconfig
-- Simplify use of CONFIG_ACPI_REDUCED_HARDWARE in #ifdefs
-- Ensure changelogs are present
-- Combine and simplify previous patches 8 & 10
Al Stone (5):
ACPI: introduce CONFIG_ACPI_REDUCED_HARDWARE to enable this ACPI mode
ACPI: bus master reload not supported in reduced HW mode
ACPI: HW reduced mode does not allow use of the FADT sci_interrupt
field
ACPI: in HW reduced mode, using FADT PM information is not allowed.
ACPI: do not map/unmap memory regions for FADT entries in reduced HW
mode
drivers/acpi/Kconfig | 8 ++++++++
drivers/acpi/bus.c | 3 ++-
drivers/acpi/osl.c | 36 +++++++++++++++++-------------------
drivers/acpi/pci_link.c | 2 ++
drivers/acpi/processor_idle.c | 15 +++++++++++++--
include/acpi/platform/aclinux.h | 6 ++++++
6 files changed, 48 insertions(+), 22 deletions(-)
--
1.8.3.1
From: Mark Brown <broonie(a)linaro.org>
Add basic CPU topology support to arm64, based on the existing pre-v8
code and some work done by Mark Hambleton. This patch does not
implement any topology discovery support since that should be based on
information from firmware, it merely implements the scaffolding for
integration of topology support in the architecture.
The goal is to separate the architecture hookup for providing topology
information from the DT parsing in order to ease review and avoid
blocking the architecture code (which will be built on by other work)
with the DT code review by providing something something simple
and basic.
A following patch will implement support for parsing the DT topology
bindings for ARM, similar patches will be needed for ACPI.
Signed-off-by: Mark Brown <broonie(a)linaro.org>
---
arch/arm64/Kconfig | 8 +++
arch/arm64/include/asm/topology.h | 42 +++++++++++++
arch/arm64/kernel/Makefile | 1 +
arch/arm64/kernel/smp.c | 12 ++++
arch/arm64/kernel/topology.c | 124 ++++++++++++++++++++++++++++++++++++++
5 files changed, 187 insertions(+)
create mode 100644 arch/arm64/include/asm/topology.h
create mode 100644 arch/arm64/kernel/topology.c
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 6d4dd22ee4b7..c0975fea9bfe 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -154,6 +154,14 @@ config SMP
If you don't know what to do here, say N.
+config ARM_CPU_TOPOLOGY
+ bool "Support CPU topology definition"
+ depends on SMP
+ default y
+ help
+ Support CPU topology definition, based on configuration
+ provided by the firmware.
+
config NR_CPUS
int "Maximum number of CPUs (2-32)"
range 2 32
diff --git a/arch/arm64/include/asm/topology.h b/arch/arm64/include/asm/topology.h
new file mode 100644
index 000000000000..611edefaeaf1
--- /dev/null
+++ b/arch/arm64/include/asm/topology.h
@@ -0,0 +1,42 @@
+#ifndef _ASM_ARM_TOPOLOGY_H
+#define _ASM_ARM_TOPOLOGY_H
+
+#ifdef CONFIG_ARM_CPU_TOPOLOGY
+
+#include <linux/cpumask.h>
+
+struct cputopo_arm {
+ int thread_id;
+ int core_id;
+ int socket_id;
+ cpumask_t thread_sibling;
+ cpumask_t core_sibling;
+};
+
+extern struct cputopo_arm cpu_topology[NR_CPUS];
+
+#define topology_physical_package_id(cpu) (cpu_topology[cpu].socket_id)
+#define topology_core_id(cpu) (cpu_topology[cpu].core_id)
+#define topology_core_cpumask(cpu) (&cpu_topology[cpu].core_sibling)
+#define topology_thread_cpumask(cpu) (&cpu_topology[cpu].thread_sibling)
+
+#define mc_capable() (cpu_topology[0].socket_id != -1)
+#define smt_capable() (cpu_topology[0].thread_id != -1)
+
+void init_cpu_topology(void);
+void store_cpu_topology(unsigned int cpuid);
+const struct cpumask *cpu_coregroup_mask(int cpu);
+int cluster_to_logical_mask(unsigned int socket_id, cpumask_t *cluster_mask);
+
+#else
+
+static inline void init_cpu_topology(void) { }
+static inline void store_cpu_topology(unsigned int cpuid) { }
+static inline int cluster_to_logical_mask(unsigned int socket_id,
+ cpumask_t *cluster_mask) { return -EINVAL; }
+
+#endif
+
+#include <asm-generic/topology.h>
+
+#endif /* _ASM_ARM_TOPOLOGY_H */
diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile
index 5ba2fd43a75b..2d145e38ad49 100644
--- a/arch/arm64/kernel/Makefile
+++ b/arch/arm64/kernel/Makefile
@@ -18,6 +18,7 @@ arm64-obj-$(CONFIG_SMP) += smp.o smp_spin_table.o
arm64-obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o
arm64-obj-$(CONFIG_HAVE_HW_BREAKPOINT)+= hw_breakpoint.o
arm64-obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
+arm64-obj-$(CONFIG_ARM_CPU_TOPOLOGY) += topology.o
obj-y += $(arm64-obj-y) vdso/
obj-m += $(arm64-obj-m)
diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c
index a0c2ca602cf8..0271fbde5363 100644
--- a/arch/arm64/kernel/smp.c
+++ b/arch/arm64/kernel/smp.c
@@ -113,6 +113,11 @@ int __cpu_up(unsigned int cpu, struct task_struct *idle)
return ret;
}
+static void __cpuinit smp_store_cpu_info(unsigned int cpuid)
+{
+ store_cpu_topology(cpuid);
+}
+
/*
* This is the secondary CPU boot entry. We're using this CPUs
* idle thread stack, but a set of temporary page tables.
@@ -150,6 +155,8 @@ asmlinkage void secondary_start_kernel(void)
*/
notify_cpu_starting(cpu);
+ smp_store_cpu_info(cpu);
+
/*
* OK, now it's safe to let the boot CPU continue. Wait for
* the CPU migration code to notice that the CPU is online
@@ -388,6 +395,11 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
int err;
unsigned int cpu, ncores = num_possible_cpus();
+ init_cpu_topology();
+
+ smp_store_cpu_info(smp_processor_id());
+
+
/*
* are we trying to boot more cores than exist?
*/
diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c
new file mode 100644
index 000000000000..aae9d4d72328
--- /dev/null
+++ b/arch/arm64/kernel/topology.c
@@ -0,0 +1,124 @@
+/*
+ * arch/arm64/kernel/topology.c
+ *
+ * Copyright (C) 2011,2013 Linaro Limited.
+ * Written by: Vincent Guittot
+ *
+ * based on arch/sh/kernel/topology.c
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/cpu.h>
+#include <linux/cpumask.h>
+#include <linux/export.h>
+#include <linux/init.h>
+#include <linux/percpu.h>
+#include <linux/node.h>
+#include <linux/nodemask.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+
+#include <asm/cputype.h>
+#include <asm/smp_plat.h>
+#include <asm/topology.h>
+
+/*
+ * cpu topology table
+ */
+struct cputopo_arm cpu_topology[NR_CPUS];
+EXPORT_SYMBOL_GPL(cpu_topology);
+
+const struct cpumask *cpu_coregroup_mask(int cpu)
+{
+ return &cpu_topology[cpu].core_sibling;
+}
+
+static void update_siblings_masks(unsigned int cpuid)
+{
+ struct cputopo_arm *cpu_topo, *cpuid_topo = &cpu_topology[cpuid];
+ int cpu;
+
+ /* update core and thread sibling masks */
+ for_each_possible_cpu(cpu) {
+ cpu_topo = &cpu_topology[cpu];
+
+ if (cpuid_topo->socket_id != cpu_topo->socket_id)
+ continue;
+
+ cpumask_set_cpu(cpuid, &cpu_topo->core_sibling);
+ if (cpu != cpuid)
+ cpumask_set_cpu(cpu, &cpuid_topo->core_sibling);
+
+ if (cpuid_topo->core_id != cpu_topo->core_id)
+ continue;
+
+ cpumask_set_cpu(cpuid, &cpu_topo->thread_sibling);
+ if (cpu != cpuid)
+ cpumask_set_cpu(cpu, &cpuid_topo->thread_sibling);
+ }
+ smp_wmb();
+}
+
+void store_cpu_topology(unsigned int cpuid)
+{
+ struct cputopo_arm *cpuid_topo = &cpu_topology[cpuid];
+
+ /* DT should have been parsed by the time we get here */
+ if (cpuid_topo->core_id == -1)
+ pr_info("CPU%u: No topology information configured\n", cpuid);
+ else
+ update_siblings_masks(cpuid);
+}
+
+
+/*
+ * cluster_to_logical_mask - return cpu logical mask of CPUs in a cluster
+ * @socket_id: cluster HW identifier
+ * @cluster_mask: the cpumask location to be initialized, modified by the
+ * function only if return value == 0
+ *
+ * Return:
+ *
+ * 0 on success
+ * -EINVAL if cluster_mask is NULL or there is no record matching socket_id
+ */
+int cluster_to_logical_mask(unsigned int socket_id, cpumask_t *cluster_mask)
+{
+ int cpu;
+
+ if (!cluster_mask)
+ return -EINVAL;
+
+ for_each_online_cpu(cpu) {
+ if (socket_id == topology_physical_package_id(cpu)) {
+ cpumask_copy(cluster_mask, topology_core_cpumask(cpu));
+ return 0;
+ }
+ }
+
+ return -EINVAL;
+}
+
+/*
+ * init_cpu_topology is called at boot when only one cpu is running
+ * which prevent simultaneous write access to cpu_topology array
+ */
+void __init init_cpu_topology(void)
+{
+ unsigned int cpu;
+
+ /* init core mask and power*/
+ for_each_possible_cpu(cpu) {
+ struct cputopo_arm *cpu_topo = &(cpu_topology[cpu]);
+
+ cpu_topo->thread_id = -1;
+ cpu_topo->core_id = -1;
+ cpu_topo->socket_id = -1;
+ cpumask_clear(&cpu_topo->core_sibling);
+ cpumask_clear(&cpu_topo->thread_sibling);
+ }
+ smp_wmb();
+}
--
1.8.5.1
From: Mark Brown <broonie(a)linaro.org>
It is possible that we may fail to set the clock rate, if we do so then
log the failure and don't bother reprogramming the IP.
Signed-off-by: Mark Brown <broonie(a)linaro.org>
Acked-by: Jaehoon Chung <jh80.chung(a)samsung.com>
---
drivers/mmc/host/sdhci-s3c.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
index 6debda952155..5c20f827d828 100644
--- a/drivers/mmc/host/sdhci-s3c.c
+++ b/drivers/mmc/host/sdhci-s3c.c
@@ -295,6 +295,7 @@ static void sdhci_cmu_set_clock(struct sdhci_host *host, unsigned int clock)
struct device *dev = &ourhost->pdev->dev;
unsigned long timeout;
u16 clk = 0;
+ int ret;
/* If the clock is going off, set to 0 at clock control register */
if (clock == 0) {
@@ -305,7 +306,12 @@ static void sdhci_cmu_set_clock(struct sdhci_host *host, unsigned int clock)
sdhci_s3c_set_clock(host, clock);
- clk_set_rate(ourhost->clk_bus[ourhost->cur_clk], clock);
+ ret = clk_set_rate(ourhost->clk_bus[ourhost->cur_clk], clock);
+ if (ret != 0) {
+ dev_err(dev, "%s: failed to set clock rate %uHz\n",
+ mmc_hostname(host->mmc), clock);
+ return;
+ }
host->clock = clock;
--
1.8.5.1
This patch adds cpufreq callbacks to dpm_{suspend|resume}_noirq() for handling
suspend/resume of cpufreq governors.
There are multiple problems that are fixed by this patch:
- Nishanth Menon (TI) found an interesting problem on his platform, OMAP. His board
wasn't working well with suspend/resume as calls for removing non-boot CPUs
was turning out into a call to drivers ->target() which then tries to play
with regulators. But regulators and their I2C bus were already suspended and
this resulted in a failure. Many platforms have such problems, samsung, tegra,
etc.. They solved it with driver specific PM notifiers where they used to
disable their driver's ->target() routine.
- Lan Tianyu (Intel) & Jinhyuk Choi (Broadcom) found another issue where
tunables configuration for clusters/sockets with non-boot CPUs was getting
lost after suspend/resume, as we were notifying governors with
CPUFREQ_GOV_POLICY_EXIT on removal of the last cpu for that policy and so
deallocating memory for tunables. This is also fixed with this patch as we
don't allow any operation on Governors during suspend/resume now.
Reported-and-tested-by: Lan Tianyu <tianyu.lan(a)intel.com>
Reported-and-tested-by: Nishanth Menon <nm(a)ti.com>
Reported-by: Jinhyuk Choi <jinchoi(a)broadcom.com>
Signed-off-by: Viresh Kumar <viresh.kumar(a)linaro.org>
---
This is almost same as 1/6 of V3 version of this patchset:
https://lkml.org/lkml/2013/11/25/838
This is done to get some initial fixes for 3.13. These are already tested by
both the reporters of initial problems. Tegra/exynos/s5p will keep running their
PM notifiers until v3.14, as they are currently able to work with them..
drivers/base/power/main.c | 3 +++
drivers/cpufreq/cpufreq.c | 50 +++++++++++++++++++++++++++++++++++++++++++++++
include/linux/cpufreq.h | 8 ++++++++
3 files changed, 61 insertions(+)
diff --git a/drivers/base/power/main.c b/drivers/base/power/main.c
index 1b41fca..e3219df 100644
--- a/drivers/base/power/main.c
+++ b/drivers/base/power/main.c
@@ -29,6 +29,7 @@
#include <linux/async.h>
#include <linux/suspend.h>
#include <trace/events/power.h>
+#include <linux/cpufreq.h>
#include <linux/cpuidle.h>
#include <linux/timer.h>
@@ -540,6 +541,7 @@ static void dpm_resume_noirq(pm_message_t state)
dpm_show_time(starttime, state, "noirq");
resume_device_irqs();
cpuidle_resume();
+ cpufreq_resume();
}
/**
@@ -955,6 +957,7 @@ static int dpm_suspend_noirq(pm_message_t state)
ktime_t starttime = ktime_get();
int error = 0;
+ cpufreq_suspend();
cpuidle_pause();
suspend_device_irqs();
mutex_lock(&dpm_list_mtx);
diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c
index 02d534d..b6c7821 100644
--- a/drivers/cpufreq/cpufreq.c
+++ b/drivers/cpufreq/cpufreq.c
@@ -26,6 +26,7 @@
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/slab.h>
+#include <linux/suspend.h>
#include <linux/syscore_ops.h>
#include <linux/tick.h>
#include <trace/events/power.h>
@@ -47,6 +48,9 @@ static LIST_HEAD(cpufreq_policy_list);
static DEFINE_PER_CPU(char[CPUFREQ_NAME_LEN], cpufreq_cpu_governor);
#endif
+/* Flag to suspend/resume CPUFreq governors */
+static bool cpufreq_suspended;
+
static inline bool has_target(void)
{
return cpufreq_driver->target_index || cpufreq_driver->target;
@@ -1462,6 +1466,48 @@ static struct subsys_interface cpufreq_interface = {
.remove_dev = cpufreq_remove_dev,
};
+/*
+ * Callbacks for suspending/resuming governors as some platforms can't change
+ * frequency after this point in suspend cycle. Because some of the devices
+ * (like: i2c, regulators, etc) they use for changing frequency are suspended
+ * quickly after this point.
+ */
+void cpufreq_suspend(void)
+{
+ struct cpufreq_policy *policy;
+
+ if (!has_target())
+ return;
+
+ pr_debug("%s: Suspending Governors\n", __func__);
+
+ list_for_each_entry(policy, &cpufreq_policy_list, policy_list)
+ if (__cpufreq_governor(policy, CPUFREQ_GOV_STOP))
+ pr_err("%s: Failed to stop governor for policy: %p\n",
+ __func__, policy);
+
+ cpufreq_suspended = true;
+}
+
+void cpufreq_resume(void)
+{
+ struct cpufreq_policy *policy;
+
+ if (!has_target())
+ return;
+
+ pr_debug("%s: Resuming Governors\n", __func__);
+
+ cpufreq_suspended = false;
+
+ list_for_each_entry(policy, &cpufreq_policy_list, policy_list)
+ if (__cpufreq_governor(policy, CPUFREQ_GOV_START) ||
+ __cpufreq_governor(policy,
+ CPUFREQ_GOV_LIMITS))
+ pr_err("%s: Failed to start governor for policy: %p\n",
+ __func__, policy);
+}
+
/**
* cpufreq_bp_suspend - Prepare the boot CPU for system suspend.
*
@@ -1764,6 +1810,10 @@ static int __cpufreq_governor(struct cpufreq_policy *policy,
struct cpufreq_governor *gov = NULL;
#endif
+ /* Don't start any governor operations if we are entering suspend */
+ if (cpufreq_suspended)
+ return 0;
+
if (policy->governor->max_transition_latency &&
policy->cpuinfo.transition_latency >
policy->governor->max_transition_latency) {
diff --git a/include/linux/cpufreq.h b/include/linux/cpufreq.h
index dc196bb..ee5fe9d 100644
--- a/include/linux/cpufreq.h
+++ b/include/linux/cpufreq.h
@@ -280,6 +280,14 @@ cpufreq_verify_within_cpu_limits(struct cpufreq_policy *policy)
policy->cpuinfo.max_freq);
}
+#ifdef CONFIG_CPU_FREQ
+void cpufreq_suspend(void);
+void cpufreq_resume(void);
+#else
+static inline void cpufreq_suspend(void) {}
+static inline void cpufreq_resume(void) {}
+#endif
+
/*********************************************************************
* CPUFREQ NOTIFIER INTERFACE *
*********************************************************************/
--
1.7.12.rc2.18.g61b472e
Hi Frederic,
Sorry for idiot of nohz_full. When we using this feature on my mobile
devices, we found this feature keep cpu0 in periodic tick mode. then the
timer interrupt on cpu0 is very higher than normal nohz mode.
that cause high power consuming cost.
I found you have mention this on commit: a382bf934449
nohz: Assign timekeeping duty to a CPU outside the full dynticks range
In fact, if all full dynticks cpu are in idle, cpu0 should be safe to
get into idle too. Do you have some plan or idea to implement this?
otherwise, power cost is too high to enable nohz_full in mobile platform.
--
Thanks
Alex
This reverts commit 4725d41daea7e0cc79b3fb92af012b8cb18fccff.
This patch was dropped when the big.LITTLE switcher was submitted to the
mainline kernel because it wasn't then being used and contained a
logical flaw which meant it wouldn't have achieved what it was
attempting to do anyway. It can also produce compilation warnings in
certain configurations.
---
arch/arm/common/bL_switcher.c | 32 --------------------------------
arch/arm/include/asm/bL_switcher.h | 6 ------
2 files changed, 38 deletions(-)
diff --git a/arch/arm/common/bL_switcher.c b/arch/arm/common/bL_switcher.c
index 1883c5b..2193ae7 100644
--- a/arch/arm/common/bL_switcher.c
+++ b/arch/arm/common/bL_switcher.c
@@ -404,38 +404,6 @@ int bL_switch_request_cb(unsigned int cpu, unsigned int new_cluster_id,
EXPORT_SYMBOL_GPL(bL_switch_request_cb);
/*
- * Detach an outstanding switch request.
- *
- * The switcher will continue with the switch request in the background,
- * but the completer function will not be called.
- *
- * This may be necessary if the completer is in a kernel module which is
- * about to be unloaded.
- */
-void bL_switch_request_detach(unsigned int cpu,
- bL_switch_completion_handler completer)
-{
- struct bL_thread *t;
-
- if (cpu >= ARRAY_SIZE(bL_threads)) {
- pr_err("%s: cpu %d out of bounds\n", __func__, cpu);
- return;
- }
-
- t = &bL_threads[cpu];
-
- if (IS_ERR(t->task) || !t->task)
- return;
-
- spin_lock(&t->lock);
- if (t->completer == completer)
- t->completer = NULL;
- spin_unlock(&t->lock);
-}
-
-EXPORT_SYMBOL_GPL(bL_switch_request_detach);
-
-/*
* Activation and configuration code.
*/
diff --git a/arch/arm/include/asm/bL_switcher.h b/arch/arm/include/asm/bL_switcher.h
index 482383b..87ebcbc 100644
--- a/arch/arm/include/asm/bL_switcher.h
+++ b/arch/arm/include/asm/bL_switcher.h
@@ -40,9 +40,6 @@ static inline int bL_switch_request(unsigned int cpu, unsigned int new_cluster_i
#ifdef CONFIG_BL_SWITCHER
-void bL_switch_request_detach(unsigned int cpu,
- bL_switch_completion_handler completer);
-
int bL_switcher_register_notifier(struct notifier_block *nb);
int bL_switcher_unregister_notifier(struct notifier_block *nb);
@@ -61,9 +58,6 @@ int bL_switcher_trace_trigger(void);
int bL_switcher_get_logical_index(u32 mpidr);
#else
-static void bL_switch_request_detach(unsigned int cpu,
- bL_switch_completion_handler completer) { }
-
static inline int bL_switcher_register_notifier(struct notifier_block *nb)
{
return 0;
--
1.7.10.4
From: Arnaldo Carvalho de Melo <acme(a)ghostprotocols.net>
Hi Ingo,
The first 20 patches in this series are the same as in the previous
one, so I'm not reposting them now.
This series has the code style/constification changes you suggested in
the symbols code and then a reworked fix to the basename problem plus some
more patches not present in the previous series.
Please let me know if you find any further problems,
Best Regards,
- Arnaldo
The following changes since commit 6d65894bc028d0342829ea1e64c9e9efad571124:
tools lib traceevent: Update kvm plugin with is_writable_pte helper (2013-12-04 15:38:14 -0300)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux tags/perf-core-for-mingo
for you to fetch changes up to 1448fef40af6079de38380c3a81bcf9994a1037d:
perf unwinding: Use the per-feature check flags (2013-12-10 16:51:12 -0300)
----------------------------------------------------------------
perf/core improvements and fixes:
. Add an option in 'perf script' to print the source line number, from Adrian Hunter
. Add --header/--header-only options to 'script' and 'report', the default is not
tho show the header info, but as this has been the default for some time,
leave a single line explaining how to obtain that information, from Jiri Olsa.
. Fix symoff printing in callchains in 'perf script', from Adrian Hunter.
. Assorted mmap_pages handling fixes, from Adrian Hunter.
. Fix summary percentage when processing files in 'perf trace', fom David Ahern.
. Handle old kernels where the "raw_syscalls" tracepoints were called plan "syscalls",
in 'perf trace', from David Ahern.
. Several man pages typo fixes from Dongsheng Yang.
. Add '-v' option to 'perf kvm', from Dongsheng Yang.
. Make perf kvm diff support --guestmount, from Dongsheng Yang.
. Get rid of several die() calls in libtraceevent, from Namhyung Kim.
. Use basename() in a more robust way, to avoid problems related to different
system library implementations for that function, from Stephane Eranian.
. Remove open coded management of short_name_allocated member, from Adrian Hunter
. Several cleanups in the "dso" methods, constifying some parameters and
renaming some fields to clarify its purpose.
. Add per-feature check flags, fixing libunwind related build problems on some
architectures, from Jean Pihet.
Signed-off-by: Arnaldo Carvalho de Melo <acme(a)redhat.com>
----------------------------------------------------------------
Adrian Hunter (7):
perf script: Fix symoff printing in callchains
perf script: Add an option to print the source line number
perf record: Fix display of incorrect mmap pages
perf evlist: Remove unnecessary parentheses
perf evlist: Fix max mmap_pages
perf evlist: Fix mmap pages rounding to power of 2
perf symbols: Remove open coded management of short_name_allocated member
Arnaldo Carvalho de Melo (8):
perf symbols: Rename [sl]name_alloc to match the members they refer to
perf machine: Don't open code assign dso->short_name
perf symbols: Set alloc flag close to setting the long_name
perf symbols: Remove open coded management of long_name_allocated member
perf symbols: Constify dso->long_name
perf symbols: Set freed members to NULL in dso destructor
perf symbols: Constify some DSO methods parameters
perf symbols: Rename filename argument
David Ahern (2):
perf trace: Add support for syscalls vs raw_syscalls
perf trace: Fix summary percentage when processing files
Dongsheng Yang (6):
perf kvm: Introduce option -v for perf kvm command.
perf kvm: Fix bug in 'stat report'
perf archive: Remove duplicated 'runs' in man page
perf annotate: Fix typo
perf kvm: Move code to generate filename for perf-kvm to function.
perf kvm: Make perf kvm diff support --guestmount.
Jean Pihet (2):
perf tools: Add per-feature check flags
perf unwinding: Use the per-feature check flags
Jiri Olsa (2):
perf report: Add --header/--header-only options
perf script: Add --header/--header-only options
Namhyung Kim (5):
tools lib traceevent: Get rid of malloc_or_die() in pevent_filter_alloc()
tools lib traceevent: Get rid of malloc_or_die() in add_event()
tools lib traceevent: Get rid of die() in create_arg_item()
tools lib traceevent: Get rid of malloc_or_die() in pevent_filter_add_filter_str()
tools lib traceevent: Get rid of die() in pevent_filter_clear_trivial()
Stephane Eranian (1):
perf symbols: Fix bug in usage of the basename() function
Steven Rostedt (1):
tools lib traceevent: Report better error message on bad function args
tools/lib/traceevent/event-parse.c | 28 +++++---
tools/lib/traceevent/event-parse.h | 2 +-
tools/lib/traceevent/parse-filter.c | 57 +++++++++++----
tools/perf/Documentation/perf-archive.txt | 6 +-
tools/perf/Documentation/perf-kvm.txt | 7 +-
tools/perf/Documentation/perf-report.txt | 9 +++
tools/perf/Documentation/perf-script.txt | 8 ++-
tools/perf/builtin-annotate.c | 2 +-
tools/perf/builtin-diff.c | 3 +-
tools/perf/builtin-kvm.c | 11 ++-
tools/perf/builtin-record.c | 2 +-
tools/perf/builtin-report.c | 22 +++++-
tools/perf/builtin-script.c | 23 +++++-
tools/perf/builtin-trace.c | 32 ++++++++-
tools/perf/config/Makefile | 52 ++++++++------
tools/perf/config/feature-checks/Makefile | 8 +--
tools/perf/util/annotate.c | 2 +-
tools/perf/util/build-id.c | 2 +-
tools/perf/util/build-id.h | 2 +-
tools/perf/util/dso.c | 112 ++++++++++++++++++++----------
tools/perf/util/dso.h | 16 ++---
tools/perf/util/evlist.c | 10 +--
tools/perf/util/header.c | 6 +-
tools/perf/util/machine.c | 6 +-
tools/perf/util/map.c | 17 +++++
tools/perf/util/map.h | 2 +
tools/perf/util/probe-event.c | 2 +-
tools/perf/util/session.c | 15 +++-
tools/perf/util/session.h | 1 +
tools/perf/util/srcline.c | 2 +-
tools/perf/util/symbol.c | 38 ++++------
tools/perf/util/symbol.h | 3 +-
tools/perf/util/util.c | 14 ++++
tools/perf/util/util.h | 14 ++++
tools/perf/util/vdso.c | 2 +-
35 files changed, 375 insertions(+), 163 deletions(-)
From: Radha Mohan Chintakuntla <rchintakuntla(a)cavium.com>
This patch series provides an implementation of supporting 48-bit
Physical Addresses for ARMv8 platforms. It is the maximum width that
any ARMv8 based processor can support.
The implementation extends the existing support of 40-bit PA.The kernel
and user space will now be able to access 128TB each. With 4KB page size
the Linux now will be using 4 levels of page tables by making use of
'pud'. And with 64KB page size the Linux will be using 3 levels of page
tables.
The code has been tested with LTP.
Radha Mohan Chintakuntla (2):
arm64: Add support for 48-bit Physical Addresses
arm64: Add 48-bit PA support for 64KB page size
arch/arm64/include/asm/memory.h | 6 +--
arch/arm64/include/asm/page.h | 4 +-
arch/arm64/include/asm/pgalloc.h | 20 ++++++-
arch/arm64/include/asm/pgtable-3level-hwdef.h | 34 ++++++++++++
arch/arm64/include/asm/pgtable-4level-hwdef.h | 57 ++++++++++++++++++++
arch/arm64/include/asm/pgtable-4level-types.h | 71 +++++++++++++++++++++++++
arch/arm64/include/asm/pgtable-hwdef.h | 9 ++--
arch/arm64/include/asm/pgtable.h | 50 +++++++++++++++---
arch/arm64/include/asm/tlb.h | 2 -
arch/arm64/kernel/head.S | 55 +++++++++++++++++--
arch/arm64/kernel/traps.c | 7 +++
arch/arm64/mm/proc.S | 2 +-
12 files changed, 289 insertions(+), 28 deletions(-)
create mode 100644 arch/arm64/include/asm/pgtable-4level-hwdef.h
create mode 100644 arch/arm64/include/asm/pgtable-4level-types.h
The Power State and Coordination Interface (PSCI) specification defines
SYSTEM_OFF and SYSTEM_RESET functions for system poweroff and reboot.
This patchset adds emulation of PSCI SYSTEM_OFF and SYSTEM_RESET functions
in KVM ARM/ARM64 by forwarding them to user space (QEMU or KVMTOOL) using
KVM_EXIT_SHUTDOWN and KVM_EXIT_RESET exit reasons.
To try this patch from guest kernel, we will need PSCI-based restart and
poweroff support in the guest kenel for both ARM and ARM64.
Rob Herring has already submitted patches for PSCI-based restart and
poweroff in ARM kernel but these are not merged yet due unstable device
tree bindings of kernel PSCI support. We will be having similar patches
for PSCI-based restart and poweroff in ARM64 kernel.
(Refer http://www.spinics.net/lists/arm-kernel/msg262217.html)
(Refer http://www.spinics.net/lists/devicetree/msg05348.html)
Anup Patel (2):
KVM: Add KVM_EXIT_RESET to user space API header
ARM/ARM64: KVM: Forward PSCI SYSTEM_OFF and SYSTEM_RESET to user
space
arch/arm/include/asm/kvm_psci.h | 2 +-
arch/arm/include/uapi/asm/kvm.h | 2 ++
arch/arm/kvm/handle_exit.c | 7 ++++++-
arch/arm/kvm/psci.c | 38 +++++++++++++++++++++++++++++--------
arch/arm64/include/asm/kvm_psci.h | 2 +-
arch/arm64/include/uapi/asm/kvm.h | 2 ++
arch/arm64/kvm/handle_exit.c | 10 ++++++----
include/uapi/linux/kvm.h | 1 +
8 files changed, 49 insertions(+), 15 deletions(-)
--
1.7.9.5
Add CFLAGS and LDFLAGS for each feature to be checked during the
build. This allows to pass particular flags and parameters to the
feature checks compilation.
Use the per-feature check flags for the unwinding feature in order
to correctly compile the test-all, libunwind and libunwind-debug-frame
feature checks.
This change set simplifies the flags passing mechanism between the
Makefiles in config/Makefile and config/feature-checks; this
could be farther optimized by moving the compilation flags to the
per-feature check flags for all features to be checked.
Tested on x86_64, ARMv7 and ARMv8 with and without LIBUNWIND_DIR
set in 'make -C tools/perf'
Jean Pihet (2):
perf: add per-feature check flags
perf: unwinding: use the per-feature check flags
tools/perf/config/Makefile | 52 ++++++++++++++++++-------------
tools/perf/config/feature-checks/Makefile | 8 ++---
2 files changed, 34 insertions(+), 26 deletions(-)
--
1.7.11.7
From: Al Stone <al.stone(a)linaro.org>
This series of patches starts with Hanjun's patch to create a kernel
config item for CONFIG_ACPI_REDUCED_HARDWARE [0]. Building on that, I
then reviewed all of the code that touched any of several fields in the
FADT that the OSPM is supposed to ignore when ACPI is in Hardware Reduced
mode [1]. Any time there was a use of one of the fields to be ignored,
I evaluated whether or not the code was implementing Hardware Reduced
mode correctly. Similarly, for each the flags in the FADT flags field
that are to be ignored in Hardware Reduced mode, the kernel code was again
scanned for proper usage. The remainder of the patches are to fix all of
the situations I could find where the kernel would not behave correctly
in this ACPI mode.
These seem to work just fine on the RTSM model for ARMv7, both with and
without ACPI enabled, and with and without ACPI_REDUCED_HARDWARE enabled;
similarly for the FVP model for ARMv8. The patches for ACPI on ARM
hardware will be coming later but they presume that reduced HW mode is
functioning correctly. In the meantime, there's no way I can think of
to test all possible scenarios so feedback would be greatly appreciated.
[0] List at https://wiki.linaro.org/LEG/Engineering/Kernel/ACPI/AcpiReducedHw#Section_5…
[1] Please see the ACPI Specification v5.0 for details on Hardware Reduced
mode.
Changes for v2:
-- Remove patch that was outside of reduced HW mode changes
-- Simplify CONFIG_ACPI_REDUCED_HARDWARE in Kconfig
-- Simplify use of CONFIG_ACPI_REDUCED_HARDWARE in #ifdefs
-- Ensure changelogs are present
-- Combine and simplify previous patches 8 & 10
Al Stone (6):
ACPI: introduce CONFIG_ACPI_REDUCED_HARDWARE to enable this ACPI mode
ACPI: bus master reload not supported in reduced HW mode
ACPI: HW reduced mode does not allow use of the FADT sci_interrupt
field
ACPI: ARM: exclude DMI calls
ACPI: do not reserve memory regions for some FADT entries in HW
reduced mode
ACPI: in HW reduced mode, using FADT PM information is not allowed.
drivers/acpi/Kconfig | 8 ++++++++
drivers/acpi/bus.c | 3 ++-
drivers/acpi/osl.c | 24 ++++++++++++------------
drivers/acpi/pci_link.c | 2 ++
drivers/acpi/processor_idle.c | 16 ++++++++++++++--
include/acpi/platform/aclinux.h | 4 ++++
include/linux/dmi.h | 2 +-
7 files changed, 43 insertions(+), 16 deletions(-)
--
1.8.3.1
Add CFLAGS and LDFLAGS for each feature to be checked during the
build. This allows to pass particular flags and parameters to the
feature checks compilation.
Use the per-feature check flags for the unwinding feature in order
to correctly compile the libunwind and libunwind-debug-frame feature
checks.
This change set simplifies the flags passing mechanism between the
Makefiles in config/Makefile and config/feature-checks; this
could be farther optimized by moving the compilation flags to the
per-feature check flags for all features to be checked.
Tested on x86_64, ARMv7 and ARMv8 with and without LIBUNWIND_DIR
set in 'make -C tools/perf'
Jean Pihet (2):
perf: add per-feature check flags
perf: unwinding: use the per-feature check flags
tools/perf/config/Makefile | 48 +++++++++++++++++--------------
tools/perf/config/feature-checks/Makefile | 8 +++---
2 files changed, 30 insertions(+), 26 deletions(-)
--
1.7.11.7
This patch set is based on part1 "Make ACPI core running on ARM64" patch
set.
After we can get the ACPI tables from UEFI, we can use these tables
to initialise the system now.
GIC (means GIC cpu interface) structure and GIC distributor structure in
MADT table contains the information of GIC cpu interface base address
and GIC distributor base address, which can be used to initialise GIC.
Further more, parked address in GIC structure can be used as cpu release
address for spin table SMP initialisation.
This patch set use these information to init SMP and GIC.
Please refer to chapter 5.2.12.14/15 of ACPI 5.0 spec for GIC and GIC
distributor structure information.
Amit Daniel Kachhap (1):
irqdomain: Add a new API irq_create_acpi_mapping()
Hanjun Guo (8):
ARM64 / ACPI: Implement core functions for parsing MADT table
ARM64 / ACPI: Prefill cpu possible/present maps and map logical cpu
id to APIC id
ARM64 / ACPI: Introduce map_gic_id() to get apic id from MADT or _MAT
method
ARM64 / ACPI: Use Parked Address in GIC structure for spin table SMP
initialisation
ACPI: Define ACPI_IRQ_MODEL_GIC needed for arm
Irqchip / gic: Set as default domain so we can access from ACPI
ACPI / ARM64: Update acpi_register_gsi to register with the core IRQ
subsystem
ACPI / GIC: Initialize GIC using the information in MADT
arch/arm64/include/asm/acpi.h | 16 +-
arch/arm64/kernel/irq.c | 5 +
arch/arm64/kernel/setup.c | 2 +
arch/arm64/kernel/smp.c | 2 +
arch/arm64/kernel/smp_spin_table.c | 16 +-
drivers/acpi/bus.c | 3 +
drivers/acpi/plat/arm-core.c | 397 +++++++++++++++++++++++++++++++++++-
drivers/acpi/processor_core.c | 26 +++
drivers/acpi/tables.c | 21 ++
drivers/irqchip/irq-gic.c | 7 +
include/linux/acpi.h | 9 +
kernel/irq/irqdomain.c | 27 +++
12 files changed, 521 insertions(+), 10 deletions(-)
--
1.7.9.5
From: Mark Brown <broonie(a)linaro.org>
These symbols are only referenced in this source file so can be made
static, and the efficiency table is constant data so can be declared as
such. This avoids polluting the global namespace and fixes warnings
from sparse.
The function arch_scale_freq_power() is still not prototyped or static,
this is a separate issue as this is overriding a weak symbol from the
scheduler which neglects to provide a prototype.
Signed-off-by: Mark Brown <broonie(a)linaro.org>
---
arch/arm/kernel/topology.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/kernel/topology.c b/arch/arm/kernel/topology.c
index 85a87370f144..0bc94b1fd1ae 100644
--- a/arch/arm/kernel/topology.c
+++ b/arch/arm/kernel/topology.c
@@ -68,16 +68,16 @@ struct cpu_efficiency {
* Processors that are not defined in the table,
* use the default SCHED_POWER_SCALE value for cpu_scale.
*/
-struct cpu_efficiency table_efficiency[] = {
+static const struct cpu_efficiency table_efficiency[] = {
{"arm,cortex-a15", 3891},
{"arm,cortex-a7", 2048},
{NULL, },
};
-unsigned long *__cpu_capacity;
+static unsigned long *__cpu_capacity;
#define cpu_capacity(cpu) __cpu_capacity[cpu]
-unsigned long middle_capacity = 1;
+static unsigned long middle_capacity = 1;
/*
* Iterate all CPUs' descriptor in DT and compute the efficiency
@@ -89,7 +89,7 @@ unsigned long middle_capacity = 1;
*/
static void __init parse_dt_topology(void)
{
- struct cpu_efficiency *cpu_eff;
+ const struct cpu_efficiency *cpu_eff;
struct device_node *cn = NULL;
unsigned long min_capacity = (unsigned long)(-1);
unsigned long max_capacity = 0;
@@ -158,7 +158,7 @@ static void __init parse_dt_topology(void)
* boot. The update of all CPUs is in O(n^2) for heteregeneous system but the
* function returns directly for SMP system.
*/
-void update_cpu_power(unsigned int cpu)
+static void update_cpu_power(unsigned int cpu)
{
if (!cpu_capacity(cpu))
return;
@@ -185,7 +185,7 @@ const struct cpumask *cpu_coregroup_mask(int cpu)
return &cpu_topology[cpu].core_sibling;
}
-void update_siblings_masks(unsigned int cpuid)
+static void update_siblings_masks(unsigned int cpuid)
{
struct cputopo_arm *cpu_topo, *cpuid_topo = &cpu_topology[cpuid];
int cpu;
--
1.8.5.1
This is the last part of patch set for core of ARM64 ACPI, and is based
on the patch set part2 "Using ACPI MADT table to initialise SMP and GIC".
ACPI GTDT (Generic Timer Description Table) is used for ARM/ARM64 only,
and contains the information for arch timer initialisation.
This patch trys to convert the arch timer to ACPI using GTDT.
After this patch set was posted, we already finished the SMP, GIC and
arch timer initialisation, which all are essential for ARM64 core system
running, then we will focus on converting the device drivers to ACPI.
Here is the GTDT ASL code I used:
---
platforms/foundation-v8.acpi/gtdt.asl | 35 ++++++++++++++++++++++-----------
1 file changed, 23 insertions(+), 12 deletions(-)
diff --git a/platforms/foundation-v8.acpi/gtdt.asl b/platforms/foundation-v8.acpi/gtdt.asl
index 18c821a..714d61c 100644
--- a/platforms/foundation-v8.acpi/gtdt.asl
+++ b/platforms/foundation-v8.acpi/gtdt.asl
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ * Hanjun Guo <hanjun.guo(a)linaro.org>
*
* [GTDT] Generic Timer Description Table
* Format: [ByteLength] FieldName : HexFieldValue
@@ -21,22 +22,32 @@
[0004] Flags (decoded below) : 00000001
Memory Present : 1
-[0004] Secure PL1 Interrupt : 00000000
-[0004] SPL1 Flags (decoded below) : 00000000
- Trigger Mode : 0
+/* In Foundation model's dts file, the last cell of interrupts
+ * is 0xff01, it means its cpu mask is FF, and trigger type
+ * and flag is 1 = low-to-high edge triggered.
+ *
+ * so in ACPI the Trigger Mode is 1 - Edge triggered, and
+ * Polarity is 0 - Active high as ACPI spec describled.
+ *
+ * using direct mapping for hwirqs, it means that we using
+ * ID [16, 31] for PPI, not [0, 15] used in FDT.
+ */
+[0004] Secure PL1 Interrupt : 0000001d
+[0004] SPL1 Flags (decoded below) : 00000001
+ Trigger Mode : 1
Polarity : 0
-[0004] Non-Secure PL1 Interrupt : 00000000
-[0004] NSPL1 Flags (decoded below) : 00000000
- Trigger Mode : 0
+[0004] Non-Secure PL1 Interrupt : 0000001e
+[0004] NSPL1 Flags (decoded below) : 00000001
+ Trigger Mode : 1
Polarity : 0
-[0004] Virtual Timer Interrupt : 00000000
-[0004] VT Flags (decoded below) : 00000000
- Trigger Mode : 0
+[0004] Virtual Timer Interrupt : 0000001b
+[0004] VT Flags (decoded below) : 00000001
+ Trigger Mode : 1
Polarity : 0
-[0004] Non-Secure PL2 Interrupt : 00000000
-[0004] NSPL2 Flags (decoded below) : 00000000
- Trigger Mode : 0
+[0004] Non-Secure PL2 Interrupt : 0000001a
+[0004] NSPL2 Flags (decoded below) : 00000001
+ Trigger Mode : 1
Polarity : 0
Hanjun Guo (2):
clocksource / arch_timer: Use ACPI GTDT table to initialize arch
timer
ARM64 / clocksource: Use arch_timer_acpi_init()
arch/arm64/kernel/time.c | 4 ++
drivers/clocksource/arm_arch_timer.c | 129 ++++++++++++++++++++++++++++++----
include/clocksource/arm_arch_timer.h | 7 +-
3 files changed, 124 insertions(+), 16 deletions(-)
--
1.7.9.5
ARM_PATCH_PHYS_VIRT and AUTO_ZRELADDR have been enabled as default configs
to MSM platform
Introduction of PHYS_VIRT config as default would enable phy-to-virt and
virt-to-phy translation function at boot and module loading time
and enforce dynamic reallocation of memory. AUTO_ZRELADDR config would
enable calculation of kernel load address at run time.
PHYS_VIRT config is mutually exclusive to XIP_KERNEL, XIP_KERNEL is used in
systems with NOR flash devices, and ZRELADDR config is mutually exclusive
to ZBOOT_ROM.
CFT::Call For Testing
Requesting maintainers of MSM platforms to evaluate the changes on the board
and comment, as I dont have the board for testing and also requesting an ACK
Signed-off-by: panchaxari <panchaxari.prasannamurthy(a)linaro.org>
Cc: David Brown <davidb(a)codeaurora.org>
Cc: Daniel Walker <dwalker(a)fifo99.com>
Cc: Bryan Huntsman <bryanh(a)codeaurora.org>
Cc: Russell King <linux(a)arm.linux.org.uk>
Cc: Linus Walleij <linus.walleij(a)linaro.org>
Cc: linux-arm-msm(a)vger.kernel.org
Cc: linux-arm-kernel(a)lists.infradead.org
Cc: linux-kernel(a)vger.kernel.org
---
ARCH_MSM supports for Qualcomm MSM/QSD based systems. This runs on the apps
processor of the MSM/QSD and depends on a shared memory interface to the modem
processor which runs the baseband stack and controls some vital subsystems
like clock and power control.
Snapdragon is based on ARMv7 instruction set. And supports Random memory devices
like DDR1, LPDDR2 and LPDDR3. And storage memory devices like NAND, eMMC.
Below lkml link is a quoting by Russell which clears the concept of PHYS_VIRT
and ZRELADDR
---------------------------------------------------
https://lkml.org/lkml/2011/10/14/434
-------------------------------------------------
---
arch/arm/Kconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 13621ed..3b77864 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -638,6 +638,8 @@ config ARCH_PXA
config ARCH_MSM
bool "Qualcomm MSM"
select ARCH_REQUIRE_GPIOLIB
+ select ARM_PATCH_PHYS_VIRT
+ select AUTO_ZRELADDR
select CLKSRC_OF if OF
select COMMON_CLK
select GENERIC_CLOCKEVENTS
--
1.7.10.4