Currently, KVM ARM/ARM64 only provides in-kernel emulation of Power State
and Coordination Interface (PSCI) v0.1.
This patchset aims at providing newer PSCI v0.2 for KVM ARM/ARM64 VCPUs
such that it does not break current KVM ARM/ARM64 ABI. Also, the patchset
provides emulation of only few PSCI v0.2 functions such as PSCI_VERSION,
CPU_ON, and CPU_OFF. Emulation of other PSCI v0.2 functions will be added
later.
The user space tools (i.e. QEMU or KVMTOOL) will have to explicitly enable
KVM_ARM_VCPU_PSCI_0_2 feature using KVM_ARM_VCPU_INIT ioctl for providing
PSCI v0.2 to VCPUs.
Anup Patel (3):
KVM: Add capability to advertise PSCI v0.2 support
ARM/ARM64: KVM: Add support for PSCI v0.2 emulation
KVM: Documentation: Add info regarding KVM_ARM_VCPU_PSCI_0_2 feature
Documentation/virtual/kvm/api.txt | 2 +
arch/arm/include/asm/kvm_host.h | 2 +-
arch/arm/include/uapi/asm/kvm.h | 39 ++++++++++++++++--
arch/arm/kvm/arm.c | 6 ++-
arch/arm/kvm/psci.c | 79 ++++++++++++++++++++++++++++++-------
arch/arm64/include/asm/kvm_host.h | 2 +-
arch/arm64/include/uapi/asm/kvm.h | 39 ++++++++++++++++--
include/uapi/linux/kvm.h | 1 +
8 files changed, 146 insertions(+), 24 deletions(-)
--
1.7.9.5
Patchsets related to hibernation resume:
- enhancement to make the use of an existing resume file more general
- enhance name_to_dev_t to ignore trailing newlines coming from userspace.
Both patches are based on the 3.12-rc3 tag. This was tested on a
Pandaboard with partial hibernation support, and compiled for x86.
[PATCH 1/2] init/do_mounts.c: ignore final \n in name_to_dev_t
init/do_mounts.c | 23 ++++++++++++++++++-----
1 file changed, 18 insertions(+), 5 deletions(-)
Changes name_to_dev_t to handle a trailing newline in the
input buffer, which will allow name_to_dev_t to be used
directly with user buffers without requiring a copy.
Also adds a const to the name parameter which reflects
how name_to_dev_t is treating the input buffer currently.
This also allows direct use of user buffers
(from resume_store for example).
[PATCH 2/2] PM / Hibernate: use name_to_dev_t to parse resume
kernel/power/hibernate.c | 15 ++++-----------
1 file changed, 4 insertions(+), 11 deletions(-)
Use name_to_dev_t to parse the /sys/power/resume file making the
syntax more flexible. It supports the previous use syntax
and additionally can support other formats such as
/dev/devicenode and UUID= formats.
By changing /sys/debug/resume to accept the same syntax as
the resume=device parameter, we can parse the resume=device
in the initrd init script and use the resume device directly
from the kernel command line.
Changes in v3:
--------------
* Dropped documentation patch as it went in through trivial
* Added patch for name_to_dev_t to support directly parsing userspace
buffer
Changes in v2:
--------------
* Added check for null return of kstrndup in hibernate.c
Thanks,
Sebastian
From: Mark Brown <broonie(a)linaro.org>
There is currently no facility in ACPI to express the hookup of voltage
regulators, the expectation is that the regulators that exist in the
system will be handled transparently by firmware if they need software
control at all. This means that if for some reason the regulator API is
enabled on such a system it should assume that any supplies that devices
need are provided by the system at all relevant times without any software
intervention.
Tell the regulator core to make this assumption by calling
regulator_has_full_constraints(). Do this as soon as we know we are using
ACPI so that the information is available to the regulator core as early
as possible. This will cause the regulator core to pretend that there is
an always on regulator supplying any supply that is requested but that has
not otherwise been mapped which is the behaviour expected on a system with
ACPI.
Should the ability to specify regulators be added in future revisions of
ACPI then once we have support for ACPI mappings in the kernel the same
assumptions will apply. It is also likely that systems will default to a
mode of operation which does not require any interpretation of these
mappings in order to be compatible with existing operating system releases
so it should remain safe to make these assumptions even if the mappings
exist but are not supported by the kernel.
Signed-off-by: Mark Brown <broonie(a)linaro.org>
---
drivers/acpi/bus.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/acpi/bus.c b/drivers/acpi/bus.c
index 384da5ab5955..fcb59c21c68d 100644
--- a/drivers/acpi/bus.c
+++ b/drivers/acpi/bus.c
@@ -33,6 +33,7 @@
#include <linux/proc_fs.h>
#include <linux/acpi.h>
#include <linux/slab.h>
+#include <linux/regulator/machine.h>
#ifdef CONFIG_X86
#include <asm/mpspec.h>
#endif
@@ -509,6 +510,14 @@ void __init acpi_early_init(void)
goto error0;
}
+ /*
+ * If the system is using ACPI then we can be reasonably
+ * confident that any regulators are managed by the firmware
+ * so tell the regulator core it has everything it needs to
+ * know.
+ */
+ regulator_has_full_constraints();
+
return;
error0:
--
1.8.5.3
On Mon, Jan 27, 2014 at 9:59 AM, Kevin's boot bot <khilman(a)linaro.org> wrote:
> Automated DT boot report for various ARM defconfigs.
>
>
> Tree/Branch: mainline
> Git describe: v3.13-8631-gba635f8
> Failed boot tests (console logs at the end)
> ===========================================
> armada-370-mirabox: FAIL: multi_v7_defconfig
This is a new(ish) boot failure that I finally bisected. Note that it
only fails on multi_v7_defconfig, and not mvebu_defconfig.
When it fails, there's no useful console output, but it was bisected down to:
first bad commit: [af8d1c63afcbf36eea06789c92e22d4af118d2fb] ARM:
mvebu: Add support to get the ID and the revision of a SoC.
Based on an idea from Jason, I added CONFIG_PCI=y and
CONFIG_MVEBU_PCI=y to multi_v7_defconfig and that made it start
booting again, some something is probably hanging when accessing PCI
registers?
Kevin
This patch set trys to make ACPI core running on ARM64.
1. Why ACPI is needed ?
ACPI provides standard interfaces for power managment, themal
control, device enumeration and configuration and etc. So ACPI
can make OS and hardware decoupling and make people upgrade
software or hardware more easily.
ACPI is more than that. It can provide standard error report
interface called ACPI Platform Error Interface (APEI) for
RAS features, and provide standard interface for dynamic
system device reconfigurations such as CPU/memory/computer
node hot-add and hot-remove, this is especially useful
for servers.
2. Does ACPI run propably on ARM64 ?
ACPI spec 5.0 introduces hardware reduced mode, GICC/GICD,
GTDT for arch timer and etc for Socs.
This makes it possible to run ACPI on ARM/ARM64. Some
company already did that (UEFI+ACPI) on ARM platforms.
ACPI spec for ARM/ARM64 is still need to be improved and
people are working on that, but for now, we can run ACPI
propably except for some new features such as PSCI and
GICv3.
3. What we did in this patch set
patch 1-8(Hanjun Guo) will make ACPI core running on ARM64 and
make the compilation is ok on ARM64.
patch 9-12 will enumeration cpus presented by MADT table.
since PSCI is not available for ACPI 5.0, we use spin-table
method for SMP initialization.
patch 13-16 will initialize GIC in the system. ACPI only
support one GIC and only report information about GICC and
GICD, so there will some limitations for GICv3 and GICH
for GICv2 for virtualization.
patch 17-19 and patch from Amit will finish the arch timer
initialization. We get informatiom from GTDT
(Generic Timer Description Table) to initialize arch timer
and introduce a macro CLOCKSOURCE_ACPI_DECLARE to do the
same job as CLOCKSOURCE_OF_DECLARE to make it scalable for
other timers.
All the ACPI tables are available with BSD license at:
git://git.linaro.org/arm/acpi/acpi-asl.git
Changs since last RFC version:
1) Introduce some PCI functions when PCI is enabled
2) Select ACPI_REDUCED_HARDWARE_ONLY if ACPI is enabled
3) Remove ACPI based CPU hotplug code
4) Use spin-table method for SMP initialization
5) Add macro CLOCKSOURCE_ACPI_DECLARE for ACPI timer init
6) Address lots of comments and suggestions in last RFC version
7) Remove RFC tag and make all the patches seperated as two
parts, one is "ACPI: Some patches to prepare for running ACPI
on !x86 and !ia64", and another is this one.
8) Rebased on 3.13-rc8.
Amit Daniel Kachhap (1):
clocksource / acpi: Add macro CLOCKSOURCE_ACPI_DECLARE
Hanjun Guo (19):
ARM64 / ACPI: Make PCI optional for ACPI on ARM64
ARM64 : Add dummy asm/cpu.h
ARM64 / ACPI: Introduce the skeleton of _PDC related for ARM64
ARM64 / ACPI: Introduce arm_core.c and its related head file
ARM64 / ACPI: Introduce lowlevel suspend function
ARM64 / ACPI: Introduce some PCI functions when PCI is enabled
ARM64 / ACPI: Enable ARM64 in Kconfig
ARM64 / ACPI: Select ACPI_REDUCED_HARDWARE_ONLY if ACPI is enabled on
ARM64
ARM64 / ACPI: Implement core functions for parsing MADT table
ARM64 / ACPI: Enumerate possible/present CPU set and map logical cpu
id to APIC id
ARM64 / ACPI: Get the enable method for SMP initialization
ARM64 / ACPI: Use Parked Address in GIC structure for spin table SMP
initialisation
ARM64 / ACPI: Define ACPI_IRQ_MODEL_GIC needed for arm
Irqchip / gic: Set as default domain so we can access from ACPI
ACPI / ARM64: Update acpi_register_gsi to register with the core IRQ
subsystem
ACPI / GIC: Initialize GIC using the information in MADT
clocksource / arch_timer: Use ACPI GTDT table to initialize arch
timer
clocksource / ACPI: Introduce clocksource_acpi_init() using
CLOCKSOURCE_ACPI_DECLARE
ARM64 / clocksource: Use clocksource_acpi_init()
arch/arm64/Kconfig | 3 +
arch/arm64/Makefile | 1 +
arch/arm64/include/asm/acpi.h | 112 +++++++
arch/arm64/include/asm/cpu.h | 25 ++
arch/arm64/include/asm/cpu_ops.h | 1 +
arch/arm64/include/asm/pci.h | 20 ++
arch/arm64/include/asm/processor.h | 2 +
arch/arm64/include/asm/smp.h | 2 +-
arch/arm64/kernel/cpu_ops.c | 2 +-
arch/arm64/kernel/irq.c | 6 +
arch/arm64/kernel/process.c | 3 +
arch/arm64/kernel/setup.c | 6 +
arch/arm64/kernel/smp.c | 42 ++-
arch/arm64/kernel/smp_spin_table.c | 12 +-
arch/arm64/kernel/time.c | 6 +
arch/arm64/pci/Makefile | 1 +
arch/arm64/pci/pci.c | 33 ++
drivers/acpi/Kconfig | 11 +-
drivers/acpi/Makefile | 4 +-
drivers/acpi/bus.c | 3 +
drivers/acpi/internal.h | 7 +
drivers/acpi/osl.c | 3 +-
drivers/acpi/plat/Makefile | 1 +
drivers/acpi/plat/arm-core.c | 599 ++++++++++++++++++++++++++++++++++
drivers/acpi/tables.c | 21 ++
drivers/clocksource/Makefile | 1 +
drivers/clocksource/arm_arch_timer.c | 101 +++++-
drivers/clocksource/clksrc-acpi.c | 36 ++
drivers/irqchip/irq-gic.c | 7 +
include/asm-generic/vmlinux.lds.h | 10 +
include/linux/acpi.h | 7 +
include/linux/clocksource.h | 15 +
include/linux/pci.h | 33 +-
33 files changed, 1099 insertions(+), 37 deletions(-)
create mode 100644 arch/arm64/include/asm/acpi.h
create mode 100644 arch/arm64/include/asm/cpu.h
create mode 100644 arch/arm64/include/asm/pci.h
create mode 100644 arch/arm64/pci/Makefile
create mode 100644 arch/arm64/pci/pci.c
create mode 100644 drivers/acpi/plat/Makefile
create mode 100644 drivers/acpi/plat/arm-core.c
create mode 100644 drivers/clocksource/clksrc-acpi.c
--
1.7.9.5
From: Mark Brown <broonie(a)linaro.org>
This will help support future enhancements in the way we negotiate
parameters in the core.
Signed-off-by: Mark Brown <broonie(a)linaro.org>
---
sound/soc/codecs/pcm1681.c | 15 ++++++++++-----
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/sound/soc/codecs/pcm1681.c b/sound/soc/codecs/pcm1681.c
index 73f9c3630e2c..e427544183d7 100644
--- a/sound/soc/codecs/pcm1681.c
+++ b/sound/soc/codecs/pcm1681.c
@@ -172,16 +172,21 @@ static int pcm1681_hw_params(struct snd_pcm_substream *substream,
struct snd_soc_codec *codec = dai->codec;
struct pcm1681_private *priv = snd_soc_codec_get_drvdata(codec);
int val = 0, ret;
- int pcm_format = params_format(params);
priv->rate = params_rate(params);
switch (priv->format & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_RIGHT_J:
- if (pcm_format == SNDRV_PCM_FORMAT_S24_LE)
- val = 0x00;
- else if (pcm_format == SNDRV_PCM_FORMAT_S16_LE)
- val = 0x03;
+ switch (params_width(params)) {
+ case 24:
+ val = 0;
+ break;
+ case 16:
+ val = 3;
+ break;
+ default:
+ return -EINVAL;
+ }
break;
case SND_SOC_DAIFMT_I2S:
val = 0x04;
--
1.8.5.3
From: Mark Brown <broonie(a)linaro.org>
There is no meaningful code sharing between the PIO and DMA variants
(just the timeout calculation) so in order to make the code easier to
work with split the two cases.
Looking at the code it is not clear how the PIO version works for large
transmits, greater than FIFO size is only handled for RX.
Signed-off-by: Mark Brown <broonie(a)linaro.org>
---
drivers/spi/spi-s3c64xx.c | 166 +++++++++++++++++++++++++---------------------
1 file changed, 89 insertions(+), 77 deletions(-)
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index 19113538f5c6..b9ba7a3e7741 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -677,101 +677,110 @@ static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd,
return RX_FIFO_LVL(status, sdd);
}
-static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,
- struct spi_transfer *xfer, int dma_mode)
+static int wait_for_dma(struct s3c64xx_spi_driver_data *sdd,
+ struct spi_transfer *xfer)
{
void __iomem *regs = sdd->regs;
unsigned long val;
+ u32 status;
int ms;
/* millisecs to xfer 'len' bytes @ 'cur_speed' */
ms = xfer->len * 8 * 1000 / sdd->cur_speed;
ms += 10; /* some tolerance */
- if (dma_mode) {
- val = msecs_to_jiffies(ms) + 10;
- val = wait_for_completion_timeout(&sdd->xfer_completion, val);
- } else {
- u32 status;
- val = msecs_to_loops(ms);
- do {
+ val = msecs_to_jiffies(ms) + 10;
+ val = wait_for_completion_timeout(&sdd->xfer_completion, val);
+
+ /*
+ * If the previous xfer was completed within timeout, then
+ * proceed further else return -EIO.
+ * DmaTx returns after simply writing data in the FIFO,
+ * w/o waiting for real transmission on the bus to finish.
+ * DmaRx returns only after Dma read data from FIFO which
+ * needs bus transmission to finish, so we don't worry if
+ * Xfer involved Rx(with or without Tx).
+ */
+ if (val && !xfer->rx_buf) {
+ val = msecs_to_loops(10);
+ status = readl(regs + S3C64XX_SPI_STATUS);
+ while ((TX_FIFO_LVL(status, sdd)
+ || !S3C64XX_SPI_ST_TX_DONE(status, sdd))
+ && --val) {
+ cpu_relax();
status = readl(regs + S3C64XX_SPI_STATUS);
- } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
+ }
+
}
- if (dma_mode) {
- u32 status;
-
- /*
- * If the previous xfer was completed within timeout, then
- * proceed further else return -EIO.
- * DmaTx returns after simply writing data in the FIFO,
- * w/o waiting for real transmission on the bus to finish.
- * DmaRx returns only after Dma read data from FIFO which
- * needs bus transmission to finish, so we don't worry if
- * Xfer involved Rx(with or without Tx).
- */
- if (val && !xfer->rx_buf) {
- val = msecs_to_loops(10);
- status = readl(regs + S3C64XX_SPI_STATUS);
- while ((TX_FIFO_LVL(status, sdd)
- || !S3C64XX_SPI_ST_TX_DONE(status, sdd))
- && --val) {
- cpu_relax();
- status = readl(regs + S3C64XX_SPI_STATUS);
- }
+ /* If timed out while checking rx/tx status return error */
+ if (!val)
+ return -EIO;
- }
+ return 0;
+}
- /* If timed out while checking rx/tx status return error */
- if (!val)
- return -EIO;
- } else {
- int loops;
- u32 cpy_len;
- u8 *buf;
-
- /* If it was only Tx */
- if (!xfer->rx_buf) {
- sdd->state &= ~TXBUSY;
- return 0;
- }
+static int wait_for_pio(struct s3c64xx_spi_driver_data *sdd,
+ struct spi_transfer *xfer)
+{
+ void __iomem *regs = sdd->regs;
+ unsigned long val;
+ u32 status;
+ int loops;
+ u32 cpy_len;
+ u8 *buf;
+ int ms;
- /*
- * If the receive length is bigger than the controller fifo
- * size, calculate the loops and read the fifo as many times.
- * loops = length / max fifo size (calculated by using the
- * fifo mask).
- * For any size less than the fifo size the below code is
- * executed atleast once.
- */
- loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1);
- buf = xfer->rx_buf;
- do {
- /* wait for data to be received in the fifo */
- cpy_len = s3c64xx_spi_wait_for_timeout(sdd,
- (loops ? ms : 0));
+ /* millisecs to xfer 'len' bytes @ 'cur_speed' */
+ ms = xfer->len * 8 * 1000 / sdd->cur_speed;
+ ms += 10; /* some tolerance */
- switch (sdd->cur_bpw) {
- case 32:
- ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
- buf, cpy_len / 4);
- break;
- case 16:
- ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
- buf, cpy_len / 2);
- break;
- default:
- ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
- buf, cpy_len);
- break;
- }
+ val = msecs_to_loops(ms);
+ do {
+ status = readl(regs + S3C64XX_SPI_STATUS);
+ } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
- buf = buf + cpy_len;
- } while (loops--);
- sdd->state &= ~RXBUSY;
+
+ /* If it was only Tx */
+ if (!xfer->rx_buf) {
+ sdd->state &= ~TXBUSY;
+ return 0;
}
+ /*
+ * If the receive length is bigger than the controller fifo
+ * size, calculate the loops and read the fifo as many times.
+ * loops = length / max fifo size (calculated by using the
+ * fifo mask).
+ * For any size less than the fifo size the below code is
+ * executed atleast once.
+ */
+ loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1);
+ buf = xfer->rx_buf;
+ do {
+ /* wait for data to be received in the fifo */
+ cpy_len = s3c64xx_spi_wait_for_timeout(sdd,
+ (loops ? ms : 0));
+
+ switch (sdd->cur_bpw) {
+ case 32:
+ ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
+ buf, cpy_len / 4);
+ break;
+ case 16:
+ ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
+ buf, cpy_len / 2);
+ break;
+ default:
+ ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
+ buf, cpy_len);
+ break;
+ }
+
+ buf = buf + cpy_len;
+ } while (loops--);
+ sdd->state &= ~RXBUSY;
+
return 0;
}
@@ -928,7 +937,10 @@ static int s3c64xx_spi_transfer_one(struct spi_master *master,
spin_unlock_irqrestore(&sdd->lock, flags);
- status = wait_for_xfer(sdd, xfer, use_dma);
+ if (use_dma)
+ status = wait_for_dma(sdd, xfer);
+ else
+ status = wait_for_pio(sdd, xfer);
if (status) {
dev_err(&spi->dev, "I/O Error: rx-%d tx-%d res:rx-%c tx-%c len-%d\n",
--
1.8.5.3
I am a bit confused on the interrupt number for CNTVIRQ..CNTHPIRQ. Can
you please help here.
As per the exynos5 public manual
What is the difference between  CPU_nCNTHPIRQ[0] and CNTHPIRQ.
While the later has an interrupt ID 26, the former is part of a group
with combined interrupt id as 33 for core 0 and 54 for core 1.
For a timer interrupt which goes to PL2, which id should be used 26 or
33 for core 0 ?
Please clear this confusion.
Many Thanks
From: Vijaya Kumar K <Vijaya.Kumar(a)caviumnetworks.com>
Based on the step-handler and break-handler hooks patch from
Sandeepa, KGDB debugging support is added for EL1
debug in AArch64 mode.
In first patch, PSTATE.D is set correctly
In second patch,register layout is updated to be inline with GDB tool.
Basic GDB connection, break point set/clear and info commands
are supported except step/next debugging
With second patch, step/next debugging support is added, where in
pc is updated to point to the instruction to be stepped and
stopped.
With third patch, the compile time breakpoint instruction
reordering is fixed by making kgbd_breakpoint() as noinline
Tested with ARM64 simulator
v8:
- fixed comments on local_dbg_{save,restore} macros
- instruction_pointer() macro to return unsigned long to fix
compilation warnings
v7:
- Changes made to set PSTATE.D properly
- Performed KGDB boot tests
- Fixed compilation warnings in driver/misc/kgbdts.c
Results:
kgdb boot test:
[32927.237895] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[32927.266066] kgdb: Registered I/O driver kgdbts.
[32927.266419] kgdb: Waiting for connection from remote gdb...
[32927.268598] kgdbts:RUN plant and detach test
[32927.270683] kgdbts:RUN sw breakpoint test
[32927.287659] kgdbts:RUN bad memory access test
[32927.290322] kgdbts:RUN singlestep test 1000 iterations
[32927.330342] kgdbts:RUN singlestep [0/1000]
[32931.286356] kgdbts:RUN singlestep [100/1000]
[32935.242536] kgdbts:RUN singlestep [200/1000]
[32939.205392] kgdbts:RUN singlestep [300/1000]
[32943.169522] kgdbts:RUN singlestep [400/1000]
[32947.231868] kgdbts:RUN singlestep [500/1000]
[32951.188008] kgdbts:RUN singlestep [600/1000]
[32955.332243] kgdbts:RUN singlestep [700/1000]
[32959.467109] kgdbts:RUN singlestep [800/1000]
[32963.430888] kgdbts:RUN singlestep [900/1000]
[32967.346992] kgdbts:RUN do_fork for 100 breakpoints
kgdb test from sysfs:
~ # echo V1F1000 > /sys/module/kgdbts/parameters/kgdbts
[33231.554237] kgdb: Registered I/O driver kgdbts.
[33231.554677] kgdbts:RUN plant and detach test
[33231.557072] kgdbts:RUN sw breakpoint test
[33231.576980] kgdbts:RUN bad memory access test
[33231.580022] kgdbts:RUN singlestep test 1000 iterations
[33231.627056] kgdbts:RUN singlestep [0/1000]
[33235.954027] kgdbts:RUN singlestep [100/1000]
[33240.429086] kgdbts:RUN singlestep [200/1000]
[33244.687118] kgdbts:RUN singlestep [300/1000]
[33248.945191] kgdbts:RUN singlestep [400/1000]
[33253.203751] kgdbts:RUN singlestep [500/1000]
[33257.462019] kgdbts:RUN singlestep [600/1000]
[33261.817809] kgdbts:RUN singlestep [700/1000]
[33266.081268] kgdbts:RUN singlestep [800/1000]
[33270.339813] kgdbts:RUN singlestep [900/1000]
[33274.712404] kgdbts:RUN do_fork for 1000 breakpoints
~ #
v6:
- Change pstate register to 8 bytes to make endian nuetral.
Use GDB below GDB patch to display pstate in Big endian mode.
https://sourceware.org/ml/gdb-patches/2013-12/msg00720.html
Thanks to Andrew.
v5:
- Updated BRK #imm16 value to 0x400 & 0x401 as per recommendation
as per Marcus recommendataion
http://patchwork.ozlabs.org/patch/290801/
- Rebased to 3.13 AArch64 kernel
v4:
- Updated kgdb_single_step and kgdb_cpu_doing_single_step
variables properly based on gdb state
v3:
- Rebased to v4 version of Sandeepa Prabhu's patch (patch 1)
- Made dynamic break point instruction encoding generic
- Made ESR value encoding generic for dynamic and compile break point
- Used memcpy and memset to copy register contents to gdb buffer
- Fixed reordering of break point instruction by compiler with
patch 3
- Rebased against AAach64 upstream kernel
v2:
- Moved break instruction encoding to debug-monitors.h file
- Fixed endianess of compile break instruction encoding
- Updated I/O buffer sizes
- Updated register buffer size
- Remove changes to debug_exception handler in entry.S for
- ELR update and step debugging with update pc instead of ELR
- Rebased against AArch64 upstream kernel
v1:
- Initial patch-set
Vijaya Kumar K (6):
arm64: Add macros to manage processor debug state
arm64: KGDB: Add Basic KGDB support
arm64: KGDB: Add step debugging support
KGDB: make kgdb_breakpoint() as noinline
misc: debug: remove compilation warnings
arm64: KGDB: Add KGDB config
arch/arm64/Kconfig | 1 +
arch/arm64/include/asm/debug-monitors.h | 64 ++++--
arch/arm64/include/asm/irqflags.h | 48 +++++
arch/arm64/include/asm/kgdb.h | 84 ++++++++
arch/arm64/include/asm/ptrace.h | 2 +-
arch/arm64/kernel/Makefile | 1 +
arch/arm64/kernel/debug-monitors.c | 1 +
arch/arm64/kernel/kgdb.c | 336 +++++++++++++++++++++++++++++++
kernel/debug/debug_core.c | 2 +-
9 files changed, 520 insertions(+), 19 deletions(-)
create mode 100644 arch/arm64/include/asm/kgdb.h
create mode 100644 arch/arm64/kernel/kgdb.c
--
1.7.9.5
From: Mark Brown <broonie(a)linaro.org>
When the driver was converted to clk_prepare() the suspend path didn't
have any changes made so the clock remains prepared throughout the runtime
of the driver. Unprepare it when suspended so that any savings that can be
made as a result are made.
Signed-off-by: Mark Brown <broonie(a)linaro.org>
---
drivers/spi/spi-pl022.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-pl022.c b/drivers/spi/spi-pl022.c
index 2789b452e711..4ec49eae6141 100644
--- a/drivers/spi/spi-pl022.c
+++ b/drivers/spi/spi-pl022.c
@@ -2296,7 +2296,7 @@ pl022_remove(struct amba_device *adev)
*/
static void pl022_suspend_resources(struct pl022 *pl022, bool runtime)
{
- clk_disable(pl022->clk);
+ clk_disable_unprepare(pl022->clk);
if (runtime)
pinctrl_pm_select_idle_state(&pl022->adev->dev);
@@ -2312,7 +2312,7 @@ static void pl022_resume_resources(struct pl022 *pl022, bool runtime)
/* Then let's idle the pins until the next transfer happens */
pinctrl_pm_select_idle_state(&pl022->adev->dev);
- clk_enable(pl022->clk);
+ clk_prepare_enable(pl022->clk);
}
#endif
--
1.8.5.3
From: Vijaya Kumar K <Vijaya.Kumar(a)caviumnetworks.com>
Based on the step-handler and break-handler hooks patch from
Sandeepa, KGDB debugging support is added for EL1
debug in AArch64 mode.
In first patch, PSTATE.D is set correctly
In second patch,register layout is updated to be inline with GDB tool.
Basic GDB connection, break point set/clear and info commands
are supported except step/next debugging
With second patch, step/next debugging support is added, where in
pc is updated to point to the instruction to be stepped and
stopped.
With third patch, the compile time breakpoint instruction
reordering is fixed by making kgbd_breakpoint() as noinline
Tested with ARM64 simulator
v7:
- Changes made to set PSTATE.D properly
- Performed KGDB boot tests
- Fixed compilation warnings in driver/misc/kgbdts.c
Results:
kgdb boot test:
[32927.237895] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[32927.266066] kgdb: Registered I/O driver kgdbts.
[32927.266419] kgdb: Waiting for connection from remote gdb...
[32927.268598] kgdbts:RUN plant and detach test
[32927.270683] kgdbts:RUN sw breakpoint test
[32927.287659] kgdbts:RUN bad memory access test
[32927.290322] kgdbts:RUN singlestep test 1000 iterations
[32927.330342] kgdbts:RUN singlestep [0/1000]
[32931.286356] kgdbts:RUN singlestep [100/1000]
[32935.242536] kgdbts:RUN singlestep [200/1000]
[32939.205392] kgdbts:RUN singlestep [300/1000]
[32943.169522] kgdbts:RUN singlestep [400/1000]
[32947.231868] kgdbts:RUN singlestep [500/1000]
[32951.188008] kgdbts:RUN singlestep [600/1000]
[32955.332243] kgdbts:RUN singlestep [700/1000]
[32959.467109] kgdbts:RUN singlestep [800/1000]
[32963.430888] kgdbts:RUN singlestep [900/1000]
[32967.346992] kgdbts:RUN do_fork for 100 breakpoints
kgdb test from sysfs:
~ # echo V1F1000 > /sys/module/kgdbts/parameters/kgdbts
[33231.554237] kgdb: Registered I/O driver kgdbts.
[33231.554677] kgdbts:RUN plant and detach test
[33231.557072] kgdbts:RUN sw breakpoint test
[33231.576980] kgdbts:RUN bad memory access test
[33231.580022] kgdbts:RUN singlestep test 1000 iterations
[33231.627056] kgdbts:RUN singlestep [0/1000]
[33235.954027] kgdbts:RUN singlestep [100/1000]
[33240.429086] kgdbts:RUN singlestep [200/1000]
[33244.687118] kgdbts:RUN singlestep [300/1000]
[33248.945191] kgdbts:RUN singlestep [400/1000]
[33253.203751] kgdbts:RUN singlestep [500/1000]
[33257.462019] kgdbts:RUN singlestep [600/1000]
[33261.817809] kgdbts:RUN singlestep [700/1000]
[33266.081268] kgdbts:RUN singlestep [800/1000]
[33270.339813] kgdbts:RUN singlestep [900/1000]
[33274.712404] kgdbts:RUN do_fork for 1000 breakpoints
~ #
v6:
- Change pstate register to 8 bytes to make endian nuetral.
Use GDB below GDB patch to display pstate in Big endian mode.
https://sourceware.org/ml/gdb-patches/2013-12/msg00720.html
Thanks to Andrew.
v5:
- Updated BRK #imm16 value to 0x400 & 0x401 as per recommendation
as per Marcus recommendataion
http://patchwork.ozlabs.org/patch/290801/
- Rebased to 3.13 AArch64 kernel
v4:
- Updated kgdb_single_step and kgdb_cpu_doing_single_step
variables properly based on gdb state
v3:
- Rebased to v4 version of Sandeepa Prabhu's patch (patch 1)
- Made dynamic break point instruction encoding generic
- Made ESR value encoding generic for dynamic and compile break point
- Used memcpy and memset to copy register contents to gdb buffer
- Fixed reordering of break point instruction by compiler with
patch 3
- Rebased against AAach64 upstream kernel
v2:
- Moved break instruction encoding to debug-monitors.h file
- Fixed endianess of compile break instruction encoding
- Updated I/O buffer sizes
- Updated register buffer size
- Remove changes to debug_exception handler in entry.S for
- ELR update and step debugging with update pc instead of ELR
- Rebased against AArch64 upstream kernel
v1:
- Initial patch-set
Vijaya Kumar K (6):
arm64: Add macros to manage processor debug state
arm64: KGDB: Add Basic KGDB support
arm64: KGDB: Add step debugging support
KGDB: make kgdb_breakpoint() as noinline
misc: debug: remove compilation warnings
arm64: KGDB: Add KGDB config
arch/arm64/Kconfig | 1 +
arch/arm64/include/asm/debug-monitors.h | 65 ++++--
arch/arm64/include/asm/irqflags.h | 22 ++
arch/arm64/include/asm/kgdb.h | 84 ++++++++
arch/arm64/kernel/Makefile | 1 +
arch/arm64/kernel/debug-monitors.c | 3 +-
arch/arm64/kernel/kgdb.c | 336 +++++++++++++++++++++++++++++++
drivers/misc/kgdbts.c | 12 +-
kernel/debug/debug_core.c | 2 +-
9 files changed, 502 insertions(+), 24 deletions(-)
create mode 100644 arch/arm64/include/asm/kgdb.h
create mode 100644 arch/arm64/kernel/kgdb.c
--
1.7.9.5