This patch adds support for Samsung GH7 PCIe host controller.
Samsung GH7 PCIe controller driver has dependency on the PCI arm64
arch support. So, the Liviu Dudau's patcheset for creating generic
host_bridge from device tree [1] and supporting PCI in AArch64 [2]
are required.
This patch is marked as RFC, so any comment will be welcomed.
Thank you.
[1] http://www.spinics.net/lists/linux-pci/msg29786.html
[2] http://www.spinics.net/lists/linux-pci/msg29793.html
Jingoo Han (2)
PCI: designware: Add ARM64 PCI support
PCI: exynos: Add PCIe support for Samsung GH7 SoC
---
drivers/pci/host/Kconfig | 2 +-
drivers/pci/host/pci-exynos.c | 135 +++++++++++++++++++++++++++++++++---
drivers/pci/host/pcie-designware.c | 32 +++++++++
3 files changed, 158 insertions(+), 11 deletions(-)
Best regards,
Jingoo Han
From: Arnd Bergmann <arnd(a)arndb.de>
The sh_mobile_lcdcfb driver calls interfaces provided
by the corresponding "meram" helper. This fails if meram
is a module but lcdcfb is built-in.
To work around it, this uses special Kconfig magic to
only allow lcdcfb to be built if
a) both are modules,
b) meram is built-in, or
c) meram is disabled and the helpers stubbed out
Changing meram from 'y' to 'm' now forces clcd to
be a module as well, which seems to be the desired
behavior.
Signed-off-by: Arnd Bergmann <arnd(a)arndb.de>
Signed-off-by: Peter Griffin <peter.griffin(a)linaro.org>
Cc: Simon Horman <horms+renesas(a)verge.net.au>
Cc: Magnus Damm <magnus.damm(a)gmail.com>
Cc: linux-sh(a)vger.kernel.org
Cc: Jean-Christophe Plagniol-Villard <plagnioj(a)jcrosoft.com>
Cc: Tomi Valkeinen <tomi.valkeinen(a)ti.com>
Cc: linux-fbdev(a)vger.kernel.org
---
drivers/video/fbdev/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/video/fbdev/Kconfig b/drivers/video/fbdev/Kconfig
index e1f4727..a4116bf 100644
--- a/drivers/video/fbdev/Kconfig
+++ b/drivers/video/fbdev/Kconfig
@@ -1971,6 +1971,7 @@ config FB_W100
config FB_SH_MOBILE_LCDC
tristate "SuperH Mobile LCDC framebuffer support"
depends on FB && (SUPERH || ARCH_SHMOBILE) && HAVE_CLK
+ depends on FB_SH_MOBILE_MERAM || !FB_SH_MOBILE_MERAM
select FB_SYS_FILLRECT
select FB_SYS_COPYAREA
select FB_SYS_IMAGEBLIT
--
1.7.9.5
Hi,
File: hrtimer.c
Function: hrtimer_get_next_event()
I was looking closely at what's waking up my system and
found this piece of code:
ktime_t hrtimer_get_next_event(void)
{
if (!hrtimer_hres_active()) {
find next hrtimer event ....
}
}
Which probably means that: "don't consider hrtimers for getting
next timer event if we are running ticks in high resolution mode".
And I couldn't understand why is it so?
When hres_active isn't set, we run hrtimer handlers from timer
handlers, which means that timers would be sufficient in finding
the next event and we don't need to check for hrtimers.
But when hres_active is set, hrtimers could be set to fire before
the next timer event and so we must take them into account.
I am new to this whole world of core frameworks and might be
missing something very very obvious. But its always better to
ask than to ignore and think that things are probably fine and
just shut up.
Thanks for your patience during my learning curve :)
--
viresh
If DCACHE_WORD_ACCESS is enabled big endian image failed to
boot. commit 7bc13fd33adb9536bd73965cd46bbf7377df097c
"arm64: dcache: select DCACHE_WORD_ACCESS for little-endian CPUs"
enabled this setting for both big endian and little endian
cpus. And code in commit itself seems to be endian agnostic,
however other, i.e C, code that sits under DCACHE_WORD_ACCESS
seems to be not endian agnostic, I could not figure out where
though.
Solution is to enable DCACHE_WORD_ACCESS only if little
endian mode is enabled (default).
Signed-off-by: Victor Kamensky <victor.kamensky(a)linaro.org>
---
arch/arm64/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index e6e4d37..106ac4f 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -13,7 +13,7 @@ config ARM64
select CLONE_BACKWARDS
select COMMON_CLK
select CPU_PM if (SUSPEND || CPU_IDLE)
- select DCACHE_WORD_ACCESS
+ select DCACHE_WORD_ACCESS if !CPU_BIG_ENDIAN
select GENERIC_CLOCKEVENTS
select GENERIC_CLOCKEVENTS_BROADCAST if SMP
select GENERIC_CPU_AUTOPROBE
--
1.8.1.4
Hi Guys,
This second version of patch to flush icache and dcache after
uprobes xol write to make written instruction available in icache.
Please see [1] for initial discussion.
This patch follows Russell's suggestion, and function that does
cache flush after xol slot instruction write is shared/reused
with similar one implemented already for ptrace code.
In order to reuse common implementation but to avoid vma use
by xol_get_insn_slot I split flush_ptrace_access into two
functions. Where first part retrieves all required conditions
from vma and places them into flags variable and then calls
second function which is common code.
Also I had to change xol_get_insn_slot function to map page
into kernel explicitly within function without use of
copy_to_page helper because ARM cache flush code need both
kernel address through which instruction write happens and
virtual address of user-land process where instruction will
end up. I hope this call back is universal enough so other
CPU could implement their cache invalidation/sync after
uprobes xol instruction write logic based on provided
parameters.
I've tested it on Arndale board with my SystemTap test case
that had cache problem before. Disassemble of
flush_uprobe_xol_access in case of Arndale shows that compiler
does good job and optimizes out all flags check effectively
leaving on this cpu call to flush_icache_alias or call to
v7_coherent_user_range (__cpuc_coherent_kern_range).
Also tested basic user-level debugging.
Wondering on what ARM boards/cpus could we test cache_is_vivt()
and cache_is_vipt_aliasing cases ...
Just to summarize, please note on [1] there were couple other
suggestions:
Oleg suggested to use flush_icache_user_range but Russell
argument was that meaning of the function is lost and on ARM
it is not implemented in such way that it could address the
issue anyway. Please see [2] for details. Note it would has
vma problem use or not, that should be hacked.
Dave Martin suggested to use flush_icache_range, which is
effectively better way to call
__cpuc_coherent_[kern|user]_range(s,e), that was originally
suggested. But Russell explained that it won't be enough in
case of user-land process pages and variety of cache types have
to be covered. Note for kernel pages it would be OK and it is
used in multiple places like kprobes, modules, etc.
Thanks,
Victor
[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2014-April/245595.htmlhttp://lists.infradead.org/pipermail/linux-arm-kernel/2014-April/245427.html
[2] http://lists.infradead.org/pipermail/linux-arm-kernel/2014-April/245605.html
Victor Kamensky (1):
ARM: uprobes need icache flush after xol write
arch/arm/include/asm/cacheflush.h | 2 ++
arch/arm/kernel/uprobes.c | 6 ++++++
arch/arm/mm/flush.c | 41 +++++++++++++++++++++++++++++++++------
include/linux/uprobes.h | 3 +++
kernel/events/uprobes.c | 33 +++++++++++++++++++++++++------
5 files changed, 73 insertions(+), 12 deletions(-)
--
1.8.1.4
On Tue, Apr 22, 2014 at 05:39:28PM -0700, Dmitry Torokhov wrote:
> On Tue, Apr 22, 2014 at 10:18:21PM +0100, Mark Brown wrote:
> > Remove the bitrotted comment, though in actual fact the use case mentioned
> > is a great use for spi_async() since it would cut down on latency handling
> > the interrupt by saving us a context switch before we start SPI.
> > This was previously implemented, it was removed in commit b534422b2d11
> > (Input: ad7877 - switch to using threaded IRQ) for code complexity reasons.
> > It may be better to revert that commit instead.
> Hmm, maybe.. although I think original would cause device 'stuck' if
> call to spi_async() fails, so probably not a straight revert...
Probably best just to apply this, then - someone can always reimplement
if they need to.
Hello, hopefully this is the correct mailing list for this question:
I'm working on a derivative of the mainline Linux 3.8 kernel and I'm trying
to enable ARM kdump functionality to collect crashdumps when we have kernel
problems. But, there's some kind of unresolved issue in
arch/arm/mm/ioremap.c which prevents /proc/vmcore from being able to
function properly. I checked and this appears to still be in kernel.org
Linux 3.13. The target is a normal, recent ARMv7 chip.
Has this issue been addressed in any version of Linaro's kernel? Or, is
there a work-around? If not, how does a crashdump file get generated when/if
the Linaro kernel crashes or a driver faults?
>> WARNING: at arch/arm/mm/ioremap.c:244
__arm_ioremap_pfn_caller+0x1d8/0x1f0()
>> Modules linked in:
>> [<c0016660>] (unwind_backtrace+0x0/0x138) from [<c0020480>]
(warn_slowpath_common+0x4c/0x64)
>> [<c0020480>] (warn_slowpath_common+0x4c/0x64) from [<c00204b4>]
(warn_slowpath_null+0x1c/0x24)
>> [<c00204b4>] (warn_slowpath_null+0x1c/0x24) from [<c0018e9c>]
(__arm_ioremap_pfn_caller+0x1d8/0x1f0)
>> [<c0018e9c>] (__arm_ioremap_pfn_caller+0x1d8/0x1f0) from [<c0018f20>]
(__arm_ioremap_caller+0x54/0x5c)
>> [<c0018f20>] (__arm_ioremap_caller+0x54/0x5c) from [<c0018c58>]
(__arm_ioremap+0x18/0x1c)
>> [<c0018c58>] (__arm_ioremap+0x18/0x1c) from [<c00168fc>]
(copy_oldmem_page+0x34/0xc0)
>> [<c00168fc>] (copy_oldmem_page+0x34/0xc0) from [<c010350c>]
(read_from_oldmem+0xb8/0xe4)
>> [<c010350c>] (read_from_oldmem+0xb8/0xe4) from [<c05c37e0>]
(parse_crash_elf32_headers+0x184/0x43c)
>> [<c05c37e0>] (parse_crash_elf32_headers+0x184/0x43c) from [<c05c3b64>]
(vmcore_init+0xcc/0x198)
>> [<c05c3b64>] (vmcore_init+0xcc/0x198) from [<c000863c>]
(do_one_initcall+0x34/0x184)
>> [<c000863c>] (do_one_initcall+0x34/0x184) from [<c05b28dc>]
(kernel_init_freeable+0xfc/0x1c8)
>> [<c05b28dc>] (kernel_init_freeable+0xfc/0x1c8) from [<c04326d4>]
(kernel_init+0x8/0xe4)
>> [<c04326d4>] (kernel_init+0x8/0xe4) from [<c000ec58>]
(ret_from_fork+0x14/0x3c)
>>
>> arch/arm/mm/ioremap.c:244
>> /*
>> * Don't allow RAM to be mapped - this causes problems with
ARMv6+
>> */
>> if (WARN_ON(pfn_valid(pfn)))
>> return NULL;
Thanks in advance for any help.
-andy
From: Mark Brown <broonie(a)linaro.org>
While searching for users of spi_async() I found a reference in the ad7877
driver to using it to initiate data transfer from the interrupt handler.
However there is no code for this, instead the interrupt handler is a
threaded handler and uses spi_sync() instead.
Remove the bitrotted comment, though in actual fact the use case mentioned
is a great use for spi_async() since it would cut down on latency handling
the interrupt by saving us a context switch before we start SPI.
This was previously implemented, it was removed in commit b534422b2d11
(Input: ad7877 - switch to using threaded IRQ) for code complexity reasons.
It may be better to revert that commit instead.
Signed-off-by: Mark Brown <broonie(a)linaro.org>
---
drivers/input/touchscreen/ad7877.c | 5 -----
1 file changed, 5 deletions(-)
diff --git a/drivers/input/touchscreen/ad7877.c b/drivers/input/touchscreen/ad7877.c
index 6793c85903ae..523865daa1d3 100644
--- a/drivers/input/touchscreen/ad7877.c
+++ b/drivers/input/touchscreen/ad7877.c
@@ -210,11 +210,6 @@ static bool gpio3;
module_param(gpio3, bool, 0);
MODULE_PARM_DESC(gpio3, "If gpio3 is set to 1 AUX3 acts as GPIO3");
-/*
- * ad7877_read/write are only used for initial setup and for sysfs controls.
- * The main traffic is done using spi_async() in the interrupt handler.
- */
-
static int ad7877_read(struct spi_device *spi, u16 reg)
{
struct ser_req *req;
--
1.9.2
This is a note to let you know that I have just added a patch titled
tick-common: Fix wrong check in tick_check_replacement()
to the linux-3.11.y-queue branch of the 3.11.y.z extended stable tree
which can be found at:
http://kernel.ubuntu.com/git?p=ubuntu/linux.git;a=shortlog;h=refs/heads/lin…
If you, or anyone else, feels it should not be added to this tree, please
reply to this email.
For more information about the 3.11.y.z tree, see
https://wiki.ubuntu.com/Kernel/Dev/ExtendedStable
Thanks.
-Luis
------
>From 39bbe41d9e322c01c6c67cf71763dd66d9172a94 Mon Sep 17 00:00:00 2001
From: Viresh Kumar <viresh.kumar(a)linaro.org>
Date: Tue, 15 Apr 2014 10:54:37 +0530
Subject: tick-common: Fix wrong check in tick_check_replacement()
commit 521c42990e9d561ed5ed9f501f07639d0512b3c9 upstream.
tick_check_replacement() returns if a replacement of clock_event_device is
possible or not. It does this as the first check:
if (tick_check_percpu(curdev, newdev, smp_processor_id()))
return false;
Thats wrong. tick_check_percpu() returns true when the device is
useable. Check for false instead.
[ tglx: Massaged changelog ]
Signed-off-by: Viresh Kumar <viresh.kumar(a)linaro.org>
Cc: linaro-kernel(a)lists.linaro.org
Cc: fweisbec(a)gmail.com
Cc: Arvind.Chauhan(a)arm.com
Cc: linaro-networking(a)linaro.org
Link: http://lkml.kernel.org/r/486a02efe0246635aaba786e24b42d316438bf3b.139753798…
Signed-off-by: Thomas Gleixner <tglx(a)linutronix.de>
Signed-off-by: Luis Henriques <luis.henriques(a)canonical.com>
---
kernel/time/tick-common.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/kernel/time/tick-common.c b/kernel/time/tick-common.c
index 64522ec..271ce26 100644
--- a/kernel/time/tick-common.c
+++ b/kernel/time/tick-common.c
@@ -260,7 +260,7 @@ static bool tick_check_preferred(struct clock_event_device *curdev,
bool tick_check_replacement(struct clock_event_device *curdev,
struct clock_event_device *newdev)
{
- if (tick_check_percpu(curdev, newdev, smp_processor_id()))
+ if (!tick_check_percpu(curdev, newdev, smp_processor_id()))
return false;
return tick_check_preferred(curdev, newdev);
--
1.9.1
There have been confusion all the time about which mailing list to follow for
cpufreq activities, linux-pm(a)vger.kernel.org or cpufreq(a)vger.kernel.org.
As Maintainers always wanted people to send patches to linux-pm(a)vger.kernel.org
and kernel source asked them to use cpufreq(a)vger.kernel.org.
Lets make linux-pm(a)vger.kernel.org the official mailing list for cpufreq stuff
and remove all references of cpufreq(a)vger.kernel.org from kernel source.
Later, we can remove the list as well from vger.kernel.org.
Signed-off-by: Viresh Kumar <viresh.kumar(a)linaro.org>
---
Documentation/ABI/testing/sysfs-devices-system-cpu | 4 ++--
Documentation/cpu-freq/index.txt | 4 ++--
MAINTAINERS | 2 --
drivers/cpufreq/speedstep-centrino.c | 2 +-
tools/power/cpupower/Makefile | 2 +-
tools/power/cpupower/debug/kernel/cpufreq-test_tsc.c | 2 +-
6 files changed, 7 insertions(+), 9 deletions(-)
diff --git a/Documentation/ABI/testing/sysfs-devices-system-cpu b/Documentation/ABI/testing/sysfs-devices-system-cpu
index d5a0d33..acb9bfc 100644
--- a/Documentation/ABI/testing/sysfs-devices-system-cpu
+++ b/Documentation/ABI/testing/sysfs-devices-system-cpu
@@ -128,7 +128,7 @@ Description: Discover cpuidle policy and mechanism
What: /sys/devices/system/cpu/cpu#/cpufreq/*
Date: pre-git history
-Contact: cpufreq(a)vger.kernel.org
+Contact: linux-pm(a)vger.kernel.org
Description: Discover and change clock speed of CPUs
Clock scaling allows you to change the clock speed of the
@@ -146,7 +146,7 @@ Description: Discover and change clock speed of CPUs
What: /sys/devices/system/cpu/cpu#/cpufreq/freqdomain_cpus
Date: June 2013
-Contact: cpufreq(a)vger.kernel.org
+Contact: linux-pm(a)vger.kernel.org
Description: Discover CPUs in the same CPU frequency coordination domain
freqdomain_cpus is the list of CPUs (online+offline) that share
diff --git a/Documentation/cpu-freq/index.txt b/Documentation/cpu-freq/index.txt
index 3d0b915..dc024ab 100644
--- a/Documentation/cpu-freq/index.txt
+++ b/Documentation/cpu-freq/index.txt
@@ -35,8 +35,8 @@ Mailing List
------------
There is a CPU frequency changing CVS commit and general list where
you can report bugs, problems or submit patches. To post a message,
-send an email to cpufreq(a)vger.kernel.org, to subscribe go to
-http://vger.kernel.org/vger-lists.html#cpufreq and follow the
+send an email to linux-pm(a)vger.kernel.org, to subscribe go to
+http://vger.kernel.org/vger-lists.html#linux-pm and follow the
instructions there.
Links
diff --git a/MAINTAINERS b/MAINTAINERS
index 6dc67b1..88b60d9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2415,7 +2415,6 @@ F: drivers/net/ethernet/ti/cpmac.c
CPU FREQUENCY DRIVERS
M: Rafael J. Wysocki <rjw(a)rjwysocki.net>
M: Viresh Kumar <viresh.kumar(a)linaro.org>
-L: cpufreq(a)vger.kernel.org
L: linux-pm(a)vger.kernel.org
S: Maintained
T: git git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git
@@ -2426,7 +2425,6 @@ F: include/linux/cpufreq.h
CPU FREQUENCY DRIVERS - ARM BIG LITTLE
M: Viresh Kumar <viresh.kumar(a)linaro.org>
M: Sudeep Holla <sudeep.holla(a)arm.com>
-L: cpufreq(a)vger.kernel.org
L: linux-pm(a)vger.kernel.org
W: http://www.arm.com/products/processors/technologies/biglittleprocessing.php
S: Maintained
diff --git a/drivers/cpufreq/speedstep-centrino.c b/drivers/cpufreq/speedstep-centrino.c
index 6723f03..7d4a315 100644
--- a/drivers/cpufreq/speedstep-centrino.c
+++ b/drivers/cpufreq/speedstep-centrino.c
@@ -28,7 +28,7 @@
#include <asm/cpu_device_id.h>
#define PFX "speedstep-centrino: "
-#define MAINTAINER "cpufreq(a)vger.kernel.org"
+#define MAINTAINER "linux-pm(a)vger.kernel.org"
#define INTEL_MSR_RANGE (0xffff)
diff --git a/tools/power/cpupower/Makefile b/tools/power/cpupower/Makefile
index cbfec92..3651db7 100644
--- a/tools/power/cpupower/Makefile
+++ b/tools/power/cpupower/Makefile
@@ -62,7 +62,7 @@ LIB_MAJ= 0.0.0
LIB_MIN= 0
PACKAGE = cpupower
-PACKAGE_BUGREPORT = cpufreq(a)vger.kernel.org
+PACKAGE_BUGREPORT = linux-pm(a)vger.kernel.org
LANGUAGES = de fr it cs pt
diff --git a/tools/power/cpupower/debug/kernel/cpufreq-test_tsc.c b/tools/power/cpupower/debug/kernel/cpufreq-test_tsc.c
index 0f10b81..5224ee5 100644
--- a/tools/power/cpupower/debug/kernel/cpufreq-test_tsc.c
+++ b/tools/power/cpupower/debug/kernel/cpufreq-test_tsc.c
@@ -18,7 +18,7 @@
* 5.) if the third value, "diff_pmtmr", changes between 2. and 4., the
* TSC-based delay routine on the Linux kernel does not correctly
* handle the cpufreq transition. Please report this to
- * cpufreq(a)vger.kernel.org
+ * linux-pm(a)vger.kernel.org
*/
#include <linux/kernel.h>
--
1.7.12.rc2.18.g61b472e
This patch series adds Qualcomm SD Card Controller support in pl180 mmci
driver. QCom SDCC is basically a pl180, but bit more customized, some of the
register layouts and offsets are different to the ones mentioned in pl180
datasheet. The plan is to totally remove the standalone SDCC driver
drivers/mmc/host/msm_sdcc.* and start using generic mmci driver for all
Qualcomm parts, as we get chance to test on other Qcom boards.
To start using the existing mmci driver, a fake amba id for Qualcomm is added
in patches:
ARM: amba: Add Qualcomm vendor ID.
mmc: mmci: Add Qualcomm Id to amba id table.
Second change is, adding a 3 clock cycle delay for register writes on QCOM SDCC
registers, which is done in patches:
mmc: mmci: Add register read/write wrappers.
mmc: mmci: Add write delay to variant structure.
mmc: mmci: Qcomm: Add 3 clock cycle delay after each register write
Third change was to accommodate DATCTRL and MMCICLK register layout changes in
Qcom SDCC. Which is done in patches:
mmc: mmci: Add Qcom datactrl register variant
mmc: mmci: Add Qcom variations to MCICommand register.
mmc: mmci: Qcom fix MCICLK register settings.
mmc: mmci: Add clock support for Qualcomm.
Fourth major change was to add qcom specfic pio read function, the need for
this is because the way MCIFIFOCNT register behaved in QCOM SDCC is very
different to the one in pl180. This change is done in patch:
mmc: mmci: Add Qcom specific pio_read function.
Last some Qcom unrelated changes to support Qcom are done in patches:
mmc: mmci: use NSEC_PER_SEC macro
mmc: mmci: move ST specific register extensions access under condition.
This patches are tested in PIO mode on IFC8064 board with both eMMC and
external SD card. I would appreciate any feedback/suggestions on the overall
approach.
Thanks,
srini
Srinivas Kandagatla (12):
ARM: amba: Add Qualcomm vendor ID.
mmc: mmci: Add Qualcomm Id to amba id table
mmc: mmci: Add Qcom datactrl register variant
mmc: mmci: Add register read/write wrappers.
mmc: mmci: use NSEC_PER_SEC macro
mmc: mmci: Add write delay to variant structure.
mmc: mmci: Qcomm: Add 3 clock cycle delay after each register write
mmc: mmci: move ST specific register extensions access under condition.
mmc: mmci: Qcom fix MCICLK register settings.
mmc: mmci: Add clock support for Qualcomm.
mmc: mmci: Add Qcom variations to MCICommand register.
mmc: mmci: Add Qcom specific pio_read function.
drivers/mmc/host/mmci.c | 239 +++++++++++++++++++++++++++++++++-------------
drivers/mmc/host/mmci.h | 28 ++++++
include/linux/amba/bus.h | 1 +
3 files changed, 202 insertions(+), 66 deletions(-)
--
1.7.9.5
Hi Guys,
Here is my understanding of Dave's and Russell's suggestion on [1]
to use direct write of xol slot instructions to user space. Now
posting patch through 'git send-email' since, as it was noted, my
mailer corrupts patches otherwise.
Note default case with __copy_to_user is NOT tested. It addresses
David's remark.
Personally, I am very concerned about this patch because it creates
writable and executable page in traced process. The way how uprobes
is implemented such page will stay in process even if all uprobes
are detached from process. IMHO it may create possible attack hole.
I would prefer to see any executable memory read-only all the time.
On top of that, at least in ARM case xol page address is not even
randomized, which was perfectly fine with current nowrite/noread,
just execute permissions.
Patch follows this cover letter.
Thanks,
Victor
[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2014-April/247763.html
Victor Kamensky (1):
ARM: uprobes xol write directly to userspace
arch/arm/kernel/uprobes.c | 8 ++++++++
include/linux/uprobes.h | 3 +++
kernel/events/uprobes.c | 28 +++++++++++++++++++---------
3 files changed, 30 insertions(+), 9 deletions(-)
--
1.8.1.4
This is LSK CMA backporting for armv8. I add some kernel config for CMA
enabling. With these config, kernel will be booted with following message:
cma: CMA: reserved 16 MiB at xxxxxxxx
Linaro Stable Kernel git tree:
git://git.linaro.org/kernel/linux-linaro-stable.git
Marek,
I saw you had mentioned testing this feature with cma-regions compatibility
layer and videobuf2-cma memory allocator module. But I didn't get it by google.
Could you give a link for them?
And I will more appreciate if you'd like to take a glance for review.
Thanks!
Alex
[PATCH 1/6] mm/cma: Move dma contiguous changes into a seperate
[PATCH 2/6] drivers: dma-contiguous: clean source code and prepare
[PATCH 3/6] arm64: Enable CMA
[PATCH 4/6] arm64: add CMA support for armv8
[PATCH 5/6] arm64: fix build error if DMA_CMA is enabled
[PATCH 6/6] arm64: Align CMA sizes to PAGE_SIZE
Patch to avoid calling kernel_power_off when pm_power_off is null.
When pm_power_off is null, the platform will not power off in
kernel_power_off. Currently, hibernate will call kernel_power_off and
then move on to kernel_halt. However, this calls the notifier chain
twice with a different parameter. In kernel/reboot.c, this is avoided
by checking if pm_power_off is NULL and bypassing kernel_power_off.
Mostly, this is a check if anyone is dependent on having the reboot
notifier called 2x if pm_power_off is null. There are some panics if
it's called this way in some drivers.
Tested this on omap beaglebone black, but have not tried on other
hardware. Please let me know if you can test this on another platform
and the results.
Thanks,
Sebastian
Fix e26a9e00afc482b971afcaef1db8c9034d4d6d7c 'ARM: Better
virt_to_page() handling' replaced __pv_phys_offset with
__pv_phys_pfn_offset. Also note that size of __pv_phys_offset
was quad but size of __pv_phys_pfn_offset is word. Instruction
that used to update __pv_phys_offset which address is in r6
had to update low word of __pv_phys_offset so it used #LOW_OFFSET
macro for store offset. Now when size of __pv_phys_pfn_offset is
word, no difference between little endian and big endian should
exist - i.e no offset should be used when __pv_phys_pfn_offset
is stored.
Note that for little endian image proposed change is noop,
since in little endian case #LOW_OFFSET is defined 0 anyway.
Reported-by: Taras Kondratiuk <taras.kondratiuk(a)linaro.org>
Signed-off-by: Victor Kamensky <victor.kamensky(a)linaro.org>
---
arch/arm/kernel/head.S | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index f8c0883..591d6e4 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -587,7 +587,7 @@ __fixup_pv_table:
add r6, r6, r3 @ adjust __pv_phys_pfn_offset address
add r7, r7, r3 @ adjust __pv_offset address
mov r0, r8, lsr #12 @ convert to PFN
- str r0, [r6, #LOW_OFFSET] @ save computed PHYS_OFFSET to __pv_phys_pfn_offset
+ str r0, [r6] @ save computed PHYS_OFFSET to __pv_phys_pfn_offset
strcc ip, [r7, #HIGH_OFFSET] @ save to __pv_offset high bits
mov r6, r3, lsr #24 @ constant for add/sub instructions
teq r3, r6, lsl #24 @ must be 16MiB aligned
--
1.8.1.4
Hi,
As it was discussed on [1] today, here is potential ARM specific
fix for uprobes dcache/icache flush problem. I am aware that
other options are still under discussion. This patch is provided for
reference only as one of possible solutions.
The xol slot flush code shares code with ARM backend of
copy_to_user_page - flush_ptrace_access function. But code and new
implementation of flush_uprobe_xol_access modified in such way that
xol flush does need vma.
Changes since V2 [2] version:
x) address Dave Long's comment about passing checkpatch
x) addressed Oleg's comment and instead of arch_uprobe_flush_xol_access
function use arch_uprobe_copy_ixol function that maps kernel pages,
copies, and flush caches
x) removed FLAG_UA_BROADCAST, during discussion on [1] it was
elaborated that task executing xol single step could be
migrated to another CPU, so we need to take care of remote
icaches if CPU does not support remote snooping. I.e
flush_uprobe_xol_access will check cache_ops_need_broadcast()
and perform smp_call_function on SMP CPUs that do not
support remote snooping.
x) added preempt_disable/preempt_enable in arch_uprobe_copy_ixol as
copy_to_user_page does. I admit that I have some guesses, but I
don't completely understand why copy_to_user_page does that, so
playing on safe side - added it similar to copy_to_user_page code.
Thanks,
Victor
[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2014-April/247611.html
[2] http://lists.infradead.org/pipermail/linux-arm-kernel/2014-April/245743.html
Victor Kamensky (1):
ARM: uprobes need icache flush after xol write
arch/arm/include/asm/cacheflush.h | 2 ++
arch/arm/kernel/uprobes.c | 22 ++++++++++++++++++++++
arch/arm/mm/flush.c | 33 ++++++++++++++++++++++++++++-----
include/linux/uprobes.h | 3 +++
kernel/events/uprobes.c | 25 +++++++++++++++++--------
5 files changed, 72 insertions(+), 13 deletions(-)
--
1.8.1.4
In switch_hrtimer_base() we are calling hrtimer_check_target() which guarantees
this:
/*
* With HIGHRES=y we do not migrate the timer when it is expiring
* before the next event on the target cpu because we cannot reprogram
* the target cpu hardware and we would cause it to fire late.
*
* Called with cpu_base->lock of target cpu held.
*/
But switch_hrtimer_base() is only called from one place, i.e.
__hrtimer_start_range_ns() and at that point (where we call
switch_hrtimer_base()) expiration time is not yet known as we call this routine
later: hrtimer_set_expires_range_ns().
To fix this, we need to find the updated expiry time before calling
switch_hrtimer_base().
Signed-off-by: Viresh Kumar <viresh.kumar(a)linaro.org>
---
Hi Thomas,
I have sent this previously as part of: https://lkml.org/lkml/2014/4/4/23
But as you asked to send bugfixes without any dependencies for ticks patches, I
thought of sending bugfixes separately for timers too. This was the only bugfix
from that series and other patches don't conflict with it, so I am not resending
other patches from above series again.
Not adding any stable tags as this is broken from a long long time and don't
know if you want to fix it for those kernels.
kernel/hrtimer.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/kernel/hrtimer.c b/kernel/hrtimer.c
index d55092c..c86b95a 100644
--- a/kernel/hrtimer.c
+++ b/kernel/hrtimer.c
@@ -968,11 +968,8 @@ int __hrtimer_start_range_ns(struct hrtimer *timer, ktime_t tim,
/* Remove an active timer from the queue: */
ret = remove_hrtimer(timer, base);
- /* Switch the timer base, if necessary: */
- new_base = switch_hrtimer_base(timer, base, mode & HRTIMER_MODE_PINNED);
-
if (mode & HRTIMER_MODE_REL) {
- tim = ktime_add_safe(tim, new_base->get_time());
+ tim = ktime_add_safe(tim, base->get_time());
/*
* CONFIG_TIME_LOW_RES is a temporary way for architectures
* to signal that they simply return xtime in
@@ -987,6 +984,9 @@ int __hrtimer_start_range_ns(struct hrtimer *timer, ktime_t tim,
hrtimer_set_expires_range_ns(timer, tim, delta_ns);
+ /* Switch the timer base, if necessary: */
+ new_base = switch_hrtimer_base(timer, base, mode & HRTIMER_MODE_PINNED);
+
timer_stats_hrtimer_set_start_info(timer);
leftmost = enqueue_hrtimer(timer, new_base);
--
1.7.12.rc2.18.g61b472e
Part of this patchset was previously part of the larger tasks packing patchset
[1]. I have splitted the latter in 3 different patchsets (at least) to make the
thing easier.
-configuration of sched_domain topology [2]
-update and consolidation of cpu_power (this patchset)
-tasks packing algorithm
SMT system is no more the only system that can have a CPUs with capacity that
is different from the default value. We need to extend the use of
cpu_power_orig to all kind of platform so the scheduler will have both the
maximum capacity (cpu_power_orig/power_orig) and the current capacity
(cpu_power/power) of CPUs and groups of the sched_domains.
During load balance, the scheduler evaluates the number of tasks that a group
of CPUs can handle. The current method ensures that we will not return more
capacity than number of real cores but it returns wrong value for group of
LITTLE cores and in some situation for SMT system. The proposed solution
computes the ratio between CPUs and cores for a group durint the init sequence
and uses it with power and power_orig to return the current capacity of a
group.
[1] https://lkml.org/lkml/2013/10/18/121
[2] https://lkml.org/lkml/2014/3/19/377
Vincent Guittot (4):
sched: extend the usage of cpu_power_orig
ARM: topology: use new cpu_power interface
sched: fix computed capacity for HMP
sched: add per group cpu_power_orig
arch/arm/kernel/topology.c | 4 ++--
kernel/sched/core.c | 9 ++++++++-
kernel/sched/fair.c | 31 +++++++++++++++++++------------
kernel/sched/sched.h | 3 ++-
4 files changed, 31 insertions(+), 16 deletions(-)
--
1.9.0
Hi Thomas,
These are separate cleanups from the timers/hrtimers ones I did. I was waiting
for the merge window to close in order to send these and by the time it
happened, I got a long pending list.
These are mostly cleanups, reorders for better readability or efficiency, and
few bugfixes.
I have pushed these here as well:
git://git.linaro.org/people/viresh.kumar/linux.git tick-cleanups
They will be tested by kbuild bot also starting from tonight.
Viresh Kumar (38):
tick: align to Coding Guidelines
tick: update doc comments for struct tick_sched
tick: rearrange members of 'struct tick_sched'
tick: move declaration of tick_cpu_device to tick.h
tick: move definition of tick_get_device() to tick.h
tick: create tick_get_cpu_device() to get tick_cpu_device on this cpu
tick-oneshot: drop local_irq_save/restore from
tick_switch_to_oneshot()
tick-oneshot: move tick_is_oneshot_available() to tick-oneshot.c
tick-oneshot: remove tick_resume_oneshot()
tick-common: remove extra checks from tick_check_new_device()
tick-common: fix wrong check in tick_check_replacement()
tick-common: call tick_check_percpu() from tick_check_preferred()
tick-common: don't check tick_oneshot_mode_active() from
tick_check_preferred()
tick-common: do additional checks in tick_check_preferred()
tick-common: remove tick_check_replacement()
tick-common: don't pass cpumask to tick_setup_device()
tick-common: call tick_install_replacement() from
tick_check_new_device()
tick-common: don't set mode to CLOCK_EVT_MODE_UNUSED in
tick_shutdown()
tick-common: remove local variable 'broadcast' from tick_resume()
tick-sched: initialize 'cpu' while defining it in
tick_nohz_full_setup()
tick-sched: no need to rewrite '1' to tick_nohz_enabled
tick-sched: no need to recheck cpu_online() in can_stop_idle_tick()
tick-sched: invert parameter of tick_check_oneshot_change()
tick-sched: don't check tick_nohz_full_cpu() in
__tick_nohz_task_switch()
tick-sched: don't call local_softirq_pending() thrice in
can_stop_idle_tick()
tick-sched: don't call update_wall_time() when delta is lesser than
tick_period
tick-sched: remove 'regs' parameter of tick_sched_handle()
tick-sched: remove parameters to {__}tick_nohz_task_switch() routines
tick-sched: remove wrapper around __tick_nohz_task_switch()
tick-sched: move nohz_full_buf[] inside tick_nohz_init()
tick-sched: initialize 'ts' during its definition
__tick_nohz_idle_enter()
tick-sched: add comment about 'idle_active' in tick_nohz_idle_exit()
tick-sched: replace tick_nohz_active with tick_nohz_enabled in
tick_nohz_switch_to_nohz()
tick-sched: remove local variable 'now' from tick_setup_sched_timer()
tick-broadcast: do checks before taking locks in
tick_do_broadcast_on_off()
tick-broadcast: get rid of extra comparison in
tick_do_broadcast_on_off()
tick-broadcast: merge tick_do_broadcast_on_off() into
tick_broadcast_on_off()
clockevents: set event_handler to clockevents_handle_noop() in
clockevents_exchange_device()
include/linux/clockchips.h | 2 -
include/linux/hrtimer.h | 3 -
include/linux/tick.h | 65 ++++++++++-------
kernel/hrtimer.c | 4 +-
kernel/sched/core.c | 2 +-
kernel/time/clockevents.c | 11 +--
kernel/time/tick-broadcast.c | 74 +++++++-------------
kernel/time/tick-common.c | 126 +++++++++++++--------------------
kernel/time/tick-internal.h | 15 ++--
kernel/time/tick-oneshot.c | 37 +++++-----
kernel/time/tick-sched.c | 163 +++++++++++++++++++++++--------------------
11 files changed, 232 insertions(+), 270 deletions(-)
--
1.7.12.rc2.18.g61b472e
Hi Thomas,
As suggested by you (https://lkml.org/lkml/2014/4/14/797), this is the first lot
of changes I have. These are all potential bug fixes (Sorry if I haven't read
the most obvious code correctly at some place :) ).
Patch 2/5 isn't a bug fix but was required as a dependency for 3/5.
Some discussions already happened for 5/5 here:
https://lkml.org/lkml/2014/4/9/243https://lkml.org/lkml/2014/4/9/346
I have tried to mark stable release wherever possible.
Viresh Kumar (5):
tick-common: fix wrong check in tick_check_replacement()
tick-common: don't check tick_oneshot_mode_active() from
tick_check_preferred()
tick-common: do additional checks in tick_check_preferred()
tick-sched: don't call update_wall_time() when delta is lesser than
tick_period
tick-sched: replace tick_nohz_active with tick_nohz_enabled in
tick_nohz_switch_to_nohz()
kernel/time/tick-common.c | 29 +++++++++++++++++++----------
kernel/time/tick-sched.c | 34 ++++++++++++++++++----------------
2 files changed, 37 insertions(+), 26 deletions(-)
--
1.7.12.rc2.18.g61b472e
Currently, KVM ARM/ARM64 only provides in-kernel emulation of Power State
and Coordination Interface (PSCI) v0.1.
This patchset aims at providing newer PSCI v0.2 for KVM ARM/ARM64 VCPUs
such that it does not break current KVM ARM/ARM64 ABI.
The user space tools (i.e. QEMU or KVMTOOL) will have to explicitly enable
KVM_ARM_VCPU_PSCI_0_2 feature using KVM_ARM_VCPU_INIT ioctl for providing
PSCI v0.2 to VCPUs.
Changlog:
V9:
- Rename undefined PSCI_VER_xxx defines to PSCI_VERSION_xxx defines
V8:
- Add #define for possible values of migrate type in uapi/linux/psci.h
- Simplified psci_affinity_mask() in psci.c
- Update comments in kvm_psci_vcpu_suspend() to indicate that for KVM
wakeup events are interrupts.
- Unconditionally update r0 (or x0) in kvm_psci_vcpu_on()
V7:
- Make uapi/linux/psci.h inline with Ashwin's patch
http://www.spinics.net/lists/arm-kernel/msg319090.html
- Incorporate Rob's suggestions for uapi/linux/psci.h
- Treat CPU_SUSPEND power-down request to be same as standby
request. This further simplifies CPU_SUSPEND emulation.
V6:
- Introduce uapi/linux/psci.h for sharing PSCI defines between
ARM kernel, ARM64 kernel, KVM ARM/ARM64 and user space
- Make CPU_SUSPEND emulation similar to WFI emulation
V5:
- Have separate last patch to advertise KVM_CAP_ARM_PSCI_0_2
- Use kvm_psci_version() in kvm_psci_vcpu_on()
- Return ALREADY_ON for PSCI v0.2 CPU_ON if VCPU is not paused
- Remove per-VCPU suspend context
- As-per PSCI v0.2 spec, only current CPU can suspend itself
V4:
- Implement all mandatory functions required by PSCI v0.2
V3:
- Make KVM_ARM_VCPU_PSCI_0_2 feature experiementatl for now so that
it fails for user space till all mandatory PSCI v0.2 functions are
emulated by KVM ARM/ARM64
- Have separate patch for making KVM_ARM_VCPU_PSCI_0_2 feature available
to user space. This patch can be defferred for now
V2:
- Don't rename PSCI return values KVM_PSCI_RET_NI and KVM_PSCI_RET_INVAL
- Added kvm_psci_version() to get PSCI version available to VCPU
- Fixed grammer in Documentation/virtual/kvm/api.txt
V1:
- Initial RFC PATCH
Anup Patel (12):
KVM: Add capability to advertise PSCI v0.2 support
ARM/ARM64: KVM: Add common header for PSCI related defines
ARM/ARM64: KVM: Add base for PSCI v0.2 emulation
KVM: Documentation: Add info regarding KVM_ARM_VCPU_PSCI_0_2 feature
ARM/ARM64: KVM: Make kvm_psci_call() return convention more flexible
KVM: Add KVM_EXIT_SYSTEM_EVENT to user space API header
ARM/ARM64: KVM: Emulate PSCI v0.2 SYSTEM_OFF and SYSTEM_RESET
ARM/ARM64: KVM: Emulate PSCI v0.2 AFFINITY_INFO
ARM/ARM64: KVM: Emulate PSCI v0.2 MIGRATE_INFO_TYPE and related
functions
ARM/ARM64: KVM: Fix CPU_ON emulation for PSCI v0.2
ARM/ARM64: KVM: Emulate PSCI v0.2 CPU_SUSPEND
ARM/ARM64: KVM: Advertise KVM_CAP_ARM_PSCI_0_2 to user space
Documentation/virtual/kvm/api.txt | 17 +++
arch/arm/include/asm/kvm_host.h | 2 +-
arch/arm/include/asm/kvm_psci.h | 6 +-
arch/arm/include/uapi/asm/kvm.h | 19 ++--
arch/arm/kvm/arm.c | 1 +
arch/arm/kvm/handle_exit.c | 10 +-
arch/arm/kvm/psci.c | 222 +++++++++++++++++++++++++++++++++----
arch/arm64/include/asm/kvm_host.h | 2 +-
arch/arm64/include/asm/kvm_psci.h | 6 +-
arch/arm64/include/uapi/asm/kvm.h | 21 ++--
arch/arm64/kvm/handle_exit.c | 10 +-
include/uapi/linux/Kbuild | 1 +
include/uapi/linux/kvm.h | 9 ++
include/uapi/linux/psci.h | 78 +++++++++++++
14 files changed, 356 insertions(+), 48 deletions(-)
create mode 100644 include/uapi/linux/psci.h
--
1.7.9.5
sched_can_stop_tick() was using 7 spaces instead of 8 spaces or a 'tab' at the
beginning of each line. Which doesn't align with the Coding Guidelines.
Also it removes the *rq variable as it was used at only one place and hence we
can directly use this_rq() instead.
Signed-off-by: Viresh Kumar <viresh.kumar(a)linaro.org>
---
V1->V2: Rebased over:
https://lkml.org/lkml/2014/3/19/456
kernel/sched/core.c | 20 ++++++++------------
1 file changed, 8 insertions(+), 12 deletions(-)
diff --git a/kernel/sched/core.c b/kernel/sched/core.c
index 1fadf61..3a4bb63 100644
--- a/kernel/sched/core.c
+++ b/kernel/sched/core.c
@@ -666,19 +666,15 @@ static inline bool got_nohz_idle_kick(void)
#ifdef CONFIG_NO_HZ_FULL
bool sched_can_stop_tick(void)
{
- struct rq *rq;
-
- rq = this_rq();
-
- /*
- * More than one running task need preemption.
- * nr_running update is assumed to be visible
- * after IPI is sent from wakers.
- */
- if (rq->nr_running > 1)
- return false;
+ /*
+ * More than one running task need preemption.
+ * nr_running update is assumed to be visible
+ * after IPI is sent from wakers.
+ */
+ if (this_rq()->nr_running > 1)
+ return false;
- return true;
+ return true;
}
#endif /* CONFIG_NO_HZ_FULL */
--
1.7.12.rc2.18.g61b472e
sched_can_stop_tick() was using 7 spaces instead of 8 spaces or a 'tab' at the
beginning of each line. Which doesn't align with the Coding Guidelines.
Also it removes the *rq variable as it was used at only one place and hence we
can directly use this_rq() instead.
Signed-off-by: Viresh Kumar <viresh.kumar(a)linaro.org>
---
I don't think rq = tihs_rq() has to be done before smp_mb(), in case yes sorry
for this patch :(
kernel/sched/core.c | 16 ++++++----------
1 file changed, 6 insertions(+), 10 deletions(-)
diff --git a/kernel/sched/core.c b/kernel/sched/core.c
index 268a45e..13299c5 100644
--- a/kernel/sched/core.c
+++ b/kernel/sched/core.c
@@ -666,18 +666,14 @@ static inline bool got_nohz_idle_kick(void)
#ifdef CONFIG_NO_HZ_FULL
bool sched_can_stop_tick(void)
{
- struct rq *rq;
-
- rq = this_rq();
-
- /* Make sure rq->nr_running update is visible after the IPI */
- smp_rmb();
+ /* Make sure rq->nr_running update is visible after the IPI */
+ smp_rmb();
- /* More than one running task need preemption */
- if (rq->nr_running > 1)
- return false;
+ /* More than one running task need preemption */
+ if (this_rq()->nr_running > 1)
+ return false;
- return true;
+ return true;
}
#endif /* CONFIG_NO_HZ_FULL */
--
1.7.12.rc2.18.g61b472e
Currently, KVM ARM/ARM64 only provides in-kernel emulation of Power State
and Coordination Interface (PSCI) v0.1.
This patchset aims at providing newer PSCI v0.2 for KVM ARM/ARM64 VCPUs
such that it does not break current KVM ARM/ARM64 ABI.
The user space tools (i.e. QEMU or KVMTOOL) will have to explicitly enable
KVM_ARM_VCPU_PSCI_0_2 feature using KVM_ARM_VCPU_INIT ioctl for providing
PSCI v0.2 to VCPUs.
Changlog:
V8:
- Add #define for possible values of migrate type in uapi/linux/psci.h
- Simplified psci_affinity_mask() in psci.c
- Update comments in kvm_psci_vcpu_suspend() to indicate that for KVM
wakeup events are interrupts.
- Unconditionally update r0 (or x0) in kvm_psci_vcpu_on()
V7:
- Make uapi/linux/psci.h inline with Ashwin's patch
http://www.spinics.net/lists/arm-kernel/msg319090.html
- Incorporate Rob's suggestions for uapi/linux/psci.h
- Treat CPU_SUSPEND power-down request to be same as standby
request. This further simplifies CPU_SUSPEND emulation.
V6:
- Introduce uapi/linux/psci.h for sharing PSCI defines between
ARM kernel, ARM64 kernel, KVM ARM/ARM64 and user space
- Make CPU_SUSPEND emulation similar to WFI emulation
V5:
- Have separate last patch to advertise KVM_CAP_ARM_PSCI_0_2
- Use kvm_psci_version() in kvm_psci_vcpu_on()
- Return ALREADY_ON for PSCI v0.2 CPU_ON if VCPU is not paused
- Remove per-VCPU suspend context
- As-per PSCI v0.2 spec, only current CPU can suspend itself
V4:
- Implement all mandatory functions required by PSCI v0.2
V3:
- Make KVM_ARM_VCPU_PSCI_0_2 feature experiementatl for now so that
it fails for user space till all mandatory PSCI v0.2 functions are
emulated by KVM ARM/ARM64
- Have separate patch for making KVM_ARM_VCPU_PSCI_0_2 feature available
to user space. This patch can be defferred for now
V2:
- Don't rename PSCI return values KVM_PSCI_RET_NI and KVM_PSCI_RET_INVAL
- Added kvm_psci_version() to get PSCI version available to VCPU
- Fixed grammer in Documentation/virtual/kvm/api.txt
V1:
- Initial RFC PATCH
Anup Patel (12):
KVM: Add capability to advertise PSCI v0.2 support
ARM/ARM64: KVM: Add common header for PSCI related defines
ARM/ARM64: KVM: Add base for PSCI v0.2 emulation
KVM: Documentation: Add info regarding KVM_ARM_VCPU_PSCI_0_2 feature
ARM/ARM64: KVM: Make kvm_psci_call() return convention more flexible
KVM: Add KVM_EXIT_SYSTEM_EVENT to user space API header
ARM/ARM64: KVM: Emulate PSCI v0.2 SYSTEM_OFF and SYSTEM_RESET
ARM/ARM64: KVM: Emulate PSCI v0.2 AFFINITY_INFO
ARM/ARM64: KVM: Emulate PSCI v0.2 MIGRATE_INFO_TYPE and related
functions
ARM/ARM64: KVM: Fix CPU_ON emulation for PSCI v0.2
ARM/ARM64: KVM: Emulate PSCI v0.2 CPU_SUSPEND
ARM/ARM64: KVM: Advertise KVM_CAP_ARM_PSCI_0_2 to user space
Documentation/virtual/kvm/api.txt | 17 +++
arch/arm/include/asm/kvm_host.h | 2 +-
arch/arm/include/asm/kvm_psci.h | 6 +-
arch/arm/include/uapi/asm/kvm.h | 19 ++--
arch/arm/kvm/arm.c | 1 +
arch/arm/kvm/handle_exit.c | 10 +-
arch/arm/kvm/psci.c | 222 +++++++++++++++++++++++++++++++++----
arch/arm64/include/asm/kvm_host.h | 2 +-
arch/arm64/include/asm/kvm_psci.h | 6 +-
arch/arm64/include/uapi/asm/kvm.h | 21 ++--
arch/arm64/kvm/handle_exit.c | 10 +-
include/uapi/linux/Kbuild | 1 +
include/uapi/linux/kvm.h | 9 ++
include/uapi/linux/psci.h | 77 +++++++++++++
14 files changed, 355 insertions(+), 48 deletions(-)
create mode 100644 include/uapi/linux/psci.h
--
1.7.9.5
Cc: Russ Dill <Russ.Dill(a)ti.com>
Cc: "Rafael J. Wysocki" <rjw(a)rjwysocki.net>
Cc: Russell King <linux(a)arm.linux.org.uk>
Cc: Pavel Machek <pavel(a)ucw.cz>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi(a)arm.com>
Cc: Stephen Warren <swarren(a)nvidia.com>
Cc: Len Brown <len.brown(a)intel.com>
Cc: Nicolas Pitre <nico(a)linaro.org>
Cc: Santosh Shilimkar <santosh.shilimkar(a)ti.com>
Cc: Will Deacon <will.deacon(a)arm.com>
Cc: Jonathan Austin <jonathan.austin(a)arm.com>
Cc: Catalin Marinas <catalin.marinas(a)arm.com>
Cc: "Uwe Kleine-König" <u.kleine-koenig(a)pengutronix.de>
Cc: Stephen Boyd <sboyd(a)codeaurora.org>
Cc: Laura Abbott <lauraa(a)codeaurora.org>
Cc: Jiang Liu <liuj97(a)gmail.com>
Cc: Sricharan R <r.sricharan(a)ti.com>
Cc: Victor Kamensky <victor.kamensky(a)linaro.org>
Cc: Stefano Stabellini <stefano.stabellini(a)eu.citrix.com>
Cc: Ben Dooks <ben.dooks(a)codethink.co.uk>
Cc: Andrew Morton <akpm(a)linux-foundation.org>
Cc: Thomas Gleixner <tglx(a)linutronix.de>
Cc: Robin Holt <robin.m.holt(a)gmail.com>
Cc: Konstantin Khlebnikov <k.khlebnikov(a)samsung.com>
Cc: Steven Capper <steve.capper(a)linaro.org>
Cc: Tejun Heo <tj(a)kernel.org>
Patches adding support for hibernation on ARM
- ARM hibernation / suspend-to-disk
- Change soft_restart to use non-tracing raw_local_irq_disable
Patches based on v3.14-rc7 tag, verified hibernation on beaglebone black on a
branch based on 3.13 merged with initial omap support from Russ Dill which
can be found here (includes v1 patchset):
http://git.linaro.org/git-ro/people/sebastian.capella/linux.git hibernation_3.13_russMerge
[PATCH v9 1/2] ARM: avoid tracers in soft_restart
arch/arm/kernel/process.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Use raw_local_irq_disable in place of local_irq_disable to avoid
infinite abort recursion while tracing. (unchanged since v3)
[PATCH v9 2/2] ARM hibernation / suspend-to-disk
arch/arm/Kconfig | 5 ++
arch/arm/include/asm/memory.h | 1 +
arch/arm/kernel/Makefile | 1 +
arch/arm/kernel/hibernate.c | 107 +++++++++++++++++++++++++++++++++++++++++
include/linux/suspend.h | 2 +
5 files changed, 116 insertions(+)
Adds support for ARM based hibernation
Additional notes:
-----------------
There are two checkpatch warnings added by this patch. These follow
behavior in existing hibernation implementations on other platforms.
WARNING: externs should be avoided in .c files
#131: FILE: arch/arm/kernel/hibernate.c:25:
+extern const void __nosave_begin, __nosave_end;
This extern is picking up the linker nosave region definitions, only
used in hibernate. Follows same extern line used mips, powerpc, s390,
sh, sparc, x86 & unicore32
WARNING: externs should be avoided in .c files
#209: FILE: arch/arm/kernel/hibernate.c:103:
+ extern void call_with_stack(void (*fn)(void *), void *arg, void *sp);
This extern is used in the arch/arm/ in hibernate, process and bL_switcher
Changes in v9:
--------------
* replace pfn calculationwith virt_to_pfn
* automatically allow ARCH_HIBERNATION_POSSIBLE if SUSPEND permitted
* move handling of ARCH config flag to arch/arm/Kconfig
Changes in v8:
--------------
* remove definition and use of __pa_symbol
Changes in v7:
--------------
* remove use of RELOC_HIDE macro
* remove unused #includes
* fixup comment for arch_restore_image
* ensure alignment of resume stack on 8 byte boundary
Changes in v6:
--------------
* Simplify static variable names
Changes in v5:
--------------
* Fixed checkpatch warning on trailing whitespace
Changes in v4:
--------------
* updated comment for soft_restart with review feedback
* dropped freeze_processes patch which was queued separately
to 3.14 by Rafael Wysocki:
https://lkml.org/lkml/2014/2/25/683
Changes in v3:
--------------
* added comment to use of soft_restart
* drop irq disable soft_restart patch
* add patch to avoid tracers in soft_restart by using raw_local_irq_*
Changes in v2:
--------------
* Removed unneeded flush_thread, use of __naked and cpu_init.
* dropped Cyril Chemparathy <cyril(a)ti.com> from Cc: list as
emails are bouncing.
Thanks,
Sebastian Capella
Hi All,
We are trying to run VM which uses mach-virt machine definition. As this machine definition depends totally on DT and we are trying to enable only virtio devices.
Is there a reference device tree which we can use for virtio console, virtio net which is based on mac-virt
Best Regads