Fix e26a9e00afc482b971afcaef1db8c9034d4d6d7c 'ARM: Better
virt_to_page() handling' replaced __pv_phys_offset with
__pv_phys_pfn_offset. Also note that size of __pv_phys_offset
was quad but size of __pv_phys_pfn_offset is word. Instruction
that used to update __pv_phys_offset which address is in r6
had to update low word of __pv_phys_offset so it used #LOW_OFFSET
macro for store offset. Now when size of __pv_phys_pfn_offset is
word, no difference between little endian and big endian should
exist - i.e no offset should be used when __pv_phys_pfn_offset
is stored.
Note that for little endian image proposed change is noop,
since in little endian case #LOW_OFFSET is defined 0 anyway.
Reported-by: Taras Kondratiuk <taras.kondratiuk(a)linaro.org>
Signed-off-by: Victor Kamensky <victor.kamensky(a)linaro.org>
---
arch/arm/kernel/head.S | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index f8c0883..591d6e4 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -587,7 +587,7 @@ __fixup_pv_table:
add r6, r6, r3 @ adjust __pv_phys_pfn_offset address
add r7, r7, r3 @ adjust __pv_offset address
mov r0, r8, lsr #12 @ convert to PFN
- str r0, [r6, #LOW_OFFSET] @ save computed PHYS_OFFSET to __pv_phys_pfn_offset
+ str r0, [r6] @ save computed PHYS_OFFSET to __pv_phys_pfn_offset
strcc ip, [r7, #HIGH_OFFSET] @ save to __pv_offset high bits
mov r6, r3, lsr #24 @ constant for add/sub instructions
teq r3, r6, lsl #24 @ must be 16MiB aligned
--
1.8.1.4
Hi,
As it was discussed on [1] today, here is potential ARM specific
fix for uprobes dcache/icache flush problem. I am aware that
other options are still under discussion. This patch is provided for
reference only as one of possible solutions.
The xol slot flush code shares code with ARM backend of
copy_to_user_page - flush_ptrace_access function. But code and new
implementation of flush_uprobe_xol_access modified in such way that
xol flush does need vma.
Changes since V2 [2] version:
x) address Dave Long's comment about passing checkpatch
x) addressed Oleg's comment and instead of arch_uprobe_flush_xol_access
function use arch_uprobe_copy_ixol function that maps kernel pages,
copies, and flush caches
x) removed FLAG_UA_BROADCAST, during discussion on [1] it was
elaborated that task executing xol single step could be
migrated to another CPU, so we need to take care of remote
icaches if CPU does not support remote snooping. I.e
flush_uprobe_xol_access will check cache_ops_need_broadcast()
and perform smp_call_function on SMP CPUs that do not
support remote snooping.
x) added preempt_disable/preempt_enable in arch_uprobe_copy_ixol as
copy_to_user_page does. I admit that I have some guesses, but I
don't completely understand why copy_to_user_page does that, so
playing on safe side - added it similar to copy_to_user_page code.
Thanks,
Victor
[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2014-April/247611.html
[2] http://lists.infradead.org/pipermail/linux-arm-kernel/2014-April/245743.html
Victor Kamensky (1):
ARM: uprobes need icache flush after xol write
arch/arm/include/asm/cacheflush.h | 2 ++
arch/arm/kernel/uprobes.c | 22 ++++++++++++++++++++++
arch/arm/mm/flush.c | 33 ++++++++++++++++++++++++++++-----
include/linux/uprobes.h | 3 +++
kernel/events/uprobes.c | 25 +++++++++++++++++--------
5 files changed, 72 insertions(+), 13 deletions(-)
--
1.8.1.4
In switch_hrtimer_base() we are calling hrtimer_check_target() which guarantees
this:
/*
* With HIGHRES=y we do not migrate the timer when it is expiring
* before the next event on the target cpu because we cannot reprogram
* the target cpu hardware and we would cause it to fire late.
*
* Called with cpu_base->lock of target cpu held.
*/
But switch_hrtimer_base() is only called from one place, i.e.
__hrtimer_start_range_ns() and at that point (where we call
switch_hrtimer_base()) expiration time is not yet known as we call this routine
later: hrtimer_set_expires_range_ns().
To fix this, we need to find the updated expiry time before calling
switch_hrtimer_base().
Signed-off-by: Viresh Kumar <viresh.kumar(a)linaro.org>
---
Hi Thomas,
I have sent this previously as part of: https://lkml.org/lkml/2014/4/4/23
But as you asked to send bugfixes without any dependencies for ticks patches, I
thought of sending bugfixes separately for timers too. This was the only bugfix
from that series and other patches don't conflict with it, so I am not resending
other patches from above series again.
Not adding any stable tags as this is broken from a long long time and don't
know if you want to fix it for those kernels.
kernel/hrtimer.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/kernel/hrtimer.c b/kernel/hrtimer.c
index d55092c..c86b95a 100644
--- a/kernel/hrtimer.c
+++ b/kernel/hrtimer.c
@@ -968,11 +968,8 @@ int __hrtimer_start_range_ns(struct hrtimer *timer, ktime_t tim,
/* Remove an active timer from the queue: */
ret = remove_hrtimer(timer, base);
- /* Switch the timer base, if necessary: */
- new_base = switch_hrtimer_base(timer, base, mode & HRTIMER_MODE_PINNED);
-
if (mode & HRTIMER_MODE_REL) {
- tim = ktime_add_safe(tim, new_base->get_time());
+ tim = ktime_add_safe(tim, base->get_time());
/*
* CONFIG_TIME_LOW_RES is a temporary way for architectures
* to signal that they simply return xtime in
@@ -987,6 +984,9 @@ int __hrtimer_start_range_ns(struct hrtimer *timer, ktime_t tim,
hrtimer_set_expires_range_ns(timer, tim, delta_ns);
+ /* Switch the timer base, if necessary: */
+ new_base = switch_hrtimer_base(timer, base, mode & HRTIMER_MODE_PINNED);
+
timer_stats_hrtimer_set_start_info(timer);
leftmost = enqueue_hrtimer(timer, new_base);
--
1.7.12.rc2.18.g61b472e
Part of this patchset was previously part of the larger tasks packing patchset
[1]. I have splitted the latter in 3 different patchsets (at least) to make the
thing easier.
-configuration of sched_domain topology [2]
-update and consolidation of cpu_power (this patchset)
-tasks packing algorithm
SMT system is no more the only system that can have a CPUs with capacity that
is different from the default value. We need to extend the use of
cpu_power_orig to all kind of platform so the scheduler will have both the
maximum capacity (cpu_power_orig/power_orig) and the current capacity
(cpu_power/power) of CPUs and groups of the sched_domains.
During load balance, the scheduler evaluates the number of tasks that a group
of CPUs can handle. The current method ensures that we will not return more
capacity than number of real cores but it returns wrong value for group of
LITTLE cores and in some situation for SMT system. The proposed solution
computes the ratio between CPUs and cores for a group durint the init sequence
and uses it with power and power_orig to return the current capacity of a
group.
[1] https://lkml.org/lkml/2013/10/18/121
[2] https://lkml.org/lkml/2014/3/19/377
Vincent Guittot (4):
sched: extend the usage of cpu_power_orig
ARM: topology: use new cpu_power interface
sched: fix computed capacity for HMP
sched: add per group cpu_power_orig
arch/arm/kernel/topology.c | 4 ++--
kernel/sched/core.c | 9 ++++++++-
kernel/sched/fair.c | 31 +++++++++++++++++++------------
kernel/sched/sched.h | 3 ++-
4 files changed, 31 insertions(+), 16 deletions(-)
--
1.9.0
