linaro-kernel January 2014

linaro-kernel@lists.linaro.org

112 participants
241 discussions

by Jon Medhurst

This is a series of fixes for big.LITTLE MP. Patches 1, 2, 3, 6 & 8 are defect fixes. Patches 4 & 5 are to including packing in the TC2 build. Patch 7 is an old patch which accidentally got ommited from LSK. Contents ---------------------------------------------------------------- [PATCH 1/8] sched: reset blocked load decay_count during [PATCH 2/8] sched: update runqueue clock before migrations away [PATCH 3/8] sched: hmp: Make idle balance behaviour normal when [PATCH 4/8] sched: hmp: Change TC2 packing config to disabled [PATCH 5/8] config: Make packing present on TC2 [PATCH 6/8] sched: hmp: Fix potential task_struct memory leak [PATCH 7/8] HMP: Restrict irq_default_affinity to hmp_slow_cpu_mask [PATCH 8/8] HMP: Fix rt task allowed cpu mask restriction code on kernel/irq/irqdesc.c | 8 +++++++ kernel/sched/core.c | 5 ++++- kernel/sched/fair.c | 66 ++++++++++++++++++++++++++++++++++++++++++++++++--------- linaro/configs/big-LITTLE-MP.conf | 1 + 4 files changed, 69 insertions(+), 11 deletions(-)

12 years

Re: [PATCH v6 0/3] AArch64: KGDB support

by Vijay Kilari

On Wed, Jan 22, 2014 at 12:06 AM, Will Deacon <will.deacon(a)arm.com> wrote: > On Tue, Jan 21, 2014 at 02:10:14PM +0000, Vijay Kilari wrote: >> Hi Will, > > Hello Vijay, > >> On Mon, Jan 20, 2014 at 3:53 PM, Will Deacon <will.deacon(a)arm.com> wrote: >> > Well, the warnings are one thing but the 100 miles of backtrace output that >> > appear on every boot (and I think end in an oops) are probably more >> > important to fix. Please enable CONFIG_KGDB_TESTS and >> > CONFIG_KGDB_TESTS_ON_BOOT and take a look. >> > >> >> I could manage to run KGDB boot tests if I run from sysfs after complete boot >> >> echo V1F1000 > /sys/module/kgdbts/parameters/kgdbts >> >> Here the value of PSTATE is 80000145, which means PSTATE.D is unmasked >> hence it works fine. >> >> If I run during boot by enabling CONFIG_KGDB_TESTS_ON_BOOT, >> the step debug test fail because value of PSTATE is 80000345. >> If I force PSTATE.D to 0, it works fine >> >> In debug_monitors.c file, only PSTATE.SS & MDSCR.KDE/MDE is managed >> but not PSTATE.D >> >> Can you please let me know if where PSTATE.D is managed in arm64? > > That's a good point: I think we wait until our first exception before they > are unmasked. Perhaps we should: > > (1) Move local_dbg_{save,restore} from debug-monitors.h into irqflags.h > (2) Add local_dbg_enable/local_dbg_disable macros > (3) Add a call to local_dbg_enable in the clear_os_lock function after the > isb(). > > Does that work for you? Yes, only after first exception occurs the PSTATE.D is unmasked. I have patched (temp) as below and now KGDB boot tests pass diff --git a/arch/arm64/include/asm/debug-monitors.h b/arch/arm64/include/asm/debug-monitors.h index aff3a76..ea2bc46 100644 --- a/arch/arm64/include/asm/debug-monitors.h +++ b/arch/arm64/include/asm/debug-monitors.h @@ -64,6 +111,24 @@ struct task_struct; #define DBG_ARCH_ID_RESERVED 0 /* In case of ptrace ABI updates. */ +#define local_dbg_enable() \ + do { \ + asm volatile( \ + "msr daifclr, #9 // arch_local_irq_disable" \ + : \ + : \ + : "memory"); \ + } while (0) + +#define local_dbg_disable() \ + do { \ + asm volatile( \ + "msr daifset, #9 // arch_local_irq_disable" \ + : \ + : \ + : "memory"); \ + } while (0) + struct step_hook { struct list_head node; int (*fn)(struct pt_regs *regs, unsigned int insn, unsigned long addr); diff --git a/arch/arm64/kernel/debug-monitors.c b/arch/arm64/kernel/debug-monitors.c index f8b90c0..d0e55f7 100644 --- a/arch/arm64/kernel/debug-monitors.c +++ b/arch/arm64/kernel/debug-monitors.c @@ -139,6 +142,7 @@ static void clear_os_lock(void *unused) { asm volatile("msr oslar_el1, %0" : : "r" (0)); isb(); + local_dbg_enable(); } boot test: [32927.161317] msgmni has been set to 1870 [32927.212747] alg: No test for stdrng (krng) [32927.213953] Key type asymmetric registered [32927.214899] Asymmetric key parser 'x509' registered [32927.220029] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 253) [32927.225824] io scheduler noop registered [32927.226764] io scheduler deadline registered [32927.230714] io scheduler cfq registered (default) [32927.237895] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled [32927.266066] kgdb: Registered I/O driver kgdbts. [32927.266419] kgdb: Waiting for connection from remote gdb... [32927.268598] kgdbts:RUN plant and detach test [32927.270683] kgdbts:RUN sw breakpoint test [32927.287659] kgdbts:RUN bad memory access test [32927.290322] kgdbts:RUN singlestep test 1000 iterations [32927.330342] kgdbts:RUN singlestep [0/1000] [32931.286356] kgdbts:RUN singlestep [100/1000] [32935.242536] kgdbts:RUN singlestep [200/1000] [32939.205392] kgdbts:RUN singlestep [300/1000] [32943.169522] kgdbts:RUN singlestep [400/1000] [32947.231868] kgdbts:RUN singlestep [500/1000] [32951.188008] kgdbts:RUN singlestep [600/1000] [32955.332243] kgdbts:RUN singlestep [700/1000] [32959.467109] kgdbts:RUN singlestep [800/1000] [32963.430888] kgdbts:RUN singlestep [900/1000] [32967.346992] kgdbts:RUN do_fork for 100 breakpoints kgdb test using sysfs: ~ # echo V1F1000 > /sys/module/kgdbts/parameters/kgdbts [33231.554237] kgdb: Registered I/O driver kgdbts. [33231.554677] kgdbts:RUN plant and detach test [33231.557072] kgdbts:RUN sw breakpoint test [33231.576980] kgdbts:RUN bad memory access test [33231.580022] kgdbts:RUN singlestep test 1000 iterations [33231.627056] kgdbts:RUN singlestep [0/1000] [33235.954027] kgdbts:RUN singlestep [100/1000] [33240.429086] kgdbts:RUN singlestep [200/1000] [33244.687118] kgdbts:RUN singlestep [300/1000] [33248.945191] kgdbts:RUN singlestep [400/1000] [33253.203751] kgdbts:RUN singlestep [500/1000] [33257.462019] kgdbts:RUN singlestep [600/1000] [33261.817809] kgdbts:RUN singlestep [700/1000] [33266.081268] kgdbts:RUN singlestep [800/1000] [33270.339813] kgdbts:RUN singlestep [900/1000] [33274.712404] kgdbts:RUN do_fork for 1000 breakpoints ~ # This works for me. Should I patch it or will you send a patch for this? PS: cc to mailing list missed > > Will

12 years

[PATCH REPOST 0/5] armv7 BE kvm support

by Victor Kamensky

[repost: adding kvmarm mailing list as per Christoffer's request] Hi Guys, Here is series that enables KVM support for V7 big endian kernels. Mostly it deals with BE KVM host support. Marc Zyngier showed before with his patches how BE guest could run on top LE host. With these patches BE guest runs on top of BE host. If Marc's kvmtool is used with few additional changes I tested that BE host could run LE guest. Also I verified that there were no regressions in BE guest on top of LE host case. Note that posted series covers only kernel side changes. The changes were tested inside of bigger setup with additional changes in qemu and kvmtool. I will post those changes separately in proper aliases but for completeness sake Appendix A gives pointers to git repositories and branches with all needed changes. Please note first patch is not related to BE KVM per se. I've run into an issue of conflicting 'push' identifier use while trying to include assembler.h into KVM .S files. Details of an issue I observed covered in Appendix B. The first patch is my take on solving it. Victor Kamensky (5): ARM: kvm: replace push and pop with stdmb and ldmia instrs to enable assembler.h inclusion ARM: fix KVM assembler files to work in BE case ARM: kvm one_reg coproc set and get BE fixes ARM: kvm vgic mmio should return data in BE format in BE case ARM: kvm MMIO support BE host running LE code arch/arm/include/asm/assembler.h | 7 +++ arch/arm/include/asm/kvm_asm.h | 4 +- arch/arm/include/asm/kvm_emulate.h | 22 +++++++-- arch/arm/kvm/coproc.c | 94 ++++++++++++++++++++++++++++---------- arch/arm/kvm/init.S | 7 ++- arch/arm/kvm/interrupts.S | 50 +++++++++++--------- arch/arm/kvm/interrupts_head.S | 61 +++++++++++++++---------- virt/kvm/arm/vgic.c | 4 +- 8 files changed, 168 insertions(+), 81 deletions(-) -- 1.8.1.4 Thanks, Victor Appendix A: Testing and Full Setup Description ---------------------------------------------- I) No mixed mode setup - i.e BE guest on BE host; and LE guest on LE host tested to make sure no regressions. KVM host and guest kernels: TC2 on top of Linus 3.13-rc4 (this patch series): git: git://git.linaro.org/people/victor.kamensky/linux-linaro-tracking-be.git branch: armv7be-kvm-3.13-rc4 TC2 and Arndale on top of Linaro BE tree: git: git://git.linaro.org/people/victor.kamensky/linux-linaro-tracking-be.git branch: llct-be-20131216-kvm - TC1 kernels used as guests qemu: git: git://git.linaro.org/people/victor.kamensky/qemu-be.git branch: armv7be-v1 description: changes to run qemu on armeb target; and other changes to work with be image on top of be host kvmtool: git: git://git.linaro.org/people/victor.kamensky/linux-linaro-tracking-be.git branch: kvmtool-armv7be-v1 desciption: minimal changes to build kvmtool for armeb target; and tiny change with virtio magic II) Mixed mode setup all possible combinations within V7 (LE guest on BE host; BE guest on LE host as Marc's setup tested to make sure no regressions) only with kvmtool. This work is based on Marc Zyngier's work that made BE guest to run on top of LE host. For this setup special version of kvmtool should be used and in addition I had to apply patch to guest kernel that would switch reading virtio configs reads to be LE only, that is made on top of previous Rusty Russell's changes. Effectively I just had to do very minor addition to make LE guest to work on BE host, most of heavy lifting was done before by Marc. KVM host kernels: as in previous setup Guest TC1 kernels with LE virtio config patch: git: git://git.linaro.org/people/victor.kamensky/linux-linaro-tracking-be.git branch: virtio-leconfig-3.13-rc4 kvmtool: git: git://git.linaro.org/people/victor.kamensky/linux-linaro-tracking-be.git branch: kvmtool-mixed-v1 description: based on git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git branch kvm-arm64/kvmtool-be-on-le; adds missing include fix; above armeb target build patches; and one fix related to BE mode qemu: git: git://git.linaro.org/people/victor.kamensky/qemu-be.git branch: armv7be-leconfig-v1 description: change virtio-blk that so qemu could work with guest image where virtio leconfig is made; note it does not work in mixed mode; to do so qemu would need bunch of similar changes that Marc did in kvmtool Appendix B: kvm asm file and asm/assembler.h file issue ------------------------------------------------------- diff --git a/arch/arm/kvm/interrupts.S b/arch/arm/kvm/interrupts.S index ddc1553..5d3b511 100644 --- a/arch/arm/kvm/interrupts.S +++ b/arch/arm/kvm/interrupts.S @@ -25,6 +25,7 @@ #include <asm/kvm_asm.h> #include <asm/kvm_arm.h> #include <asm/vfpmacros.h> +#include <asm/assembler.h> #include "interrupts_head.S" .text produce the following compilation errors: /run/media/kamensky/wd/linaro/linux-linaro-core-tracking/092913/linux-linaro-tracking-be/arch/arm/kvm/interrupts.S: Assembler messages: /run/media/kamensky/wd/linaro/linux-linaro-core-tracking/092913/linux-linaro-tracking-be/arch/arm/kvm/interrupts.S:51: Error: ARM register expected -- `lsr {r2,r3}' /run/media/kamensky/wd/linaro/linux-linaro-core-tracking/092913/linux-linaro-tracking-be/arch/arm/kvm/interrupts.S:100: Error: ARM register expected -- `lsr {r2}' /run/media/kamensky/wd/linaro/linux-linaro-core-tracking/092913/linux-linaro-tracking-be/arch/arm/kvm/interrupts.S:100: Error: ARM register expected -- `lsr {r4-r12}'

12 years

[PATCH] ARM64: perf: support dwarf unwinding in compat mode

by Jean Pihet

Add support for unwinding using the dwarf information in compat mode. Using the correct user stack pointer allows perf to record the frames correctly in the native and compat modes. Note that although the dwarf frame unwinding works ok using libunwind in native mode (on ARMv7 & ARMv8), some changes are required to the libunwind code for the compat mode. Those changes are posted separately on the libunwind mailing list. Tested on ARMv8 platform with v8 and compat v7 binaries, the latter are statically built. Signed-off-by: Jean Pihet <jean.pihet(a)linaro.org> --- arch/arm64/include/asm/ptrace.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/ptrace.h b/arch/arm64/include/asm/ptrace.h index fbb0020..86d5b54 100644 --- a/arch/arm64/include/asm/ptrace.h +++ b/arch/arm64/include/asm/ptrace.h @@ -133,7 +133,7 @@ struct pt_regs { (!((regs)->pstate & PSR_F_BIT)) #define user_stack_pointer(regs) \ - ((regs)->sp) + (!compat_user_mode(regs)) ? ((regs)->sp) : ((regs)->compat_sp) /* * Are the current registers suitable for user mode? (used to maintain -- 1.7.11.7

12 years

Re: [alsa-devel] [PATCH] ASoC: da9055: Partially fix device

by Opensource [Adam Thomson]

On Wed, 8 Jan 2014 20:38:55 +0000, Mark Brown wrote: > It has never been possible to even load the da9055 driver since both the > MFD and CODEC drivers register the I2C device "da9055". Fix this by using > the usual pattern for MFDs with multiple I2C addresses and having the CODEC > driver reference an I2C dummy registered by the MFD. > Since I don't know which I2C address to use for the CODEC a FIXME has been > left in the MFD, this doesn't make anything any worse since the device has > never been able to load in the first place. What you're saying here is incorrect, as previously discussed at length in this thread: http://mailman.alsa-project.org/pipermail/alsa-devel/2013-September/066027.… The two drivers did work together fine until someone in 3.12 changed the PMIC I2C Id back to just 'da9055' and broke it again. Also, I wanted to add a simple patch to tidy up the I2C Id names and avoid this but you would not agree. The codec part can be standalone and by doing what you've done here means that customers would need to now add additional, unnecessary code to be able to use just the codec driver. This is not right to me.

12 years

[PATCH 1/4] sched: Remove 'cpu' parameter for idle_balance()

by Daniel Lezcano

The cpu parameter passed to idle_balance is not needed as it could be retrieved from the struct rq. Signed-off-by: Daniel Lezcano <daniel.lezcano(a)linaro.org> --- kernel/sched/core.c | 2 +- kernel/sched/fair.c | 3 ++- kernel/sched/sched.h | 2 +- 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/kernel/sched/core.c b/kernel/sched/core.c index 36c951b..cf51601 100644 --- a/kernel/sched/core.c +++ b/kernel/sched/core.c @@ -2680,7 +2680,7 @@ need_resched: pre_schedule(rq, prev); if (unlikely(!rq->nr_running)) - idle_balance(cpu, rq); + idle_balance(rq); put_prev_task(rq, prev); next = pick_next_task(rq); diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c index b24b6cf..d601df3 100644 --- a/kernel/sched/fair.c +++ b/kernel/sched/fair.c @@ -6359,12 +6359,13 @@ out: * idle_balance is called by schedule() if this_cpu is about to become * idle. Attempts to pull tasks from other CPUs. */ -void idle_balance(int this_cpu, struct rq *this_rq) +void idle_balance(struct rq *this_rq) { struct sched_domain *sd; int pulled_task = 0; unsigned long next_balance = jiffies + HZ; u64 curr_cost = 0; + int this_cpu = this_rq->cpu; this_rq->idle_stamp = rq_clock(this_rq); diff --git a/kernel/sched/sched.h b/kernel/sched/sched.h index c2119fd..b0be4c6 100644 --- a/kernel/sched/sched.h +++ b/kernel/sched/sched.h @@ -1176,7 +1176,7 @@ extern const struct sched_class idle_sched_class; extern void update_group_power(struct sched_domain *sd, int cpu); extern void trigger_load_balance(struct rq *rq); -extern void idle_balance(int this_cpu, struct rq *this_rq); +extern void idle_balance(struct rq *this_rq); extern void idle_enter_fair(struct rq *this_rq); extern void idle_exit_fair(struct rq *this_rq); -- 1.7.9.5

12 years

[discussion] simpler load balance in scheduler

by Alex Shi

Paul & Vincent & Morten, The following rough idea get during this KS. I want to have internal review before send to LKML. Would you like to give some comments? ========================== 1, Current scheduler load balance is bottom-up mode, each CPU need initiate the balance by self. Like in a integrate computer system, it has smt/core/cpu/numa, 4 level scheduler domains. If there is just 2 tasks in whole system that both running on cpu0. Current load balance need to pull task to another smt in smt domain, then pull task to another core, then pull task to another cpu, finally pull task to another numa. Totally it is need 4 times task moving to get system balance. Generally, the task moving complexity is O(nm log n), n := nr_cpus, m := nr_tasks PeterZ has a excellent summary and explanation for this in kernel/sched/fair.c:4605 Another weakness of current LB is that every cpu need to get the other cpus' load info repeatedly and try to figure out busiest sched group/queue on every sched domain level. but may not conduct a task moving, one of reasons is that cpu can only pull task, not pushing. 2, Consider huge cost of task moving: CS, tlb/cache refill, and the useless remote cpu load info getting. If we can have better solution for load balance, like reduce the balance times to. O(m) m := nr_tasks It will be a great win on performance. like above example, we can move task from cpu0 direct to another numa. that only need 1 task moving, save 3 CS and tlb/cache refill. To get this point, a rough idea is changing the load balance behaviour to top-down mode. Say let each of cpu report self load status on per-cpu memory. And a baby-sitter in system to collect these cpus load info, then decide how to move task centralize, finally send IPI to each hungry cpu to let them pull load quota from appointed cpus. Like in above example, the baby-sitter will fetch each cpus' load info, then send a pull task IPI to let a cpu in another numa pull one task from cpu0. So in the task pulling, we still just involved 2 cpus, can reuse move_tasks functions. BTW, the baby-sitter can care all kind of balance, regular balance, idle balance, wake up balance. 3, One of concern of top-down mode is that baby-sitter need remote access cpu load info on top domain level every times. But the fact is current load balance also need to get remote cpu load info for top level domain balance. and more worse, such remote accessing maybe useless. -- since there is just one thread reading the info, no competitor writer, Paul, do you think it is worthy concern? BTW, to reduce unnecessary remote info fetching, we can use current idle_cpus_mask in nohz, we just skip the idle cpu in this cpumask simply. 4, From power saving POV, top-down give the whole system cpu topology info directly. So beside the CS reducing, it can reduce the idle cpu interfere by a transition task. and let idle cpu sleep better. -- Thanks Alex

12 years

[PATCH] ASoC: omap: Make RX51 depend on GPIOLIB due to jack usage

by Mark Brown

From: Mark Brown <broonie(a)linaro.org> Since the GPIO jacks are only supported if gpiolib is built and fail to compile otherwise add a build depedency. This is unlikely to have any practical impact outside of coverage testing. Reported-by: Russell King <linux(a)arm.linux.org.uk> Signed-off-by: Mark Brown <broonie(a)linaro.org> --- sound/soc/omap/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/sound/soc/omap/Kconfig b/sound/soc/omap/Kconfig index 4a07f7179690..22ad9c5654b5 100644 --- a/sound/soc/omap/Kconfig +++ b/sound/soc/omap/Kconfig @@ -30,6 +30,7 @@ config SND_OMAP_SOC_RX51 select SND_OMAP_SOC_MCBSP select SND_SOC_TLV320AIC3X select SND_SOC_TPA6130A2 + depends on GPIOLIB help Say Y if you want to add support for SoC audio on Nokia RX-51 hardware. This is also known as Nokia N900 product. -- 1.8.5.2

12 years

[PATCH] ARM: asm: __und_usr_thumb need byteswap instructions in BE case

by Victor Kamensky

__und_usr_thumb function deals with thumb2 opcodes. In case of BE image, it needs to byteswap half word thumb2 encoded instructions before further processing them. Without this fix BE image user-land thread executing first VFP instruction encoded in thumb2 fails with SIGILL, because kernel does not recognize instruction and does not enable VFP. Reported-by: Corey Melton <comelton(a)cisco.com> Signed-off-by: Victor Kamensky <victor.kamensky(a)linaro.org> --- arch/arm/kernel/entry-armv.S | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index b3fb8c9..1879e8d 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S @@ -451,9 +451,11 @@ __und_usr_thumb: .arch armv6t2 #endif 2: ldrht r5, [r4] +ARM_BE8(rev16 r5, r5) @ little endian instruction cmp r5, #0xe800 @ 32bit instruction if xx != 0 blo __und_usr_fault_16 @ 16bit undefined instruction 3: ldrht r0, [r2] +ARM_BE8(rev16 r0, r0) @ little endian instruction add r2, r2, #2 @ r2 is PC + 2, make it PC + 4 str r2, [sp, #S_PC] @ it's a 2x16bit instr, update orr r0, r0, r5, lsl #16 -- 1.8.1.4

12 years

[PATCH 0/3] ACPI: Some patches to prepare for running ACPI on !x86 and !ia64

by Hanjun Guo

Some of the ACPI code is arch-dependent and make the code can't be compiled on !x86 and !ia64, the first two patches just do some rework on the idle_boot_override and _PDC related stuff to make the ACPI code more arch-independent. The third patch just introduce map_gic_id() for ACPI processor core followed by the ACPI 5.0 spec. These three patches are just ACPI related so I send them out as a separate patch set. I have compiled the kernel successful after appling this patch set on x86, ia64 and powerpc(with cross compile tool). Changes since last RFC version: a) Remove the RFC tag; b) Move idle_boot_override out of the arch directory suggested by Alan; c) Make these 3 patches as a separate patch set since there are not not related to the ARM/ARM64 platform. Hanjun Guo (3): ACPI / idle: Move idle_boot_override out of the arch directory ACPI / processor_core: Rework _PDC related stuff to make it more arch-independent ACPI: Introduce map_gic_id() to get apic id from MADT or _MAT method arch/ia64/include/asm/acpi.h | 5 +--- arch/ia64/include/asm/processor.h | 3 --- arch/ia64/kernel/acpi.c | 17 +++++++++++++ arch/powerpc/include/asm/processor.h | 1 - arch/x86/include/asm/acpi.h | 19 +-------------- arch/x86/include/asm/processor.h | 3 --- arch/x86/kernel/acpi/cstate.c | 31 ++++++++++++++++++++++++ arch/x86/kernel/process.c | 1 + drivers/acpi/processor_core.c | 47 +++++++++++++++++++++--------------- include/linux/cpu.h | 8 ++++++ 10 files changed, 87 insertions(+), 48 deletions(-) -- 1.8.2.2

12 years

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linaro-kernel January 2014