Add CFLAGS and LDFLAGS for each feature to be checked during the
build. This allows to pass particular flags and parameters to the
feature checks compilation.
Use the per-feature check flags for the unwinding feature in order
to correctly compile the libunwind and libunwind-debug-frame feature
checks.
This change set simplifies the flags passing mechanism between the
Makefiles in config/Makefile and config/feature-checks; this
could be farther optimized by moving the compilation flags to the
per-feature check flags for all features to be checked.
Tested on x86_64, ARMv7 and ARMv8 with and without LIBUNWIND_DIR
set in 'make -C tools/perf'
Jean Pihet (2):
perf: add per-feature check flags
perf: unwinding: use the per-feature check flags
tools/perf/config/Makefile | 48 +++++++++++++++++--------------
tools/perf/config/feature-checks/Makefile | 8 +++---
2 files changed, 30 insertions(+), 26 deletions(-)
--
1.7.11.7
This patch set is based on part1 "Make ACPI core running on ARM64" patch
set.
After we can get the ACPI tables from UEFI, we can use these tables
to initialise the system now.
GIC (means GIC cpu interface) structure and GIC distributor structure in
MADT table contains the information of GIC cpu interface base address
and GIC distributor base address, which can be used to initialise GIC.
Further more, parked address in GIC structure can be used as cpu release
address for spin table SMP initialisation.
This patch set use these information to init SMP and GIC.
Please refer to chapter 5.2.12.14/15 of ACPI 5.0 spec for GIC and GIC
distributor structure information.
Amit Daniel Kachhap (1):
irqdomain: Add a new API irq_create_acpi_mapping()
Hanjun Guo (8):
ARM64 / ACPI: Implement core functions for parsing MADT table
ARM64 / ACPI: Prefill cpu possible/present maps and map logical cpu
id to APIC id
ARM64 / ACPI: Introduce map_gic_id() to get apic id from MADT or _MAT
method
ARM64 / ACPI: Use Parked Address in GIC structure for spin table SMP
initialisation
ACPI: Define ACPI_IRQ_MODEL_GIC needed for arm
Irqchip / gic: Set as default domain so we can access from ACPI
ACPI / ARM64: Update acpi_register_gsi to register with the core IRQ
subsystem
ACPI / GIC: Initialize GIC using the information in MADT
arch/arm64/include/asm/acpi.h | 16 +-
arch/arm64/kernel/irq.c | 5 +
arch/arm64/kernel/setup.c | 2 +
arch/arm64/kernel/smp.c | 2 +
arch/arm64/kernel/smp_spin_table.c | 16 +-
drivers/acpi/bus.c | 3 +
drivers/acpi/plat/arm-core.c | 397 +++++++++++++++++++++++++++++++++++-
drivers/acpi/processor_core.c | 26 +++
drivers/acpi/tables.c | 21 ++
drivers/irqchip/irq-gic.c | 7 +
include/linux/acpi.h | 9 +
kernel/irq/irqdomain.c | 27 +++
12 files changed, 521 insertions(+), 10 deletions(-)
--
1.7.9.5
From: Mark Brown <broonie(a)linaro.org>
These symbols are only referenced in this source file so can be made
static, and the efficiency table is constant data so can be declared as
such. This avoids polluting the global namespace and fixes warnings
from sparse.
The function arch_scale_freq_power() is still not prototyped or static,
this is a separate issue as this is overriding a weak symbol from the
scheduler which neglects to provide a prototype.
Signed-off-by: Mark Brown <broonie(a)linaro.org>
---
arch/arm/kernel/topology.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/kernel/topology.c b/arch/arm/kernel/topology.c
index 85a87370f144..0bc94b1fd1ae 100644
--- a/arch/arm/kernel/topology.c
+++ b/arch/arm/kernel/topology.c
@@ -68,16 +68,16 @@ struct cpu_efficiency {
* Processors that are not defined in the table,
* use the default SCHED_POWER_SCALE value for cpu_scale.
*/
-struct cpu_efficiency table_efficiency[] = {
+static const struct cpu_efficiency table_efficiency[] = {
{"arm,cortex-a15", 3891},
{"arm,cortex-a7", 2048},
{NULL, },
};
-unsigned long *__cpu_capacity;
+static unsigned long *__cpu_capacity;
#define cpu_capacity(cpu) __cpu_capacity[cpu]
-unsigned long middle_capacity = 1;
+static unsigned long middle_capacity = 1;
/*
* Iterate all CPUs' descriptor in DT and compute the efficiency
@@ -89,7 +89,7 @@ unsigned long middle_capacity = 1;
*/
static void __init parse_dt_topology(void)
{
- struct cpu_efficiency *cpu_eff;
+ const struct cpu_efficiency *cpu_eff;
struct device_node *cn = NULL;
unsigned long min_capacity = (unsigned long)(-1);
unsigned long max_capacity = 0;
@@ -158,7 +158,7 @@ static void __init parse_dt_topology(void)
* boot. The update of all CPUs is in O(n^2) for heteregeneous system but the
* function returns directly for SMP system.
*/
-void update_cpu_power(unsigned int cpu)
+static void update_cpu_power(unsigned int cpu)
{
if (!cpu_capacity(cpu))
return;
@@ -185,7 +185,7 @@ const struct cpumask *cpu_coregroup_mask(int cpu)
return &cpu_topology[cpu].core_sibling;
}
-void update_siblings_masks(unsigned int cpuid)
+static void update_siblings_masks(unsigned int cpuid)
{
struct cputopo_arm *cpu_topo, *cpuid_topo = &cpu_topology[cpuid];
int cpu;
--
1.8.5.1
This is the last part of patch set for core of ARM64 ACPI, and is based
on the patch set part2 "Using ACPI MADT table to initialise SMP and GIC".
ACPI GTDT (Generic Timer Description Table) is used for ARM/ARM64 only,
and contains the information for arch timer initialisation.
This patch trys to convert the arch timer to ACPI using GTDT.
After this patch set was posted, we already finished the SMP, GIC and
arch timer initialisation, which all are essential for ARM64 core system
running, then we will focus on converting the device drivers to ACPI.
Here is the GTDT ASL code I used:
---
platforms/foundation-v8.acpi/gtdt.asl | 35 ++++++++++++++++++++++-----------
1 file changed, 23 insertions(+), 12 deletions(-)
diff --git a/platforms/foundation-v8.acpi/gtdt.asl b/platforms/foundation-v8.acpi/gtdt.asl
index 18c821a..714d61c 100644
--- a/platforms/foundation-v8.acpi/gtdt.asl
+++ b/platforms/foundation-v8.acpi/gtdt.asl
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2013, Al Stone <al.stone(a)linaro.org>
+ * Hanjun Guo <hanjun.guo(a)linaro.org>
*
* [GTDT] Generic Timer Description Table
* Format: [ByteLength] FieldName : HexFieldValue
@@ -21,22 +22,32 @@
[0004] Flags (decoded below) : 00000001
Memory Present : 1
-[0004] Secure PL1 Interrupt : 00000000
-[0004] SPL1 Flags (decoded below) : 00000000
- Trigger Mode : 0
+/* In Foundation model's dts file, the last cell of interrupts
+ * is 0xff01, it means its cpu mask is FF, and trigger type
+ * and flag is 1 = low-to-high edge triggered.
+ *
+ * so in ACPI the Trigger Mode is 1 - Edge triggered, and
+ * Polarity is 0 - Active high as ACPI spec describled.
+ *
+ * using direct mapping for hwirqs, it means that we using
+ * ID [16, 31] for PPI, not [0, 15] used in FDT.
+ */
+[0004] Secure PL1 Interrupt : 0000001d
+[0004] SPL1 Flags (decoded below) : 00000001
+ Trigger Mode : 1
Polarity : 0
-[0004] Non-Secure PL1 Interrupt : 00000000
-[0004] NSPL1 Flags (decoded below) : 00000000
- Trigger Mode : 0
+[0004] Non-Secure PL1 Interrupt : 0000001e
+[0004] NSPL1 Flags (decoded below) : 00000001
+ Trigger Mode : 1
Polarity : 0
-[0004] Virtual Timer Interrupt : 00000000
-[0004] VT Flags (decoded below) : 00000000
- Trigger Mode : 0
+[0004] Virtual Timer Interrupt : 0000001b
+[0004] VT Flags (decoded below) : 00000001
+ Trigger Mode : 1
Polarity : 0
-[0004] Non-Secure PL2 Interrupt : 00000000
-[0004] NSPL2 Flags (decoded below) : 00000000
- Trigger Mode : 0
+[0004] Non-Secure PL2 Interrupt : 0000001a
+[0004] NSPL2 Flags (decoded below) : 00000001
+ Trigger Mode : 1
Polarity : 0
Hanjun Guo (2):
clocksource / arch_timer: Use ACPI GTDT table to initialize arch
timer
ARM64 / clocksource: Use arch_timer_acpi_init()
arch/arm64/kernel/time.c | 4 ++
drivers/clocksource/arm_arch_timer.c | 129 ++++++++++++++++++++++++++++++----
include/clocksource/arm_arch_timer.h | 7 +-
3 files changed, 124 insertions(+), 16 deletions(-)
--
1.7.9.5
