[PATCH 0/7] RFC: convert OMAP to common struct clk

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Mike Turquette

14 Dec 2011 14 Dec '11

4:11 a.m.

This patch series is an RFC for converting OMAP to the common struct clk. These patches are based on v4 of the common struct clk series: https://lkml.org/lkml/2011/12/13/451

OMAP's old struct clk has been renamed to struct clk_hw_omap, but left essentially the same. This series only targets OMAP4 and was only tested on a 4430 Panda.

The next step is to figure out: * what are the various clk types we want to support in separate structures * where does the "clk driver" code live (still in mach-omap2?) * kill off plat-omap/clock.* completely? I vote yes.

These patches can also be found at, http://git.linaro.org/gitweb?p=people/mturquette/linux.git%3Ba=shortlog%3Bh=...

The same series merged with Kevin's PM branch (to get CPUfreq working) can be found at, http://git.linaro.org/gitweb?p=people/mturquette/linux.git%3Ba=shortlog%3Bh=...

This series will be followed up shortly with another set of patches for "testing" the clk rate change notifiers, parent propagation of rate changes and debugfs re-parenting.

Mike Turquette (7): OMAP: Kconfig: select GENERIC_CLK HACK: omap4: clk: convert to common struct clk HACK: omap: convert 44xx data to common struct clk omap: hwmod: convert to use common struct clk omap: panda: use clk_prepare in ehci init omap: dss: use clk_prepare in dss reset HACK: comment WARN_ON in _clkdm_clk_hwmod_disable

-- 1.7.5.4

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Mike Turquette

14 Dec 14 Dec

4:11 a.m.

New subject: [PATCH 1/7] OMAP: Kconfig: select GENERIC_CLK

From: Mike Turquette mturquette@linaro.org

Signed-off-by: Mike Turquette mturquette@ti.com --- arch/arm/mach-omap2/Kconfig | 1 + 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index e1293aa..921451c 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -17,6 +17,7 @@ config ARCH_OMAP2PLUS_TYPICAL select MENELAUS if ARCH_OMAP2 select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4 select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4 + select GENERIC_CLK help Compile a kernel suitable for booting most boards

-- 1.7.5.4

Mike Turquette

4:11 a.m.

New subject: [PATCH 2/7] HACK: omap4: clk: convert to common struct clk

This is a pile of code to convert the OMAP4 clk framework over to the common struct clk definition and it's supporting functions.

Note that this only works for OMAP4, and I have only tested it on Panda. This patch is only for testing purposes and to kick off discussion of how we want to reshape the OMAP clk framework for the new way of doing things.

Again... this patch was done in a hurry to get things booting, so try not to nitpick the gross stuff. It's more important to focus on what future data structures and the layout of the OMAP clk code will look like.

Not-signed-off-by: Mike Turquette mturquette@ti.com --- arch/arm/mach-omap2/clkt_clksel.c | 195 +++++++++-------- arch/arm/mach-omap2/clkt_dpll.c | 54 +++-- arch/arm/mach-omap2/clock.c | 363 +++++++++++-------------------- arch/arm/mach-omap2/clock.h | 59 +++-- arch/arm/mach-omap2/dpll3xxx.c | 228 +++++++++++--------- arch/arm/mach-omap2/dpll44xx.c | 62 ++++-- arch/arm/plat-omap/clock.c | 315 +++++++++----------------- arch/arm/plat-omap/include/plat/clock.h | 96 +++----- 8 files changed, 618 insertions(+), 754 deletions(-)

diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c index e25364d..ad3befb 100644 --- a/arch/arm/mach-omap2/clkt_clksel.c +++ b/arch/arm/mach-omap2/clkt_clksel.c @@ -1,12 +1,13 @@ /* * clkt_clksel.c - OMAP2/3/4 clksel clock functions * - * Copyright (C) 2005-2008 Texas Instruments, Inc. + * Copyright (C) 2005-2011 Texas Instruments, Inc. * Copyright (C) 2004-2010 Nokia Corporation * * Contacts: * Richard Woodruff r-woodruff2@ti.com * Paul Walmsley + * Mike Turquette mturquette@ti.com * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -43,6 +44,7 @@ #include <linux/errno.h> #include <linux/clk.h> #include <linux/io.h> +#include <linux/err.h>

#include <plat/clock.h>

@@ -59,19 +61,19 @@ * the element associated with the supplied parent clock address. * Returns a pointer to the struct clksel on success or NULL on error. */ -static const struct clksel *_get_clksel_by_parent(struct clk *clk, +static const struct clksel *_get_clksel_by_parent(struct clk_hw_omap *oclk, struct clk *src_clk) { const struct clksel *clks;

- for (clks = clk->clksel; clks->parent; clks++) + for (clks = oclk->clksel; clks->parent; clks++) if (clks->parent == src_clk) break; /* Found the requested parent */

if (!clks->parent) { /* This indicates a data problem */ WARN(1, "clock: Could not find parent clock %s in clksel array " - "of clock %s\n", src_clk->name, clk->name); + "of clock %s\n", src_clk->name, oclk->clk.name); return NULL; }

@@ -93,14 +95,14 @@ static const struct clksel *_get_clksel_by_parent(struct clk *clk, * success (in this latter case, the corresponding register bitfield * value is passed back in the variable pointed to by @field_val) */ -static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk, +static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk_hw_omap *oclk, u32 *field_val) { const struct clksel *clks; const struct clksel_rate *clkr, *max_clkr = NULL; u8 max_div = 0;

- clks = _get_clksel_by_parent(clk, src_clk); + clks = _get_clksel_by_parent(oclk, src_clk); if (!clks) return 0;

@@ -126,7 +128,7 @@ static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk, if (max_div == 0) { /* This indicates an error in the clksel data */ WARN(1, "clock: Could not find divisor for clock %s parent %s" - "\n", clk->name, src_clk->parent->name); + "\n", oclk->clk.name, src_clk->parent->name); return 0; }

@@ -148,16 +150,16 @@ static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk, * take into account any time the hardware might take to switch the * clock source. */ -static void _write_clksel_reg(struct clk *clk, u32 field_val) +static void _write_clksel_reg(struct clk_hw_omap *oclk, u32 field_val) { u32 v;

- v = __raw_readl(clk->clksel_reg); - v &= ~clk->clksel_mask; - v |= field_val << __ffs(clk->clksel_mask); - __raw_writel(v, clk->clksel_reg); + v = __raw_readl(oclk->clksel_reg); + v &= ~oclk->clksel_mask; + v |= field_val << __ffs(oclk->clksel_mask); + __raw_writel(v, oclk->clksel_reg);

- v = __raw_readl(clk->clksel_reg); /* OCP barrier */ + v = __raw_readl(oclk->clksel_reg); /* OCP barrier */ }

/** @@ -171,12 +173,12 @@ static void _write_clksel_reg(struct clk *clk, u32 field_val) * before calling. Returns 0 on error or returns the actual integer divisor * upon success. */ -static u32 _clksel_to_divisor(struct clk *clk, u32 field_val) +static u32 _clksel_to_divisor(struct clk_hw_omap *oclk, u32 field_val) { const struct clksel *clks; const struct clksel_rate *clkr;

- clks = _get_clksel_by_parent(clk, clk->parent); + clks = _get_clksel_by_parent(oclk, oclk->clk.parent); if (!clks) return 0;

@@ -190,8 +192,9 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val)

if (!clkr->div) { /* This indicates a data error */ - WARN(1, "clock: Could not find fieldval %d for clock %s parent " - "%s\n", field_val, clk->name, clk->parent->name); + WARN(1, "%s: Could not find fieldval %d for clock %s parent %s\n", + __func__, field_val, oclk->clk.name, + oclk->clk.parent->name); return 0; }

@@ -208,7 +211,7 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val) * register field value _before_ left-shifting (i.e., LSB is at bit * 0); or returns 0xFFFFFFFF (~0) upon error. */ -static u32 _divisor_to_clksel(struct clk *clk, u32 div) +static u32 _divisor_to_clksel(struct clk_hw_omap *oclk, u32 div) { const struct clksel *clks; const struct clksel_rate *clkr; @@ -216,7 +219,7 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div) /* should never happen */ WARN_ON(div == 0);

- clks = _get_clksel_by_parent(clk, clk->parent); + clks = _get_clksel_by_parent(oclk, oclk->clk.parent); if (!clks) return ~0;

@@ -229,8 +232,8 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div) }

if (!clkr->div) { - pr_err("clock: Could not find divisor %d for clock %s parent " - "%s\n", div, clk->name, clk->parent->name); + pr_err("%s: Could not find divisor %d for clock %s parent %s\n", + __func__, div, oclk->clk.name, oclk->clk.parent->name); return ~0; }

@@ -245,18 +248,18 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div) * into the hardware, convert it into the actual divisor value, and * return it; or return 0 on error. */ -static u32 _read_divisor(struct clk *clk) +static u32 _read_divisor(struct clk_hw_omap *oclk) { u32 v;

- if (!clk->clksel || !clk->clksel_mask) + if (!oclk->clksel || !oclk->clksel_mask) return 0;

- v = __raw_readl(clk->clksel_reg); - v &= clk->clksel_mask; - v >>= __ffs(clk->clksel_mask); + v = __raw_readl(oclk->clksel_reg); + v &= oclk->clksel_mask; + v >>= __ffs(oclk->clksel_mask);

- return _clksel_to_divisor(clk, v); + return _clksel_to_divisor(oclk, v); }

/* Public functions */ @@ -273,23 +276,26 @@ static u32 _read_divisor(struct clk *clk) * * Returns the rounded clock rate or returns 0xffffffff on error. */ -u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, - u32 *new_div) +u32 omap2_clksel_round_rate_div(struct clk_hw_omap *oclk, + unsigned long target_rate, u32 *new_div) { unsigned long test_rate; const struct clksel *clks; const struct clksel_rate *clkr; + struct clk *parent; u32 last_div = 0;

- if (!clk->clksel || !clk->clksel_mask) + parent = oclk->clk.parent; + + if (!oclk->clksel || !oclk->clksel_mask) return ~0;

- pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n", - clk->name, target_rate); + pr_debug("%s: clksel_round_rate_div: %s target_rate %ld\n", + __func__, oclk->clk.name, target_rate);

*new_div = 1;

- clks = _get_clksel_by_parent(clk, clk->parent); + clks = _get_clksel_by_parent(oclk, parent); if (!clks) return ~0;

@@ -299,30 +305,30 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,

/* Sanity check */ if (clkr->div <= last_div) - pr_err("clock: clksel_rate table not sorted " - "for clock %s", clk->name); + pr_err("%s: clksel_rate table not sorted for clock %s", + __func__, oclk->clk.name);

last_div = clkr->div;

- test_rate = clk->parent->rate / clkr->div; + test_rate = parent->rate / clkr->div;

if (test_rate <= target_rate) break; /* found it */ }

if (!clkr->div) { - pr_err("clock: Could not find divisor for target " - "rate %ld for clock %s parent %s\n", target_rate, - clk->name, clk->parent->name); + pr_err("%s: Could not find divisor for target rate %ld for clock %s parent %s\n", + __func__, target_rate, oclk->clk.name, + parent->name); return ~0; }

*new_div = clkr->div;

pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div, - (clk->parent->rate / clkr->div)); + (parent->rate / clkr->div));

- return clk->parent->rate / clkr->div; + return parent->rate / clkr->div; }

/* @@ -339,42 +345,45 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, * to. Update @clk's .parent field with the appropriate clk ptr. No * return value. */ -void omap2_init_clksel_parent(struct clk *clk) +struct clk *omap2_init_clksel_parent(struct clk *clk) { + struct clk_hw_omap *oclk; const struct clksel *clks; const struct clksel_rate *clkr; - u32 r, found = 0; + u32 r; + + oclk = to_clk_hw_omap(clk);

- if (!clk->clksel || !clk->clksel_mask) - return; + if (!oclk->clksel || !oclk->clksel_mask) + return ERR_PTR(-EINVAL);

- r = __raw_readl(clk->clksel_reg) & clk->clksel_mask; - r >>= __ffs(clk->clksel_mask); + r = __raw_readl(oclk->clksel_reg) & oclk->clksel_mask; + r >>= __ffs(oclk->clksel_mask);

- for (clks = clk->clksel; clks->parent && !found; clks++) { - for (clkr = clks->rates; clkr->div && !found; clkr++) { + for (clks = oclk->clksel; clks->parent; clks++) { + for (clkr = clks->rates; clkr->div; clkr++) { if (!(clkr->flags & cpu_mask)) continue;

if (clkr->val == r) { - if (clk->parent != clks->parent) { - pr_debug("clock: inited %s parent " - "to %s (was %s)\n", - clk->name, clks->parent->name, - ((clk->parent) ? - clk->parent->name : "NULL")); - clk_reparent(clk, clks->parent); + if (oclk->clk.parent != clks->parent) { + pr_debug("clock: inited %s parent to %s (was %s)\n", + oclk->clk.name, + clks->parent->name, + ((oclk->clk.parent) ? + oclk->clk.parent->name : + "NULL")); }; - found = 1; + return clks->parent; } } }

/* This indicates a data error */ - WARN(!found, "clock: %s: init parent: could not find regval %0x\n", - clk->name, r); + WARN(1, "clock: %s: init parent: could not find regval %0x\n", + oclk->clk.name, r);

- return; + return ERR_PTR(-ENODEV); }

/** @@ -388,17 +397,21 @@ void omap2_init_clksel_parent(struct clk *clk) */ unsigned long omap2_clksel_recalc(struct clk *clk) { + struct clk_hw_omap *oclk; unsigned long rate; u32 div = 0;

- div = _read_divisor(clk); - if (div == 0) - return clk->rate; + oclk = to_clk_hw_omap(clk); + + div = _read_divisor(oclk);

- rate = clk->parent->rate / div; + if (!div) + rate = oclk->clk.parent->rate; + else + rate = oclk->clk.parent->rate / div;

- pr_debug("clock: %s: recalc'd rate is %ld (div %d)\n", clk->name, - rate, div); + pr_debug("%s: recalc'd %s's rate to %lu (div %d)\n", __func__, + oclk->clk.name, rate, div);

return rate; } @@ -414,11 +427,15 @@ unsigned long omap2_clksel_recalc(struct clk *clk) * * Returns the rounded clock rate or returns 0xffffffff on error. */ -long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate) +long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate, + unsigned long *parent_rate) { + struct clk_hw_omap *oclk; u32 new_div;

- return omap2_clksel_round_rate_div(clk, target_rate, &new_div); + oclk = to_clk_hw_omap(clk); + + return omap2_clksel_round_rate_div(oclk, target_rate, &new_div); }

/** @@ -438,24 +455,31 @@ long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate) */ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) { + struct clk_hw_omap *oclk; u32 field_val, validrate, new_div = 0;

- if (!clk->clksel || !clk->clksel_mask) + if (clk->rate == rate) + return 0; + + oclk = to_clk_hw_omap(clk); + + if (!oclk->clksel || !oclk->clksel_mask) return -EINVAL;

- validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); + validrate = omap2_clksel_round_rate_div(oclk, rate, &new_div); if (validrate != rate) return -EINVAL;

- field_val = _divisor_to_clksel(clk, new_div); + field_val = _divisor_to_clksel(oclk, new_div); if (field_val == ~0) return -EINVAL;

- _write_clksel_reg(clk, field_val); - - clk->rate = clk->parent->rate / new_div; + _write_clksel_reg(oclk, field_val);

- pr_debug("clock: %s: set rate to %ld\n", clk->name, clk->rate); + pr_debug("%s: parent->rate is %lu, new_div is %lu, new rate is %lu\n", + __func__, oclk->clk.parent->rate, + (unsigned long) new_div, + (oclk->clk.parent->rate / new_div));

return 0; } @@ -482,28 +506,23 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) */ int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent) { + struct clk_hw_omap *oclk; u32 field_val = 0; u32 parent_div;

- if (!clk->clksel || !clk->clksel_mask) + oclk = to_clk_hw_omap(clk); + + if (!oclk->clksel || !oclk->clksel_mask) return -EINVAL;

- parent_div = _get_div_and_fieldval(new_parent, clk, &field_val); + parent_div = _get_div_and_fieldval(new_parent, oclk, &field_val); if (!parent_div) return -EINVAL;

- _write_clksel_reg(clk, field_val); - - clk_reparent(clk, new_parent); - - /* CLKSEL clocks follow their parents' rates, divided by a divisor */ - clk->rate = new_parent->rate; - - if (parent_div > 0) - clk->rate /= parent_div; + _write_clksel_reg(oclk, field_val);

- pr_debug("clock: %s: set parent to %s (new rate %ld)\n", - clk->name, clk->parent->name, clk->rate); + pr_debug("%s: re-parented %s to %s (new rate %lu)\n", __func__, + oclk->clk.name, oclk->clk.parent->name, oclk->clk.rate);

return 0; } diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c index e069a9b..929e9d7 100644 --- a/arch/arm/mach-omap2/clkt_dpll.c +++ b/arch/arm/mach-omap2/clkt_dpll.c @@ -1,12 +1,13 @@ /* * OMAP2/3/4 DPLL clock functions * - * Copyright (C) 2005-2008 Texas Instruments, Inc. + * Copyright (C) 2005-2011 Texas Instruments, Inc. * Copyright (C) 2004-2010 Nokia Corporation * * Contacts: * Richard Woodruff r-woodruff2@ti.com * Paul Walmsley + * Mike Turquette mturquette@ti.com * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -16,6 +17,7 @@

#include <linux/kernel.h> #include <linux/errno.h> +#include <linux/err.h> #include <linux/clk.h> #include <linux/io.h>

@@ -77,16 +79,16 @@ * (assuming that it is counting N upwards), or -2 if the enclosing loop * should skip to the next iteration (again assuming N is increasing). */ -static int _dpll_test_fint(struct clk *clk, u8 n) +static int _dpll_test_fint(struct clk_hw_omap *oclk, u8 n) { struct dpll_data *dd; long fint, fint_min, fint_max; int ret = 0;

- dd = clk->dpll_data; + dd = oclk->dpll_data;

/* DPLL divider must result in a valid jitter correction val */ - fint = clk->parent->rate / n; + fint = oclk->clk.parent->rate / n;

if (cpu_is_omap24xx()) { /* Should not be called for OMAP2, so warn if it is called */ @@ -188,14 +190,17 @@ static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,

/* Public functions */

-void omap2_init_dpll_parent(struct clk *clk) +struct clk *omap2_init_dpll_parent(struct clk *clk) { u32 v; struct dpll_data *dd; + struct clk_hw_omap *oclk;

- dd = clk->dpll_data; + oclk = to_clk_hw_omap(clk); + + dd = oclk->dpll_data; if (!dd) - return; + return ERR_PTR(-EINVAL);

v = __raw_readl(dd->control_reg); v &= dd->enable_mask; @@ -205,18 +210,18 @@ void omap2_init_dpll_parent(struct clk *clk) if (cpu_is_omap24xx()) { if (v == OMAP2XXX_EN_DPLL_LPBYPASS || v == OMAP2XXX_EN_DPLL_FRBYPASS) - clk_reparent(clk, dd->clk_bypass); + return dd->clk_bypass; } else if (cpu_is_omap34xx()) { if (v == OMAP3XXX_EN_DPLL_LPBYPASS || v == OMAP3XXX_EN_DPLL_FRBYPASS) - clk_reparent(clk, dd->clk_bypass); + return dd->clk_bypass; } else if (cpu_is_omap44xx()) { if (v == OMAP4XXX_EN_DPLL_LPBYPASS || v == OMAP4XXX_EN_DPLL_FRBYPASS || v == OMAP4XXX_EN_DPLL_MNBYPASS) - clk_reparent(clk, dd->clk_bypass); + return dd->clk_bypass; } - return; + return dd->clk_ref; }

/** @@ -233,13 +238,13 @@ void omap2_init_dpll_parent(struct clk *clk) * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0 * if the clock @clk is not a DPLL. */ -u32 omap2_get_dpll_rate(struct clk *clk) +unsigned long omap2_get_dpll_rate(struct clk_hw_omap *oclk) { long long dpll_clk; u32 dpll_mult, dpll_div, v; struct dpll_data *dd;

- dd = clk->dpll_data; + dd = oclk->dpll_data; if (!dd) return 0;

@@ -289,20 +294,24 @@ u32 omap2_get_dpll_rate(struct clk *clk) * (expensive) function again. Returns ~0 if the target rate cannot * be rounded, or the rounded rate upon success. */ -long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) +long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate, + unsigned long *parent_rate) { int m, n, r, scaled_max_m; unsigned long scaled_rt_rp; unsigned long new_rate = 0; struct dpll_data *dd; + struct clk_hw_omap *oclk; + + oclk = to_clk_hw_omap(clk);

- if (!clk || !clk->dpll_data) + if (!oclk->dpll_data) return ~0;

- dd = clk->dpll_data; + dd = oclk->dpll_data;

- pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n", - clk->name, target_rate); + pr_debug("%s: starting DPLL round_rate for %s, target rate %ld\n", + __func__, oclk->clk.name, target_rate);

scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR); scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR; @@ -312,7 +321,7 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) for (n = dd->min_divider; n <= dd->max_divider; n++) {

/* Is the (input clk, divider) pair valid for the DPLL? */ - r = _dpll_test_fint(clk, n); + r = _dpll_test_fint(oclk, n); if (r == DPLL_FINT_UNDERFLOW) break; else if (r == DPLL_FINT_INVALID) @@ -338,7 +347,7 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) continue;

pr_debug("clock: %s: m = %d: n = %d: new_rate = %ld\n", - clk->name, m, n, new_rate); + oclk->clk.name, m, n, new_rate);

if (target_rate == new_rate) { dd->last_rounded_m = m; @@ -349,11 +358,10 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) }

if (target_rate != new_rate) { - pr_debug("clock: %s: cannot round to rate %ld\n", clk->name, - target_rate); + pr_debug("%s: cannot round %s's rate to %ld\n", __func__, + oclk->clk.name, target_rate); return ~0; }

return target_rate; } - diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 1f3481f..24fd97e 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -37,6 +37,19 @@

u8 cpu_mask;

+struct clk_hw_ops dummy_ck_ops = { + .get_parent = &omap2_get_parent_fixed, +}; + +struct clk_hw_omap dummy_ck_hw = { + .clk = { + .name = "dummy_clk", + .ops = &dummy_ck_ops, + }, +}; + +//struct clk *dummy_ck = &dummy_ck_hw.clk; + /* * clkdm_control: if true, then when a clock is enabled in the * hardware, its clockdomain will first be enabled; and when a clock @@ -61,22 +74,22 @@ static bool clkdm_control = true; * belong in the clock code and will be moved in the medium term to * module-dependent code. No return value. */ -static void _omap2_module_wait_ready(struct clk *clk) +static void _omap2_module_wait_ready(struct clk_hw_omap *oclk) { void __iomem *companion_reg, *idlest_reg; u8 other_bit, idlest_bit, idlest_val;

/* Not all modules have multiple clocks that their IDLEST depends on */ - if (clk->ops->find_companion) { - clk->ops->find_companion(clk, &companion_reg, &other_bit); + if (oclk->find_companion) { + oclk->find_companion(oclk, &companion_reg, &other_bit); if (!(__raw_readl(companion_reg) & (1 << other_bit))) return; }

- clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val); + oclk->find_idlest(oclk, &idlest_reg, &idlest_bit, &idlest_val);

omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), idlest_val, - clk->name); + oclk->clk.name); }

/* Public functions */ @@ -89,21 +102,27 @@ static void _omap2_module_wait_ready(struct clk *clk) * clockdomain pointer, and save it into the struct clk. Intended to be * called during clk_register(). No return value. */ +/* FIXME should this get folded into clk-specific "clk_hw_init"? */ void omap2_init_clk_clkdm(struct clk *clk) { + struct clk_hw_omap *oclk; struct clockdomain *clkdm;

- if (!clk->clkdm_name) + oclk = to_clk_hw_omap(clk); + + //pr_err("%s: %s is here0\n", __func__, clk->name); + if (!oclk->clkdm_name) return; + //pr_err("%s: %s is here1, oclk->clkdm_name is %s\n", __func__, clk->name, oclk->clkdm_name);

- clkdm = clkdm_lookup(clk->clkdm_name); + clkdm = clkdm_lookup(oclk->clkdm_name); if (clkdm) { - pr_debug("clock: associated clk %s to clkdm %s\n", - clk->name, clk->clkdm_name); - clk->clkdm = clkdm; + pr_debug("%s: associated clk %s to clkdm %s\n", + __func__, clk->name, oclk->clkdm_name); + oclk->clkdm = clkdm; } else { - pr_debug("clock: could not associate clk %s to " - "clkdm %s\n", clk->name, clk->clkdm_name); + pr_debug("%s: could not associate clk %s to clkdm %s\n", + __func__, clk->name, oclk->clkdm_name); } }

@@ -141,8 +160,14 @@ void __init omap2_clk_disable_clkdm_control(void) * associate this type of code with per-module data structures to * avoid this issue, and remove the casts. No return value. */ -void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, - u8 *other_bit) +/* + * FIXME should "internal" functions like this be renamed to + * __omap2_clk_dflt_find_companion, and also accept struct clk_hw_omap instead + * struct clk? Makes sense to me since this function pointer is *in* struct + * clk_hw_omap anyways... + */ +void omap2_clk_dflt_find_companion(struct clk_hw_omap *oclk, void __iomem **other_reg, + u8 *other_bit) { u32 r;

@@ -150,10 +175,10 @@ void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes * it's just a matter of XORing the bits. */ - r = ((__force u32)clk->enable_reg ^ (CM_FCLKEN ^ CM_ICLKEN)); + r = ((__force u32)oclk->enable_reg ^ (CM_FCLKEN ^ CM_ICLKEN));

*other_reg = (__force void __iomem *)r; - *other_bit = clk->enable_bit; + *other_bit = oclk->enable_bit; }

/** @@ -170,14 +195,14 @@ void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, * register address ID (e.g., that CM_FCLKEN2 corresponds to * CM_IDLEST2). This is not true for all modules. No return value. */ -void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, - u8 *idlest_bit, u8 *idlest_val) +void omap2_clk_dflt_find_idlest(struct clk_hw_omap *oclk, + void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val) { u32 r;

- r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); + r = (((__force u32)oclk->enable_reg & ~0xf0) | 0x20); *idlest_reg = (__force void __iomem *)r; - *idlest_bit = clk->enable_bit; + *idlest_bit = oclk->enable_bit;

/* * 24xx uses 0 to indicate not ready, and 1 to indicate ready. @@ -195,231 +220,82 @@ void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg,

int omap2_dflt_clk_enable(struct clk *clk) { + struct clk_hw_omap *oclk; u32 v; + int ret = 0; + + oclk = to_clk_hw_omap(clk);

- if (unlikely(clk->enable_reg == NULL)) { - pr_err("clock.c: Enable for %s without enable code\n", - clk->name); - return 0; /* REVISIT: -EINVAL */ + if (clkdm_control && oclk->clkdm) { + ret = clkdm_clk_enable(oclk->clkdm, &oclk->clk); + if (ret) { + WARN(1, "%s: could not enable %s's clockdomain %s: %d\n", + __func__, oclk->clk.name, + oclk->clkdm->name, ret); + goto out; + } }

- v = __raw_readl(clk->enable_reg); - if (clk->flags & INVERT_ENABLE) - v &= ~(1 << clk->enable_bit); + if (unlikely(oclk->enable_reg == NULL)) { + pr_err("%s: %s missing enable_reg\n", __func__, oclk->clk.name); + ret = -EINVAL; + goto err; + } + + /* FIXME should not have INVERT_ENABLE bit here */ + v = __raw_readl(oclk->enable_reg); + if (oclk->flags & INVERT_ENABLE) + v &= ~(1 << oclk->enable_bit); else - v |= (1 << clk->enable_bit); - __raw_writel(v, clk->enable_reg); - v = __raw_readl(clk->enable_reg); /* OCP barrier */ + v |= (1 << oclk->enable_bit); + __raw_writel(v, oclk->enable_reg); + v = __raw_readl(oclk->enable_reg); /* OCP barrier */

- if (clk->ops->find_idlest) - _omap2_module_wait_ready(clk); + if (oclk->find_idlest) + _omap2_module_wait_ready(oclk);

- return 0; +err: + if (clkdm_control && oclk->clkdm) + clkdm_clk_disable(oclk->clkdm, &oclk->clk); +out: + return ret; }

void omap2_dflt_clk_disable(struct clk *clk) { + struct clk_hw_omap *oclk; u32 v;

- if (!clk->enable_reg) { + oclk = to_clk_hw_omap(clk); + + if (!oclk->enable_reg) { /* - * 'Independent' here refers to a clock which is not + * 'independent' here refers to a clock which is not * controlled by its parent. */ - printk(KERN_ERR "clock: clk_disable called on independent " - "clock %s which has no enable_reg\n", clk->name); + pr_err("%s: independent clock %s has no enable_reg\n", + __func__, oclk->clk.name); return; }

- v = __raw_readl(clk->enable_reg); - if (clk->flags & INVERT_ENABLE) - v |= (1 << clk->enable_bit); + v = __raw_readl(oclk->enable_reg); + if (oclk->flags & INVERT_ENABLE) + v |= (1 << oclk->enable_bit); else - v &= ~(1 << clk->enable_bit); - __raw_writel(v, clk->enable_reg); + v &= ~(1 << oclk->enable_bit); + __raw_writel(v, oclk->enable_reg); /* No OCP barrier needed here since it is a disable operation */ -} - -const struct clkops clkops_omap2_dflt_wait = { - .enable = omap2_dflt_clk_enable, - .disable = omap2_dflt_clk_disable, - .find_companion = omap2_clk_dflt_find_companion, - .find_idlest = omap2_clk_dflt_find_idlest, -}; - -const struct clkops clkops_omap2_dflt = { - .enable = omap2_dflt_clk_enable, - .disable = omap2_dflt_clk_disable, -}; - -/** - * omap2_clk_disable - disable a clock, if the system is not using it - * @clk: struct clk * to disable - * - * Decrements the usecount on struct clk @clk. If there are no users - * left, call the clkops-specific clock disable function to disable it - * in hardware. If the clock is part of a clockdomain (which they all - * should be), request that the clockdomain be disabled. (It too has - * a usecount, and so will not be disabled in the hardware until it no - * longer has any users.) If the clock has a parent clock (most of - * them do), then call ourselves, recursing on the parent clock. This - * can cause an entire branch of the clock tree to be powered off by - * simply disabling one clock. Intended to be called with the clockfw_lock - * spinlock held. No return value. - */ -void omap2_clk_disable(struct clk *clk) -{ - if (clk->usecount == 0) { - WARN(1, "clock: %s: omap2_clk_disable() called, but usecount " - "already 0?", clk->name); - return; - }

- pr_debug("clock: %s: decrementing usecount\n", clk->name); - - clk->usecount--; - - if (clk->usecount > 0) - return; - - pr_debug("clock: %s: disabling in hardware\n", clk->name); - - if (clk->ops && clk->ops->disable) { - trace_clock_disable(clk->name, 0, smp_processor_id()); - clk->ops->disable(clk); - } - - if (clkdm_control && clk->clkdm) - clkdm_clk_disable(clk->clkdm, clk); - - if (clk->parent) - omap2_clk_disable(clk->parent); + if (clkdm_control && oclk->clkdm) + clkdm_clk_disable(oclk->clkdm, &oclk->clk); }

-/** - * omap2_clk_enable - request that the system enable a clock - * @clk: struct clk * to enable - * - * Increments the usecount on struct clk @clk. If there were no users - * previously, then recurse up the clock tree, enabling all of the - * clock's parents and all of the parent clockdomains, and finally, - * enabling @clk's clockdomain, and @clk itself. Intended to be - * called with the clockfw_lock spinlock held. Returns 0 upon success - * or a negative error code upon failure. - */ -int omap2_clk_enable(struct clk *clk) -{ - int ret; - - pr_debug("clock: %s: incrementing usecount\n", clk->name); - - clk->usecount++; - - if (clk->usecount > 1) - return 0; - - pr_debug("clock: %s: enabling in hardware\n", clk->name); - - if (clk->parent) { - ret = omap2_clk_enable(clk->parent); - if (ret) { - WARN(1, "clock: %s: could not enable parent %s: %d\n", - clk->name, clk->parent->name, ret); - goto oce_err1; - } - } - - if (clkdm_control && clk->clkdm) { - ret = clkdm_clk_enable(clk->clkdm, clk); - if (ret) { - WARN(1, "clock: %s: could not enable clockdomain %s: " - "%d\n", clk->name, clk->clkdm->name, ret); - goto oce_err2; - } - } - - if (clk->ops && clk->ops->enable) { - trace_clock_enable(clk->name, 1, smp_processor_id()); - ret = clk->ops->enable(clk); - if (ret) { - WARN(1, "clock: %s: could not enable: %d\n", - clk->name, ret); - goto oce_err3; - } - } - - return 0; - -oce_err3: - if (clkdm_control && clk->clkdm) - clkdm_clk_disable(clk->clkdm, clk); -oce_err2: - if (clk->parent) - omap2_clk_disable(clk->parent); -oce_err1: - clk->usecount--; - - return ret; -} - -/* Given a clock and a rate apply a clock specific rounding function */ -long omap2_clk_round_rate(struct clk *clk, unsigned long rate) -{ - if (clk->round_rate) - return clk->round_rate(clk, rate); - - return clk->rate; -} - -/* Set the clock rate for a clock source */ -int omap2_clk_set_rate(struct clk *clk, unsigned long rate) -{ - int ret = -EINVAL; - - pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate); - - /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */ - if (clk->set_rate) { - trace_clock_set_rate(clk->name, rate, smp_processor_id()); - ret = clk->set_rate(clk, rate); - } - - return ret; -} - -int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) -{ - if (!clk->clksel) - return -EINVAL; - - if (clk->parent == new_parent) - return 0; - - return omap2_clksel_set_parent(clk, new_parent); -} - -/* OMAP3/4 non-CORE DPLL clkops */ - -#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) - -const struct clkops clkops_omap3_noncore_dpll_ops = { - .enable = omap3_noncore_dpll_enable, - .disable = omap3_noncore_dpll_disable, - .allow_idle = omap3_dpll_allow_idle, - .deny_idle = omap3_dpll_deny_idle, -}; - -const struct clkops clkops_omap3_core_dpll_ops = { - .allow_idle = omap3_dpll_allow_idle, - .deny_idle = omap3_dpll_deny_idle, -}; - -#endif - /* * OMAP2+ clock reset and init functions */

+/* FIXME revisit to figure out how common clk should do this */ +#if 0 #ifdef CONFIG_OMAP_RESET_CLOCKS void omap2_clk_disable_unused(struct clk *clk) { @@ -442,6 +318,7 @@ void omap2_clk_disable_unused(struct clk *clk) pwrdm_clkdm_state_switch(clk->clkdm); } #endif +#endif

/** * omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument @@ -479,7 +356,14 @@ int __init omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name) }

calibrate_delay(); + /* + * FIXME + * 1) this code shouldn't be here + * 2) common clk should provide recalculate_root_clks + */ +#if 0 recalculate_root_clocks(); +#endif

clk_put(mpurate_ck);

@@ -527,19 +411,36 @@ void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name, (clk_get_rate(mpu_ck) / 1000000)); }

-/* Common data */ - -struct clk_functions omap2_clk_functions = { - .clk_enable = omap2_clk_enable, - .clk_disable = omap2_clk_disable, - .clk_round_rate = omap2_clk_round_rate, - .clk_set_rate = omap2_clk_set_rate, - .clk_set_parent = omap2_clk_set_parent, - .clk_disable_unused = omap2_clk_disable_unused, -#ifdef CONFIG_CPU_FREQ - /* These will be removed when the OPP code is integrated */ - .clk_init_cpufreq_table = omap2_clk_init_cpufreq_table, - .clk_exit_cpufreq_table = omap2_clk_exit_cpufreq_table, -#endif +/** + * omap2_get_parent_fixed - helper function to return fixed parent + * @hw - pointer to struct clk_hw + * + * Returns struct clk_hw_omap->parent (whether or not it exists). + */ +struct clk *omap2_get_parent_fixed(struct clk *clk) +{ + struct clk_hw_omap *oclk; + + if (!clk) + return ERR_PTR(-EINVAL); + + oclk = to_clk_hw_omap(clk); + + /* may be NULL. Up to the caller to handle */ + if (!oclk->fixed_parent) + pr_debug("%s: oclk->parent is NULL for %s\n", __func__, oclk->clk.name); + + return oclk->fixed_parent; };

+unsigned long omap2_recalc_rate_fixed(struct clk *clk) +{ + struct clk_hw_omap *oclk; + + if (!clk) + return -EINVAL; + + oclk = to_clk_hw_omap(clk); + + return oclk->fixed_rate; +} diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 2311bc2..b1e13ce 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -1,12 +1,13 @@ /* * linux/arch/arm/mach-omap2/clock.h * - * Copyright (C) 2005-2009 Texas Instruments, Inc. + * Copyright (C) 2005-2011 Texas Instruments, Inc. * Copyright (C) 2004-2011 Nokia Corporation * * Contacts: * Richard Woodruff r-woodruff2@ti.com * Paul Walmsley + * Mike Turquette mturquette@ti.com * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -49,24 +50,21 @@ /* DPLL Type and DCO Selection Flags */ #define DPLL_J_TYPE 0x1

-int omap2_clk_enable(struct clk *clk); -void omap2_clk_disable(struct clk *clk); -long omap2_clk_round_rate(struct clk *clk, unsigned long rate); -int omap2_clk_set_rate(struct clk *clk, unsigned long rate); -int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent); -long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate); +long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate, + unsigned long *parent_rate); unsigned long omap3_dpll_recalc(struct clk *clk); unsigned long omap3_clkoutx2_recalc(struct clk *clk); -void omap3_dpll_allow_idle(struct clk *clk); -void omap3_dpll_deny_idle(struct clk *clk); -u32 omap3_dpll_autoidle_read(struct clk *clk); +void omap3_dpll_allow_idle(struct clk_hw_omap *oclk); +void omap3_dpll_deny_idle(struct clk_hw_omap *oclk); +u32 omap3_dpll_autoidle_read(struct clk_hw_omap *oclk); int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate); int omap3_noncore_dpll_enable(struct clk *clk); void omap3_noncore_dpll_disable(struct clk *clk); -int omap4_dpllmx_gatectrl_read(struct clk *clk); -void omap4_dpllmx_allow_gatectrl(struct clk *clk); -void omap4_dpllmx_deny_gatectrl(struct clk *clk); -long omap4_dpll_regm4xen_round_rate(struct clk *clk, unsigned long target_rate); +int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *oclk); +void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *oclk); +void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *oclk); +long omap4_dpll_regm4xen_round_rate(struct clk *clk, unsigned long target_rate, + unsigned long *parent_rate); unsigned long omap4_dpll_regm4xen_recalc(struct clk *clk);

#ifdef CONFIG_OMAP_RESET_CLOCKS @@ -78,12 +76,16 @@ void omap2_clk_disable_unused(struct clk *clk); void omap2_init_clk_clkdm(struct clk *clk); void __init omap2_clk_disable_clkdm_control(void);

+struct clk *omap2_get_parent_fixed(struct clk *clk); +unsigned long omap2_recalc_rate_fixed(struct clk *clk); + /* clkt_clksel.c public functions */ -u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, +u32 omap2_clksel_round_rate_div(struct clk_hw_omap *oclk, unsigned long target_rate, u32 *new_div); -void omap2_init_clksel_parent(struct clk *clk); +struct clk *omap2_init_clksel_parent(struct clk *clk); unsigned long omap2_clksel_recalc(struct clk *clk); -long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate); +long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate, + unsigned long *parent_rate); int omap2_clksel_set_rate(struct clk *clk, unsigned long rate); int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent);

@@ -91,8 +93,8 @@ int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent); extern void omap2_clkt_iclk_allow_idle(struct clk *clk); extern void omap2_clkt_iclk_deny_idle(struct clk *clk);

-u32 omap2_get_dpll_rate(struct clk *clk); -void omap2_init_dpll_parent(struct clk *clk); +unsigned long omap2_get_dpll_rate(struct clk_hw_omap *oclk); +struct clk *omap2_init_dpll_parent(struct clk *clk);

int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name);

@@ -123,22 +125,27 @@ static inline void omap4_clk_prepare_for_reboot(void)

int omap2_dflt_clk_enable(struct clk *clk); void omap2_dflt_clk_disable(struct clk *clk); -void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, - u8 *other_bit); -void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, - u8 *idlest_bit, u8 *idlest_val); + +void omap2_clk_dflt_find_companion(struct clk_hw_omap *oclk, + void __iomem **other_reg, u8 *other_bit); +void omap2_clk_dflt_find_idlest(struct clk_hw_omap *oclk, + void __iomem **idlest_reg, u8 *idlest_bit, + u8 *idlest_val); int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name); void omap2_clk_print_new_rates(const char *hfclkin_ck_name, - const char *core_ck_name, - const char *mpu_ck_name); + const char *core_ck_name, + const char *mpu_ck_name);

+extern struct clk_hw_omap dummy_ck_hw; extern u8 cpu_mask;

+#if 0 extern const struct clkops clkops_omap2_dflt_wait; extern const struct clkops clkops_dummy; extern const struct clkops clkops_omap2_dflt;

extern struct clk_functions omap2_clk_functions; +#endif extern struct clk *vclk, *sclk;

extern const struct clksel_rate gpt_32k_rates[]; @@ -154,6 +161,7 @@ extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table) #define omap2_clk_exit_cpufreq_table 0 #endif

+#if 0 extern const struct clkops clkops_omap2_iclk_dflt_wait; extern const struct clkops clkops_omap2_iclk_dflt; extern const struct clkops clkops_omap2_iclk_idle_only; @@ -162,5 +170,6 @@ extern const struct clkops clkops_omap2xxx_dpll_ops; extern const struct clkops clkops_omap3_noncore_dpll_ops; extern const struct clkops clkops_omap3_core_dpll_ops; extern const struct clkops clkops_omap4_dpllmx_ops; +#endif

#endif diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c index fc56745..b241257 100644 --- a/arch/arm/mach-omap2/dpll3xxx.c +++ b/arch/arm/mach-omap2/dpll3xxx.c @@ -44,12 +44,12 @@ /* Private functions */

/* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */ -static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits) +static void _omap3_dpll_write_clken(struct clk_hw_omap *oclk, u8 clken_bits) { const struct dpll_data *dd; u32 v;

- dd = clk->dpll_data; + dd = oclk->dpll_data;

v = __raw_readl(dd->control_reg); v &= ~dd->enable_mask; @@ -58,13 +58,13 @@ static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits) }

/* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */ -static int _omap3_wait_dpll_status(struct clk *clk, u8 state) +static int _omap3_wait_dpll_status(struct clk_hw_omap *oclk, u8 state) { const struct dpll_data *dd; int i = 0; int ret = -EINVAL;

- dd = clk->dpll_data; + dd = oclk->dpll_data;

state <<= __ffs(dd->idlest_mask);

@@ -75,11 +75,11 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state) }

if (i == MAX_DPLL_WAIT_TRIES) { - printk(KERN_ERR "clock: %s failed transition to '%s'\n", - clk->name, (state) ? "locked" : "bypassed"); + pr_err("%s: %s failed transition to '%s'\n", __func__, + oclk->clk.name, (state) ? "locked" : "bypassed"); } else { - pr_debug("clock: %s transition to '%s' in %d loops\n", - clk->name, (state) ? "locked" : "bypassed", i); + pr_debug("%s: %s transition to '%s' in %d loops\n", __func__, + oclk->clk.name, (state) ? "locked" : "bypassed", i);

ret = 0; } @@ -88,12 +88,12 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state) }

/* From 3430 TRM ES2 4.7.6.2 */ -static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n) +static u16 _omap3_dpll_compute_freqsel(struct clk_hw_omap *oclk, u8 n) { unsigned long fint; u16 f = 0;

- fint = clk->dpll_data->clk_ref->rate / n; + fint = oclk->dpll_data->clk_ref->rate / n;

pr_debug("clock: fint is %lu\n", fint);

@@ -133,23 +133,23 @@ static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n) * locked successfully, return 0; if the DPLL did not lock in the time * allotted, or DPLL3 was passed in, return -EINVAL. */ -static int _omap3_noncore_dpll_lock(struct clk *clk) +static int _omap3_noncore_dpll_lock(struct clk_hw_omap *oclk) { u8 ai; int r;

- pr_debug("clock: locking DPLL %s\n", clk->name); + pr_debug("%s: locking DPLL %s\n", __func__, oclk->clk.name);

- ai = omap3_dpll_autoidle_read(clk); + ai = omap3_dpll_autoidle_read(oclk);

- omap3_dpll_deny_idle(clk); + omap3_dpll_deny_idle(oclk);

- _omap3_dpll_write_clken(clk, DPLL_LOCKED); + _omap3_dpll_write_clken(oclk, DPLL_LOCKED);

- r = _omap3_wait_dpll_status(clk, 1); + r = _omap3_wait_dpll_status(oclk, 1);

if (ai) - omap3_dpll_allow_idle(clk); + omap3_dpll_allow_idle(oclk);

return r; } @@ -167,27 +167,30 @@ static int _omap3_noncore_dpll_lock(struct clk *clk) * DPLL3 was passed in, or the DPLL does not support low-power bypass, * return -EINVAL. */ -static int _omap3_noncore_dpll_bypass(struct clk *clk) +static int _omap3_noncore_dpll_bypass(struct clk_hw_omap *oclk) { + const struct dpll_data *dd; int r; u8 ai;

- if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) + dd = oclk->dpll_data; + + if (!(dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) return -EINVAL;

- pr_debug("clock: configuring DPLL %s for low-power bypass\n", - clk->name); + pr_debug("%s: configuring DPLL %s for low-power bypass\n", + __func__, oclk->clk.name);

- ai = omap3_dpll_autoidle_read(clk); + ai = omap3_dpll_autoidle_read(oclk);

- _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS); + _omap3_dpll_write_clken(oclk, DPLL_LOW_POWER_BYPASS);

- r = _omap3_wait_dpll_status(clk, 0); + r = _omap3_wait_dpll_status(oclk, 0);

if (ai) - omap3_dpll_allow_idle(clk); + omap3_dpll_allow_idle(oclk); else - omap3_dpll_deny_idle(clk); + omap3_dpll_deny_idle(oclk);

return r; } @@ -201,23 +204,26 @@ static int _omap3_noncore_dpll_bypass(struct clk *clk) * code. If DPLL3 was passed in, or the DPLL does not support * low-power stop, return -EINVAL; otherwise, return 0. */ -static int _omap3_noncore_dpll_stop(struct clk *clk) +static int _omap3_noncore_dpll_stop(struct clk_hw_omap *oclk) { + const struct dpll_data *dd; u8 ai;

- if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP))) + dd = oclk->dpll_data; + + if (!(dd->modes & (1 << DPLL_LOW_POWER_STOP))) return -EINVAL;

- pr_debug("clock: stopping DPLL %s\n", clk->name); + pr_debug("%s: stopping DPLL %s\n", __func__, oclk->clk.name);

- ai = omap3_dpll_autoidle_read(clk); + ai = omap3_dpll_autoidle_read(oclk);

- _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP); + _omap3_dpll_write_clken(oclk, DPLL_LOW_POWER_STOP);

if (ai) - omap3_dpll_allow_idle(clk); + omap3_dpll_allow_idle(oclk); else - omap3_dpll_deny_idle(clk); + omap3_dpll_deny_idle(oclk);

return 0; } @@ -234,11 +240,11 @@ static int _omap3_noncore_dpll_stop(struct clk *clk) * XXX This code is not needed for 3430/AM35xx; can it be optimized * out in non-multi-OMAP builds for those chips? */ -static void _lookup_dco(struct clk *clk, u8 *dco, u16 m, u8 n) +static void _lookup_dco(struct clk_hw_omap *oclk, u8 *dco, u16 m, u8 n) { unsigned long fint, clkinp; /* watch out for overflow */

- clkinp = clk->parent->rate; + clkinp = oclk->clk.parent->rate; fint = (clkinp / n) * m;

if (fint < 1000000000) @@ -259,12 +265,12 @@ static void _lookup_dco(struct clk *clk, u8 *dco, u16 m, u8 n) * XXX This code is not needed for 3430/AM35xx; can it be optimized * out in non-multi-OMAP builds for those chips? */ -static void _lookup_sddiv(struct clk *clk, u8 *sd_div, u16 m, u8 n) +static void _lookup_sddiv(struct clk_hw_omap *oclk, u8 *sd_div, u16 m, u8 n) { unsigned long clkinp, sd; /* watch out for overflow */ int mod1, mod2;

- clkinp = clk->parent->rate; + clkinp = oclk->clk.parent->rate;

/* * target sigma-delta to near 250MHz @@ -291,14 +297,16 @@ static void _lookup_sddiv(struct clk *clk, u8 *sd_div, u16 m, u8 n) * Program the DPLL with the supplied M, N values, and wait for the DPLL to * lock.. Returns -EINVAL upon error, or 0 upon success. */ -static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) +static int omap3_noncore_dpll_program(struct clk_hw_omap *oclk, u16 m, u8 n, u16 freqsel) { - struct dpll_data *dd = clk->dpll_data; + struct dpll_data *dd; u8 dco, sd_div; u32 v;

+ dd = oclk->dpll_data; + /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */ - _omap3_noncore_dpll_bypass(clk); + _omap3_noncore_dpll_bypass(oclk);

/* * Set jitter correction. No jitter correction for OMAP4 and 3630 @@ -319,12 +327,12 @@ static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)

/* Configure dco and sd_div for dplls that have these fields */ if (dd->dco_mask) { - _lookup_dco(clk, &dco, m, n); + _lookup_dco(oclk, &dco, m, n); v &= ~(dd->dco_mask); v |= dco << __ffs(dd->dco_mask); } if (dd->sddiv_mask) { - _lookup_sddiv(clk, &sd_div, m, n); + _lookup_sddiv(oclk, &sd_div, m, n); v &= ~(dd->sddiv_mask); v |= sd_div << __ffs(dd->sddiv_mask); } @@ -335,7 +343,7 @@ static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)

/* REVISIT: Set ramp-up delay? */

- _omap3_noncore_dpll_lock(clk); + _omap3_noncore_dpll_lock(oclk);

return 0; } @@ -350,7 +358,11 @@ static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) */ unsigned long omap3_dpll_recalc(struct clk *clk) { - return omap2_get_dpll_rate(clk); + struct clk_hw_omap *oclk; + + oclk = to_clk_hw_omap(clk); + + return omap2_get_dpll_rate(oclk); }

/* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */ @@ -371,27 +383,22 @@ unsigned long omap3_dpll_recalc(struct clk *clk) */ int omap3_noncore_dpll_enable(struct clk *clk) { - int r; + struct clk_hw_omap *oclk; struct dpll_data *dd; + int r;

- dd = clk->dpll_data; + oclk = to_clk_hw_omap(clk); + dd = oclk->dpll_data; if (!dd) return -EINVAL;

- if (clk->rate == dd->clk_bypass->rate) { - WARN_ON(clk->parent != dd->clk_bypass); - r = _omap3_noncore_dpll_bypass(clk); + if (oclk->clk.rate == dd->clk_bypass->rate) { + WARN_ON(oclk->clk.parent != dd->clk_bypass); + r = _omap3_noncore_dpll_bypass(oclk); } else { - WARN_ON(clk->parent != dd->clk_ref); - r = _omap3_noncore_dpll_lock(clk); + WARN_ON(oclk->clk.parent != dd->clk_ref); + r = _omap3_noncore_dpll_lock(oclk); } - /* - *FIXME: this is dubious - if clk->rate has changed, what about - * propagating? - */ - if (!r) - clk->rate = (clk->recalc) ? clk->recalc(clk) : - omap2_get_dpll_rate(clk);

return r; } @@ -405,7 +412,11 @@ int omap3_noncore_dpll_enable(struct clk *clk) */ void omap3_noncore_dpll_disable(struct clk *clk) { - _omap3_noncore_dpll_stop(clk); + struct clk_hw_omap *oclk; + + oclk = to_clk_hw_omap(clk); + + _omap3_noncore_dpll_stop(oclk); }

@@ -424,8 +435,9 @@ void omap3_noncore_dpll_disable(struct clk *clk) */ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) { + struct clk_hw_omap *oclk; struct clk *new_parent = NULL; - unsigned long hw_rate; + //unsigned long hw_rate; u16 freqsel = 0; struct dpll_data *dd; int ret; @@ -433,48 +445,56 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) if (!clk || !rate) return -EINVAL;

- dd = clk->dpll_data; + oclk = to_clk_hw_omap(clk); + dd = oclk->dpll_data; + if (!dd) return -EINVAL;

+ /* FIXME revisit - not sure this makes sense any more */ +#if 0 hw_rate = (clk->recalc) ? clk->recalc(clk) : omap2_get_dpll_rate(clk); if (rate == hw_rate) return 0; +#endif

/* * Ensure both the bypass and ref clocks are enabled prior to * doing anything; we need the bypass clock running to reprogram * the DPLL. */ - omap2_clk_enable(dd->clk_bypass); - omap2_clk_enable(dd->clk_ref); + __clk_prepare(dd->clk_bypass); + clk_enable(dd->clk_bypass); + __clk_prepare(dd->clk_ref); + clk_enable(dd->clk_ref);

if (dd->clk_bypass->rate == rate && - (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) { - pr_debug("clock: %s: set rate: entering bypass.\n", clk->name); + (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) { + pr_debug("%s: %s: set rate: entering bypass.\n", + __func__, oclk->clk.name);

- ret = _omap3_noncore_dpll_bypass(clk); + ret = _omap3_noncore_dpll_bypass(oclk); if (!ret) new_parent = dd->clk_bypass; } else { if (dd->last_rounded_rate != rate) - rate = clk->round_rate(clk, rate); + rate = clk_round_rate(&oclk->clk, rate);

if (dd->last_rounded_rate == 0) return -EINVAL;

/* No freqsel on OMAP4 and OMAP3630 */ if (!cpu_is_omap44xx() && !cpu_is_omap3630()) { - freqsel = _omap3_dpll_compute_freqsel(clk, + freqsel = _omap3_dpll_compute_freqsel(oclk, dd->last_rounded_n); if (!freqsel) WARN_ON(1); }

- pr_debug("clock: %s: set rate: locking rate to %lu.\n", - clk->name, rate); + pr_debug("%s: %s: set rate: locking rate to %lu.\n", + __func__, oclk->clk.name, rate);

- ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m, + ret = omap3_noncore_dpll_program(oclk, dd->last_rounded_m, dd->last_rounded_n, freqsel); if (!ret) new_parent = dd->clk_ref; @@ -486,15 +506,16 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) * enable the new parent before disabling the old to avoid * any unnecessary hardware disable->enable transitions. */ - if (clk->usecount) { - omap2_clk_enable(new_parent); - omap2_clk_disable(clk->parent); + if (oclk->clk.enable_count) { + clk_enable(new_parent); + clk_disable(oclk->clk.parent); } - clk_reparent(clk, new_parent); - clk->rate = rate; + __clk_reparent(&oclk->clk, new_parent); } - omap2_clk_disable(dd->clk_ref); - omap2_clk_disable(dd->clk_bypass); + clk_disable(dd->clk_ref); + __clk_unprepare(dd->clk_ref); + clk_disable(dd->clk_bypass); + __clk_unprepare(dd->clk_bypass);

return 0; } @@ -509,15 +530,15 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) * -EINVAL if passed a null pointer or if the struct clk does not * appear to refer to a DPLL. */ -u32 omap3_dpll_autoidle_read(struct clk *clk) +u32 omap3_dpll_autoidle_read(struct clk_hw_omap *oclk) { const struct dpll_data *dd; u32 v;

- if (!clk || !clk->dpll_data) + if (!oclk || !oclk->dpll_data) return -EINVAL;

- dd = clk->dpll_data; + dd = oclk->dpll_data;

v = __raw_readl(dd->autoidle_reg); v &= dd->autoidle_mask; @@ -535,15 +556,15 @@ u32 omap3_dpll_autoidle_read(struct clk *clk) * OMAP3430. The DPLL will enter low-power stop when its downstream * clocks are gated. No return value. */ -void omap3_dpll_allow_idle(struct clk *clk) +void omap3_dpll_allow_idle(struct clk_hw_omap *oclk) { const struct dpll_data *dd; u32 v;

- if (!clk || !clk->dpll_data) + if (!oclk || !oclk->dpll_data) return;

- dd = clk->dpll_data; + dd = oclk->dpll_data;

/* * REVISIT: CORE DPLL can optionally enter low-power bypass @@ -562,15 +583,15 @@ void omap3_dpll_allow_idle(struct clk *clk) * * Disable DPLL automatic idle control. No return value. */ -void omap3_dpll_deny_idle(struct clk *clk) +void omap3_dpll_deny_idle(struct clk_hw_omap *oclk) { const struct dpll_data *dd; u32 v;

- if (!clk || !clk->dpll_data) + if (!oclk || !oclk->dpll_data) return;

- dd = clk->dpll_data; + dd = oclk->dpll_data;

v = __raw_readl(dd->autoidle_reg); v &= ~dd->autoidle_mask; @@ -590,28 +611,39 @@ void omap3_dpll_deny_idle(struct clk *clk) */ unsigned long omap3_clkoutx2_recalc(struct clk *clk) { + struct clk_hw_omap *oclk; + struct clk_hw_omap *poclk; + struct clk *parent; const struct dpll_data *dd; unsigned long rate; u32 v; - struct clk *pclk;

- /* Walk up the parents of clk, looking for a DPLL */ - pclk = clk->parent; - while (pclk && !pclk->dpll_data) - pclk = pclk->parent; + parent = clk->parent; + if (!parent) { + WARN_ON(1); + return -EINVAL; + }

- /* clk does not have a DPLL as a parent? */ - WARN_ON(!pclk); + oclk = to_clk_hw_omap(clk); + poclk = to_clk_hw_omap(parent);

- dd = pclk->dpll_data; + if (!poclk->dpll_data) { + WARN_ON(1); + return -EINVAL; + } + + dd = poclk->dpll_data;

- WARN_ON(!dd->enable_mask); + if (!dd->enable_mask) { + WARN_ON(1); + return -EINVAL; + }

v = __raw_readl(dd->control_reg) & dd->enable_mask; v >>= __ffs(dd->enable_mask); if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE)) - rate = clk->parent->rate; + rate = parent->rate; else - rate = clk->parent->rate * 2; + rate = parent->rate * 2; return rate; } diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c index 9c6a296..210a87c 100644 --- a/arch/arm/mach-omap2/dpll44xx.c +++ b/arch/arm/mach-omap2/dpll44xx.c @@ -23,65 +23,68 @@ #include "cm-regbits-44xx.h"

/* Supported only on OMAP4 */ -int omap4_dpllmx_gatectrl_read(struct clk *clk) +int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *oclk) { u32 v; u32 mask;

- if (!clk || !clk->clksel_reg || !cpu_is_omap44xx()) + if (!oclk->clksel_reg || !cpu_is_omap44xx()) return -EINVAL;

- mask = clk->flags & CLOCK_CLKOUTX2 ? + mask = oclk->flags & CLOCK_CLKOUTX2 ? OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK : OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;

- v = __raw_readl(clk->clksel_reg); + v = __raw_readl(oclk->clksel_reg); v &= mask; v >>= __ffs(mask);

return v; }

-void omap4_dpllmx_allow_gatectrl(struct clk *clk) +void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *oclk) { u32 v; u32 mask;

- if (!clk || !clk->clksel_reg || !cpu_is_omap44xx()) + if (!oclk->clksel_reg || !cpu_is_omap44xx()) return;

- mask = clk->flags & CLOCK_CLKOUTX2 ? + mask = oclk->flags & CLOCK_CLKOUTX2 ? OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK : OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;

- v = __raw_readl(clk->clksel_reg); + v = __raw_readl(oclk->clksel_reg); /* Clear the bit to allow gatectrl */ v &= ~mask; - __raw_writel(v, clk->clksel_reg); + __raw_writel(v, oclk->clksel_reg); }

-void omap4_dpllmx_deny_gatectrl(struct clk *clk) +void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *oclk) { u32 v; u32 mask;

- if (!clk || !clk->clksel_reg || !cpu_is_omap44xx()) + if (!oclk->clksel_reg || !cpu_is_omap44xx()) return;

- mask = clk->flags & CLOCK_CLKOUTX2 ? + mask = oclk->flags & CLOCK_CLKOUTX2 ? OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK : OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;

- v = __raw_readl(clk->clksel_reg); + v = __raw_readl(oclk->clksel_reg); /* Set the bit to deny gatectrl */ v |= mask; - __raw_writel(v, clk->clksel_reg); + __raw_writel(v, oclk->clksel_reg); }

+/* XXX moved directly into struct clk_hw_omap */ +#if 0 const struct clkops clkops_omap4_dpllmx_ops = { .allow_idle = omap4_dpllmx_allow_gatectrl, .deny_idle = omap4_dpllmx_deny_gatectrl, }; +#endif

/** * omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit @@ -96,14 +99,20 @@ unsigned long omap4_dpll_regm4xen_recalc(struct clk *clk) { u32 v; unsigned long rate; + struct clk_hw_omap *oclk; struct dpll_data *dd;

- if (!clk || !clk->dpll_data) + if (!clk) return 0;

- dd = clk->dpll_data; + oclk = to_clk_hw_omap(clk);

- rate = omap2_get_dpll_rate(clk); + if (!oclk->dpll_data) + return 0; + + dd = oclk->dpll_data; + + rate = omap2_get_dpll_rate(oclk);

/* regm4xen adds a multiplier of 4 to DPLL calculations */ v = __raw_readl(dd->control_reg); @@ -125,16 +134,23 @@ unsigned long omap4_dpll_regm4xen_recalc(struct clk *clk) * M-dividers) upon success, -EINVAL if @clk is null or not a DPLL, or * ~0 if an error occurred in omap2_dpll_round_rate(). */ -long omap4_dpll_regm4xen_round_rate(struct clk *clk, unsigned long target_rate) +long omap4_dpll_regm4xen_round_rate(struct clk *clk, unsigned long target_rate, + unsigned long *parent_rate) { u32 v; + struct clk_hw_omap *oclk; struct dpll_data *dd; long r;

- if (!clk || !clk->dpll_data) + if (!clk) + return -EINVAL; + + oclk = to_clk_hw_omap(clk); + + if (!oclk->dpll_data) return -EINVAL;

- dd = clk->dpll_data; + dd = oclk->dpll_data;

/* regm4xen adds a multiplier of 4 to DPLL calculations */ v = __raw_readl(dd->control_reg) & OMAP4430_DPLL_REGM4XEN_MASK; @@ -142,12 +158,12 @@ long omap4_dpll_regm4xen_round_rate(struct clk *clk, unsigned long target_rate) if (v) target_rate = target_rate / OMAP4430_REGM4XEN_MULT;

- r = omap2_dpll_round_rate(clk, target_rate); + r = omap2_dpll_round_rate(clk, target_rate, NULL); if (r == ~0) return r;

if (v) - clk->dpll_data->last_rounded_rate *= OMAP4430_REGM4XEN_MULT; + dd->last_rounded_rate *= OMAP4430_REGM4XEN_MULT;

- return clk->dpll_data->last_rounded_rate; + return dd->last_rounded_rate; } diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c index 567e4b5..670ab2c 100644 --- a/arch/arm/plat-omap/clock.c +++ b/arch/arm/plat-omap/clock.c @@ -25,153 +25,8 @@

#include <plat/clock.h>

-static LIST_HEAD(clocks); -static DEFINE_MUTEX(clocks_mutex); -static DEFINE_SPINLOCK(clockfw_lock); - -static struct clk_functions *arch_clock; - -/* - * Standard clock functions defined in include/linux/clk.h - */ - -int clk_enable(struct clk *clk) -{ - unsigned long flags; - int ret; - - if (clk == NULL || IS_ERR(clk)) - return -EINVAL; - - if (!arch_clock || !arch_clock->clk_enable) - return -EINVAL; - - spin_lock_irqsave(&clockfw_lock, flags); - ret = arch_clock->clk_enable(clk); - spin_unlock_irqrestore(&clockfw_lock, flags); - - return ret; -} -EXPORT_SYMBOL(clk_enable); - -void clk_disable(struct clk *clk) -{ - unsigned long flags; - - if (clk == NULL || IS_ERR(clk)) - return; - - if (!arch_clock || !arch_clock->clk_disable) - return; - - spin_lock_irqsave(&clockfw_lock, flags); - if (clk->usecount == 0) { - pr_err("Trying disable clock %s with 0 usecount\n", - clk->name); - WARN_ON(1); - goto out; - } - - arch_clock->clk_disable(clk); - -out: - spin_unlock_irqrestore(&clockfw_lock, flags); -} -EXPORT_SYMBOL(clk_disable); - -unsigned long clk_get_rate(struct clk *clk) -{ - unsigned long flags; - unsigned long ret; - - if (clk == NULL || IS_ERR(clk)) - return 0; - - spin_lock_irqsave(&clockfw_lock, flags); - ret = clk->rate; - spin_unlock_irqrestore(&clockfw_lock, flags); - - return ret; -} -EXPORT_SYMBOL(clk_get_rate); - -/* - * Optional clock functions defined in include/linux/clk.h - */ - -long clk_round_rate(struct clk *clk, unsigned long rate) -{ - unsigned long flags; - long ret; - - if (clk == NULL || IS_ERR(clk)) - return 0; - - if (!arch_clock || !arch_clock->clk_round_rate) - return 0; - - spin_lock_irqsave(&clockfw_lock, flags); - ret = arch_clock->clk_round_rate(clk, rate); - spin_unlock_irqrestore(&clockfw_lock, flags); - - return ret; -} -EXPORT_SYMBOL(clk_round_rate); - -int clk_set_rate(struct clk *clk, unsigned long rate) -{ - unsigned long flags; - int ret = -EINVAL; - - if (clk == NULL || IS_ERR(clk)) - return ret; - - if (!arch_clock || !arch_clock->clk_set_rate) - return ret; - - spin_lock_irqsave(&clockfw_lock, flags); - ret = arch_clock->clk_set_rate(clk, rate); - if (ret == 0) - propagate_rate(clk); - spin_unlock_irqrestore(&clockfw_lock, flags); - - return ret; -} -EXPORT_SYMBOL(clk_set_rate); - -int clk_set_parent(struct clk *clk, struct clk *parent) -{ - unsigned long flags; - int ret = -EINVAL; - - if (clk == NULL || IS_ERR(clk) || parent == NULL || IS_ERR(parent)) - return ret; - - if (!arch_clock || !arch_clock->clk_set_parent) - return ret; - - spin_lock_irqsave(&clockfw_lock, flags); - if (clk->usecount == 0) { - ret = arch_clock->clk_set_parent(clk, parent); - if (ret == 0) - propagate_rate(clk); - } else - ret = -EBUSY; - spin_unlock_irqrestore(&clockfw_lock, flags); - - return ret; -} -EXPORT_SYMBOL(clk_set_parent); - -struct clk *clk_get_parent(struct clk *clk) -{ - return clk->parent; -} -EXPORT_SYMBOL(clk_get_parent); - -/* - * OMAP specific clock functions shared between omap1 and omap2 - */ +LIST_HEAD(omap_clocks); +DEFINE_MUTEX(omap_clocks_mutex);

int __initdata mpurate;

@@ -193,78 +48,27 @@ static int __init omap_clk_setup(char *str) } __setup("mpurate=", omap_clk_setup);

-/* Used for clocks that always have same value as the parent clock */ -unsigned long followparent_recalc(struct clk *clk) -{ - return clk->parent->rate; -} - /* * Used for clocks that have the same value as the parent clock, * divided by some factor */ unsigned long omap_fixed_divisor_recalc(struct clk *clk) { - WARN_ON(!clk->fixed_div); + struct clk_hw_omap *oclk;

- return clk->parent->rate / clk->fixed_div; -} - -void clk_reparent(struct clk *child, struct clk *parent) -{ - list_del_init(&child->sibling); - if (parent) - list_add(&child->sibling, &parent->children); - child->parent = parent; - - /* now do the debugfs renaming to reattach the child - to the proper parent */ -} - -/* Propagate rate to children */ -void propagate_rate(struct clk *tclk) -{ - struct clk *clkp; - - list_for_each_entry(clkp, &tclk->children, sibling) { - if (clkp->recalc) - clkp->rate = clkp->recalc(clkp); - propagate_rate(clkp); + if (!clk) { + pr_warning("%s: clk is NULL\n", __func__); + return -EINVAL; } -}

-static LIST_HEAD(root_clks); + oclk = to_clk_hw_omap(clk);

-/** - * recalculate_root_clocks - recalculate and propagate all root clocks - * - * Recalculates all root clocks (clocks with no parent), which if the - * clock's .recalc is set correctly, should also propagate their rates. - * Called at init. - */ -void recalculate_root_clocks(void) -{ - struct clk *clkp; + WARN_ON(!oclk->fixed_div);

- list_for_each_entry(clkp, &root_clks, sibling) { - if (clkp->recalc) - clkp->rate = clkp->recalc(clkp); - propagate_rate(clkp); - } -} - -/** - * clk_preinit - initialize any fields in the struct clk before clk init - * @clk: struct clk * to initialize - * - * Initialize any struct clk fields needed before normal clk initialization - * can run. No return value. - */ -void clk_preinit(struct clk *clk) -{ - INIT_LIST_HEAD(&clk->children); + return oclk->clk.parent->rate / oclk->fixed_div; }

+#if 0 int clk_register(struct clk *clk) { if (clk == NULL || IS_ERR(clk)) @@ -302,7 +106,10 @@ void clk_unregister(struct clk *clk) mutex_unlock(&clocks_mutex); } EXPORT_SYMBOL(clk_unregister); +#endif

+/* FIXME useful! migrate to common clk */ +#if 0 void clk_enable_init_clocks(void) { struct clk *clkp; @@ -340,6 +147,58 @@ struct clk *omap_clk_get_by_name(const char *name) return ret; }

+/** + * recalculate_root_clocks - recalculate and propagate all root clocks + * + * Recalculates all root clocks (clocks with no parent), which if the + * clock's .recalc is set correctly, should also propagate their rates. + * Called at init. + */ +void recalculate_root_clocks(void) +{ + struct clk *clkp; + + list_for_each_entry(clkp, &root_clks, sibling) { + if (clkp->recalc) + clkp->rate = clkp->recalc(clkp); + propagate_rate(clkp); + } +} +#endif + +/** + * omap_clk_get_by_name - locate OMAP struct clk by its name + * @name: name of the struct clk to locate + * + * Locate an OMAP struct clk by its name. Assumes that struct clk + * names are unique. Returns NULL if not found or a pointer to the + * struct clk if found. + */ +struct clk *omap_clk_get_by_name(const char *name) +{ + //struct clk_hw_omap *hw; + struct clk_hw_omap *oclk; + struct clk *ret = NULL; + + mutex_lock(&omap_clocks_mutex); + + list_for_each_entry(oclk, &omap_clocks, node) { + //oclk = to_clk_hw_omap(hw); + /*pr_err("%s: name is %s, oclk->hw.clk->name is %s, pointer is %p\n", + __func__, name, oclk->hw.clk->name, oclk);*/ + if (!strcmp(oclk->clk.name, name)) { + ret = &oclk->clk; + break; + } + } + + mutex_unlock(&omap_clocks_mutex); + + return ret; +} + +/* FIXME not sure if I can migrate these. Probably refactor clk tree walk */ +#if 0 int omap_clk_enable_autoidle_all(void) { struct clk *c; @@ -371,7 +230,10 @@ int omap_clk_disable_autoidle_all(void)

return 0; } +#endif

+/* can probably live without entirely */ +#if 0 /* * Low level helpers */ @@ -398,7 +260,42 @@ struct clk dummy_ck = { .name = "dummy", .ops = &clkops_null, }; +#endif + +/* FIXME rethink the way I'm doing this... */ +#if 0 +struct clk dummy_ck; + +struct clk_dummy dummy_ck_hw = { + .hw = { + .clk = &dummy_ck, + }, +};

+struct clk dummy_ck = { + .name = "dummy_clk", + .ops = &clk_dummy_ops, + .hw = &dummy_ck_hw.hw, +}; +#endif + +/* MOVED to mach-omap2/clock.h */ +#if 0 +struct clk_hw_ops dummy_ck_ops = { + .get_parent = &omap2_get_parent_fixed, +}; + +struct clk_hw_omap dummy_ck_hw = { + .clk = { + .name = "dummy_clk", + .ops = &dummy_ck_ops, + }, +}; + +struct clk *dummy_ck = &dummy_ck_hw.clk; +#endif + +#if 0 #ifdef CONFIG_CPU_FREQ void clk_init_cpufreq_table(struct cpufreq_frequency_table **table) { @@ -424,11 +321,14 @@ void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table) spin_unlock_irqrestore(&clockfw_lock, flags); } #endif +#endif

/* * */

+/* FIXME should probably keep this, but in some other form */ +#if 0 #ifdef CONFIG_OMAP_RESET_CLOCKS /* * Disable any unused clocks left on by the bootloader @@ -459,7 +359,9 @@ static int __init clk_disable_unused(void) late_initcall(clk_disable_unused); late_initcall(omap_clk_enable_autoidle_all); #endif +#endif

+#if 0 int __init clk_init(struct clk_functions * custom_clocks) { if (!custom_clocks) { @@ -593,3 +495,4 @@ err_out: late_initcall(clk_debugfs_init);

#endif /* defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) */ +#endif diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h index eb73ab4..f0245be 100644 --- a/arch/arm/plat-omap/include/plat/clock.h +++ b/arch/arm/plat-omap/include/plat/clock.h @@ -13,40 +13,17 @@ #ifndef __ARCH_ARM_OMAP_CLOCK_H #define __ARCH_ARM_OMAP_CLOCK_H

+#include <linux/clk.h> #include <linux/list.h>

+#define to_clk_hw_omap(ck) container_of(ck, struct clk_hw_omap, clk) + struct module; struct clk; struct clockdomain;

-/** - * struct clkops - some clock function pointers - * @enable: fn ptr that enables the current clock in hardware - * @disable: fn ptr that enables the current clock in hardware - * @find_idlest: function returning the IDLEST register for the clock's IP blk - * @find_companion: function returning the "companion" clk reg for the clock - * @allow_idle: fn ptr that enables autoidle for the current clock in hardware - * @deny_idle: fn ptr that disables autoidle for the current clock in hardware - * - * A "companion" clk is an accompanying clock to the one being queried - * that must be enabled for the IP module connected to the clock to - * become accessible by the hardware. Neither @find_idlest nor - * @find_companion should be needed; that information is IP - * block-specific; the hwmod code has been created to handle this, but - * until hwmod data is ready and drivers have been converted to use PM - * runtime calls in place of clk_enable()/clk_disable(), @find_idlest and - * @find_companion must, unfortunately, remain. - */ -struct clkops { - int (*enable)(struct clk *); - void (*disable)(struct clk *); - void (*find_idlest)(struct clk *, void __iomem **, - u8 *, u8 *); - void (*find_companion)(struct clk *, void __iomem **, - u8 *); - void (*allow_idle)(struct clk *); - void (*deny_idle)(struct clk *); -}; +extern struct list_head omap_clocks; +extern struct mutex omap_clocks_mutex;

#ifdef CONFIG_ARCH_OMAP2PLUS

@@ -237,22 +214,14 @@ struct dpll_data { * XXX The notion of the clock's current rate probably needs to be * separated from the clock's target rate. */ -struct clk { +struct clk_hw_omap { + struct clk clk; struct list_head node; - const struct clkops *ops; - const char *name; - struct clk *parent; - struct list_head children; - struct list_head sibling; /* node for children */ - unsigned long rate; + unsigned long fixed_rate; + struct clk *fixed_parent; + u8 fixed_div; void __iomem *enable_reg; - unsigned long (*recalc)(struct clk *); - int (*set_rate)(struct clk *, unsigned long); - long (*round_rate)(struct clk *, unsigned long); - void (*init)(struct clk *); u8 enable_bit; - s8 usecount; - u8 fixed_div; u8 flags; #ifdef CONFIG_ARCH_OMAP2PLUS void __iomem *clksel_reg; @@ -268,35 +237,40 @@ struct clk { #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) struct dentry *dent; /* For visible tree hierarchy */ #endif + void (*find_idlest)(struct clk_hw_omap *oclk, + void __iomem **idlest_reg, + u8 *idlest_bit, u8 *idlest_val); + void (*find_companion)(struct clk_hw_omap *oclk, + void __iomem **other_reg, u8 *other_bit); + void (*allow_idle)(struct clk_hw_omap *oclk); + void (*deny_idle)(struct clk_hw_omap *oclk); };

struct cpufreq_frequency_table;

-struct clk_functions { - int (*clk_enable)(struct clk *clk); - void (*clk_disable)(struct clk *clk); - long (*clk_round_rate)(struct clk *clk, unsigned long rate); - int (*clk_set_rate)(struct clk *clk, unsigned long rate); - int (*clk_set_parent)(struct clk *clk, struct clk *parent); - void (*clk_allow_idle)(struct clk *clk); - void (*clk_deny_idle)(struct clk *clk); - void (*clk_disable_unused)(struct clk *clk); -#ifdef CONFIG_CPU_FREQ - void (*clk_init_cpufreq_table)(struct cpufreq_frequency_table **); - void (*clk_exit_cpufreq_table)(struct cpufreq_frequency_table **); -#endif -}; - extern int mpurate;

+#if 0 extern int clk_init(struct clk_functions *custom_clocks); extern void clk_preinit(struct clk *clk); -extern int clk_register(struct clk *clk); +/* XXX defined in drivers/clk/clk.h +extern int clk_register(struct clk *clk); */ extern void clk_reparent(struct clk *child, struct clk *parent); -extern void clk_unregister(struct clk *clk); +/* XXX defined in drivers/clk/clk.h +extern void clk_unregister(struct clk *clk);*/ extern void propagate_rate(struct clk *clk); extern void recalculate_root_clocks(void); extern unsigned long followparent_recalc(struct clk *clk); +#endif + +/* + * FIXME add this stuff someday (probably used by DT) + * + * extern int omap_clk_init(struct device *dev, struct clk_hw_omap *oclk); + * extern struct clk_hw_omap *omap_clk_register(struct device *dev, + * const char *name); + */ + extern void clk_enable_init_clocks(void); unsigned long omap_fixed_divisor_recalc(struct clk *clk); #ifdef CONFIG_CPU_FREQ @@ -307,8 +281,10 @@ extern struct clk *omap_clk_get_by_name(const char *name); extern int omap_clk_enable_autoidle_all(void); extern int omap_clk_disable_autoidle_all(void);

-extern const struct clkops clkops_null; +extern struct clk *omap2_get_parent_fixed(struct clk *clk); + +//extern const struct clkops clkops_null;

-extern struct clk dummy_ck; +//extern struct clk *dummy_ck;

#endif

-- 1.7.5.4

Mike Turquette

4:11 a.m.

New subject: [PATCH 3/7] HACK: omap: convert 44xx data to common struct clk

This patch is 100% output from the omap hw data autogeneration scripts, after those scripts were modified to support the common struct clk stuff. No manual edits! It has been boot-tested on an OMAP4 Panda.

Shortcomings:

Doesn't reuse any of the basic clks in drivers/clk/clk-basic.c. This is mostly due to some omap platform clk functions that always expect struct clk to have a clkdm member.

Every clk has it own struct clk_ops defined which is very wasteful. I need to support some clever hashing in the autogen scripts since a huge number of these ops structures are duplicates and should go away.

omap_clk_get_by_name must die.

Still using dummy_clk from plat-omap/clock.c. The new common clk code should provide a stub clk somehow, since I think this is a common problem across platforms.

Not-signed-off-by: Mike Turquette mturquette@ti.com --- arch/arm/mach-omap2/clock44xx_data.c | 4615 ++++++++++++++++++++-------------- 1 files changed, 2750 insertions(+), 1865 deletions(-)

diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index 0798a80..33249b3 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -1,12 +1,13 @@ /* * OMAP4 Clock data * - * Copyright (C) 2009-2010 Texas Instruments, Inc. + * Copyright (C) 2009-2011 Texas Instruments, Inc. * Copyright (C) 2009-2010 Nokia Corporation * * Paul Walmsley (paul@pwsan.com) * Rajendra Nayak (rnayak@ti.com) * Benoit Cousson (b-cousson@ti.com) + * Mike Turquette (mturquette@ti.com) * * This file is automatically generated from the OMAP hardware databases. * We respectfully ask that any modifications to this file be coordinated @@ -39,91 +40,129 @@ #include "scrm44xx.h"

/* OMAP4 modulemode control */ -#define OMAP4430_MODULEMODE_HWCTRL 0 -#define OMAP4430_MODULEMODE_SWCTRL 1 +#define OMAP4430_MODULEMODE_HWCTRL_SHIFT 0 +#define OMAP4430_MODULEMODE_SWCTRL_SHIFT 1 + +/*LIST_HEAD(clocks);*/

/* Root clocks */

-static struct clk extalt_clkin_ck = { - .name = "extalt_clkin_ck", - .rate = 59000000, - .ops = &clkops_null, +static struct clk_hw_ops virt_ck_ops = { + .recalc_rate = &omap2_recalc_rate_fixed, +}; + +static struct clk_hw_ops root_ck_gate_ops = { + .recalc_rate = &omap2_recalc_rate_fixed, + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, +}; + +static struct clk_hw_ops root_ck_ops = { + .recalc_rate = &omap2_recalc_rate_fixed, };

-static struct clk pad_clks_ck = { - .name = "pad_clks_ck", - .rate = 12000000, - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_CLKSEL_ABE, - .enable_bit = OMAP4430_PAD_CLKS_GATE_SHIFT, +static struct clk_hw_omap extalt_clkin_ck_hw = { + .clk = { + .name = "extalt_clkin_ck", + .ops = &root_ck_ops, + }, + .fixed_rate = 59000000, };

-static struct clk pad_slimbus_core_clks_ck = { - .name = "pad_slimbus_core_clks_ck", - .rate = 12000000, - .ops = &clkops_null, +static struct clk_hw_omap pad_clks_ck_hw = { + .clk = { + .name = "pad_clks_ck", + .ops = &root_ck_gate_ops, + }, + .fixed_rate = 12000000, };

-static struct clk secure_32k_clk_src_ck = { - .name = "secure_32k_clk_src_ck", - .rate = 32768, - .ops = &clkops_null, +static struct clk_hw_omap pad_slimbus_core_clks_ck_hw = { + .clk = { + .name = "pad_slimbus_core_clks_ck", + .ops = &root_ck_ops, + }, + .fixed_rate = 12000000, };

-static struct clk slimbus_clk = { - .name = "slimbus_clk", - .rate = 12000000, - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_CLKSEL_ABE, - .enable_bit = OMAP4430_SLIMBUS_CLK_GATE_SHIFT, +static struct clk_hw_omap secure_32k_clk_src_ck_hw = { + .clk = { + .name = "secure_32k_clk_src_ck", + .ops = &root_ck_ops, + }, + .fixed_rate = 32768, };

-static struct clk sys_32k_ck = { - .name = "sys_32k_ck", - .rate = 32768, - .ops = &clkops_null, +static struct clk_hw_omap slimbus_clk_hw = { + .clk = { + .name = "slimbus_clk", + .ops = &root_ck_gate_ops, + }, + .fixed_rate = 12000000, };

-static struct clk virt_12000000_ck = { - .name = "virt_12000000_ck", - .ops = &clkops_null, - .rate = 12000000, +static struct clk_hw_omap sys_32k_ck_hw = { + .clk = { + .name = "sys_32k_ck", + .ops = &root_ck_ops, + }, + .fixed_rate = 32768, };

-static struct clk virt_13000000_ck = { - .name = "virt_13000000_ck", - .ops = &clkops_null, - .rate = 13000000, +static struct clk_hw_omap virt_12000000_ck_hw = { + .clk = { + .name = "virt_12000000_ck", + .ops = &virt_ck_ops, + }, + .fixed_rate = 12000000, };

-static struct clk virt_16800000_ck = { - .name = "virt_16800000_ck", - .ops = &clkops_null, - .rate = 16800000, +static struct clk_hw_omap virt_13000000_ck_hw = { + .clk = { + .name = "virt_13000000_ck", + .ops = &virt_ck_ops, + }, + .fixed_rate = 13000000, };

-static struct clk virt_19200000_ck = { - .name = "virt_19200000_ck", - .ops = &clkops_null, - .rate = 19200000, +static struct clk_hw_omap virt_16800000_ck_hw = { + .clk = { + .name = "virt_16800000_ck", + .ops = &virt_ck_ops, + }, + .fixed_rate = 16800000, };

-static struct clk virt_26000000_ck = { - .name = "virt_26000000_ck", - .ops = &clkops_null, - .rate = 26000000, +static struct clk_hw_omap virt_19200000_ck_hw = { + .clk = { + .name = "virt_19200000_ck", + .ops = &virt_ck_ops, + }, + .fixed_rate = 19200000, };

-static struct clk virt_27000000_ck = { - .name = "virt_27000000_ck", - .ops = &clkops_null, - .rate = 27000000, +static struct clk_hw_omap virt_26000000_ck_hw = { + .clk = { + .name = "virt_26000000_ck", + .ops = &virt_ck_ops, + }, + .fixed_rate = 26000000, };

-static struct clk virt_38400000_ck = { - .name = "virt_38400000_ck", - .ops = &clkops_null, - .rate = 38400000, +static struct clk_hw_omap virt_27000000_ck_hw = { + .clk = { + .name = "virt_27000000_ck", + .ops = &virt_ck_ops, + }, + .fixed_rate = 27000000, +}; + +static struct clk_hw_omap virt_38400000_ck_hw = { + .clk = { + .name = "virt_38400000_ck", + .ops = &virt_ck_ops, + }, + .fixed_rate = 38400000, };

static const struct clksel_rate div_1_0_rates[] = { @@ -167,88 +206,115 @@ static const struct clksel_rate div_1_7_rates[] = { };

static const struct clksel sys_clkin_sel[] = { - { .parent = &virt_12000000_ck, .rates = div_1_1_rates }, - { .parent = &virt_13000000_ck, .rates = div_1_2_rates }, - { .parent = &virt_16800000_ck, .rates = div_1_3_rates }, - { .parent = &virt_19200000_ck, .rates = div_1_4_rates }, - { .parent = &virt_26000000_ck, .rates = div_1_5_rates }, - { .parent = &virt_27000000_ck, .rates = div_1_6_rates }, - { .parent = &virt_38400000_ck, .rates = div_1_7_rates }, + { .parent = &virt_12000000_ck_hw.clk, .rates = div_1_1_rates }, + { .parent = &virt_13000000_ck_hw.clk, .rates = div_1_2_rates }, + { .parent = &virt_16800000_ck_hw.clk, .rates = div_1_3_rates }, + { .parent = &virt_19200000_ck_hw.clk, .rates = div_1_4_rates }, + { .parent = &virt_26000000_ck_hw.clk, .rates = div_1_5_rates }, + { .parent = &virt_27000000_ck_hw.clk, .rates = div_1_6_rates }, + { .parent = &virt_38400000_ck_hw.clk, .rates = div_1_7_rates }, { .parent = NULL }, };

-static struct clk sys_clkin_ck = { - .name = "sys_clkin_ck", - .rate = 38400000, +static const struct clk_hw_ops sys_clkin_ck_ops = { + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_init_clksel_parent, + .set_parent = &omap2_clksel_set_parent, +}; + +static struct clk_hw_omap sys_clkin_ck_hw = { + .clk = { + .name = "sys_clkin_ck", + .ops = &sys_clkin_ck_ops, + }, + .fixed_rate = 38400000, .clksel = sys_clkin_sel, - .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM_SYS_CLKSEL, .clksel_mask = OMAP4430_SYS_CLKSEL_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, };

-static struct clk tie_low_clock_ck = { - .name = "tie_low_clock_ck", - .rate = 0, - .ops = &clkops_null, +static struct clk_hw_omap tie_low_clock_ck_hw = { + .clk = { + .name = "tie_low_clock_ck", + .ops = &root_ck_ops, + }, + .fixed_rate = 0, };

-static struct clk utmi_phy_clkout_ck = { - .name = "utmi_phy_clkout_ck", - .rate = 60000000, - .ops = &clkops_null, +static struct clk_hw_omap utmi_phy_clkout_ck_hw = { + .clk = { + .name = "utmi_phy_clkout_ck", + .ops = &root_ck_ops, + }, + .fixed_rate = 60000000, };

-static struct clk xclk60mhsp1_ck = { - .name = "xclk60mhsp1_ck", - .rate = 60000000, - .ops = &clkops_null, +static struct clk_hw_omap xclk60mhsp1_ck_hw = { + .clk = { + .name = "xclk60mhsp1_ck", + .ops = &root_ck_ops, + }, + .fixed_rate = 60000000, };

-static struct clk xclk60mhsp2_ck = { - .name = "xclk60mhsp2_ck", - .rate = 60000000, - .ops = &clkops_null, +static struct clk_hw_omap xclk60mhsp2_ck_hw = { + .clk = { + .name = "xclk60mhsp2_ck", + .ops = &root_ck_ops, + }, + .fixed_rate = 60000000, };

-static struct clk xclk60motg_ck = { - .name = "xclk60motg_ck", - .rate = 60000000, - .ops = &clkops_null, +static struct clk_hw_omap xclk60motg_ck_hw = { + .clk = { + .name = "xclk60motg_ck", + .ops = &root_ck_ops, + }, + .fixed_rate = 60000000, };

/* Module clocks and DPLL outputs */

static const struct clksel abe_dpll_bypass_clk_mux_sel[] = { - { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, - { .parent = &sys_32k_ck, .rates = div_1_1_rates }, + { .parent = &sys_clkin_ck_hw.clk, .rates = div_1_0_rates }, + { .parent = &sys_32k_ck_hw.clk, .rates = div_1_1_rates }, { .parent = NULL }, };

-static struct clk abe_dpll_bypass_clk_mux_ck = { - .name = "abe_dpll_bypass_clk_mux_ck", - .parent = &sys_clkin_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, +static const struct clk_hw_ops abe_dpll_bypass_clk_mux_ck_ops = { + .get_parent = &omap2_get_parent_fixed, };

-static struct clk abe_dpll_refclk_mux_ck = { - .name = "abe_dpll_refclk_mux_ck", - .parent = &sys_clkin_ck, +static struct clk_hw_omap abe_dpll_bypass_clk_mux_ck_hw = { + .clk = { + .name = "abe_dpll_bypass_clk_mux_ck", + .ops = &abe_dpll_bypass_clk_mux_ck_ops, + }, + .fixed_parent = &sys_clkin_ck_hw.clk, +}; + +static const struct clk_hw_ops abe_dpll_refclk_mux_ck_ops = { + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_init_clksel_parent, + .set_parent = &omap2_clksel_set_parent, +}; + +static struct clk_hw_omap abe_dpll_refclk_mux_ck_hw = { + .clk = { + .name = "abe_dpll_refclk_mux_ck", + .ops = &abe_dpll_refclk_mux_ck_ops, + }, + .fixed_parent = &sys_clkin_ck_hw.clk, .clksel = abe_dpll_bypass_clk_mux_sel, - .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM_ABE_PLL_REF_CLKSEL, .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, };

/* DPLL_ABE */ static struct dpll_data dpll_abe_dd = { .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_ABE, - .clk_bypass = &abe_dpll_bypass_clk_mux_ck, - .clk_ref = &abe_dpll_refclk_mux_ck, + .clk_bypass = &abe_dpll_bypass_clk_mux_ck_hw.clk, + .clk_ref = &abe_dpll_refclk_mux_ck_hw.clk, .control_reg = OMAP4430_CM_CLKMODE_DPLL_ABE, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_ABE, @@ -264,24 +330,41 @@ static struct dpll_data dpll_abe_dd = { };

-static struct clk dpll_abe_ck = { - .name = "dpll_abe_ck", - .parent = &abe_dpll_refclk_mux_ck, - .dpll_data = &dpll_abe_dd, - .init = &omap2_init_dpll_parent, - .ops = &clkops_omap3_noncore_dpll_ops, - .recalc = &omap4_dpll_regm4xen_recalc, - .round_rate = &omap4_dpll_regm4xen_round_rate, +static const struct clk_hw_ops dpll_abe_ck_ops = { + .enable = &omap3_noncore_dpll_enable, + .disable = &omap3_noncore_dpll_disable, + .recalc_rate = &omap3_dpll_recalc, + .round_rate = &omap2_dpll_round_rate, .set_rate = &omap3_noncore_dpll_set_rate, + .get_parent = &omap2_init_dpll_parent, };

-static struct clk dpll_abe_x2_ck = { - .name = "dpll_abe_x2_ck", - .parent = &dpll_abe_ck, - .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE, +static struct clk_hw_omap dpll_abe_ck_hw = { + .clk = { + .name = "dpll_abe_ck", + .ops = &dpll_abe_ck_ops, + }, + .fixed_parent = &abe_dpll_refclk_mux_ck_hw.clk, + .dpll_data = &dpll_abe_dd, + .allow_idle = &omap3_dpll_allow_idle, + .deny_idle = &omap3_dpll_deny_idle, +}; + +static const struct clk_hw_ops dpll_abe_x2_ck_ops = { + .recalc_rate = &omap3_clkoutx2_recalc, + .get_parent = &omap2_get_parent_fixed, +}; + +static struct clk_hw_omap dpll_abe_x2_ck_hw = { + .clk = { + .name = "dpll_abe_x2_ck", + .ops = &dpll_abe_x2_ck_ops, + }, + .fixed_parent = &dpll_abe_ck_hw.clk, .flags = CLOCK_CLKOUTX2, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap3_clkoutx2_recalc, + .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE, + .allow_idle = &omap4_dpllmx_allow_gatectrl, + .deny_idle = &omap4_dpllmx_deny_gatectrl, };

static const struct clksel_rate div31_1to31_rates[] = { @@ -320,28 +403,42 @@ static const struct clksel_rate div31_1to31_rates[] = { };

static const struct clksel dpll_abe_m2x2_div[] = { - { .parent = &dpll_abe_x2_ck, .rates = div31_1to31_rates }, + { .parent = &dpll_abe_x2_ck_hw.clk, .rates = div31_1to31_rates }, { .parent = NULL }, };

-static struct clk dpll_abe_m2x2_ck = { - .name = "dpll_abe_m2x2_ck", - .parent = &dpll_abe_x2_ck, +static const struct clk_hw_ops dpll_abe_m2x2_ck_ops = { + .recalc_rate = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, + .get_parent = &omap2_get_parent_fixed, +}; + +static struct clk_hw_omap dpll_abe_m2x2_ck_hw = { + .clk = { + .name = "dpll_abe_m2x2_ck", + .ops = &dpll_abe_m2x2_ck_ops, + }, + .fixed_parent = &dpll_abe_x2_ck_hw.clk, .clksel = dpll_abe_m2x2_div, .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE, .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, + .allow_idle = &omap4_dpllmx_allow_gatectrl, + .deny_idle = &omap4_dpllmx_deny_gatectrl, +}; + +static const struct clk_hw_ops abe_24m_fclk_ops = { + .recalc_rate = &omap_fixed_divisor_recalc, + .get_parent = &omap2_get_parent_fixed, };

-static struct clk abe_24m_fclk = { - .name = "abe_24m_fclk", - .parent = &dpll_abe_m2x2_ck, - .ops = &clkops_null, - .fixed_div = 8, - .recalc = &omap_fixed_divisor_recalc, +static struct clk_hw_omap abe_24m_fclk_hw = { + .clk = { + .name = "abe_24m_fclk", + .ops = &abe_24m_fclk_ops, + }, + .fixed_parent = &dpll_abe_m2x2_ck_hw.clk, + .fixed_div = 8, };

static const struct clksel_rate div3_1to4_rates[] = { @@ -352,20 +449,26 @@ static const struct clksel_rate div3_1to4_rates[] = { };

static const struct clksel abe_clk_div[] = { - { .parent = &dpll_abe_m2x2_ck, .rates = div3_1to4_rates }, + { .parent = &dpll_abe_m2x2_ck_hw.clk, .rates = div3_1to4_rates }, { .parent = NULL }, };

-static struct clk abe_clk = { - .name = "abe_clk", - .parent = &dpll_abe_m2x2_ck, +static const struct clk_hw_ops abe_clk_ops = { + .recalc_rate = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, + .get_parent = &omap2_get_parent_fixed, +}; + +static struct clk_hw_omap abe_clk_hw = { + .clk = { + .name = "abe_clk", + .ops = &abe_clk_ops, + }, + .fixed_parent = &dpll_abe_m2x2_ck_hw.clk, .clksel = abe_clk_div, .clksel_reg = OMAP4430_CM_CLKSEL_ABE, .clksel_mask = OMAP4430_CLKSEL_OPP_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, };

static const struct clksel_rate div2_1to2_rates[] = { @@ -375,56 +478,76 @@ static const struct clksel_rate div2_1to2_rates[] = { };

static const struct clksel aess_fclk_div[] = { - { .parent = &abe_clk, .rates = div2_1to2_rates }, + { .parent = &abe_clk_hw.clk, .rates = div2_1to2_rates }, { .parent = NULL }, };

-static struct clk aess_fclk = { - .name = "aess_fclk", - .parent = &abe_clk, +static const struct clk_hw_ops aess_fclk_ops = { + .recalc_rate = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, + .get_parent = &omap2_get_parent_fixed, +}; + +static struct clk_hw_omap aess_fclk_hw = { + .clk = { + .name = "aess_fclk", + .ops = &aess_fclk_ops, + }, + .fixed_parent = &abe_clk_hw.clk, .clksel = aess_fclk_div, .clksel_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_AESS_FCLK_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, +}; + +static const struct clk_hw_ops dpll_abe_m3x2_ck_ops = { + .recalc_rate = &omap2_clksel_recalc, .round_rate = &omap2_clksel_round_rate, .set_rate = &omap2_clksel_set_rate, + .get_parent = &omap2_get_parent_fixed, };

-static struct clk dpll_abe_m3x2_ck = { - .name = "dpll_abe_m3x2_ck", - .parent = &dpll_abe_x2_ck, +static struct clk_hw_omap dpll_abe_m3x2_ck_hw = { + .clk = { + .name = "dpll_abe_m3x2_ck", + .ops = &dpll_abe_m3x2_ck_ops, + }, + .fixed_parent = &dpll_abe_x2_ck_hw.clk, .clksel = dpll_abe_m2x2_div, .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_ABE, .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, + .allow_idle = &omap4_dpllmx_allow_gatectrl, + .deny_idle = &omap4_dpllmx_deny_gatectrl, };

static const struct clksel core_hsd_byp_clk_mux_sel[] = { - { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, - { .parent = &dpll_abe_m3x2_ck, .rates = div_1_1_rates }, + { .parent = &sys_clkin_ck_hw.clk, .rates = div_1_0_rates }, + { .parent = &dpll_abe_m3x2_ck_hw.clk, .rates = div_1_1_rates }, { .parent = NULL }, };

-static struct clk core_hsd_byp_clk_mux_ck = { - .name = "core_hsd_byp_clk_mux_ck", - .parent = &sys_clkin_ck, +static const struct clk_hw_ops core_hsd_byp_clk_mux_ck_ops = { + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_init_clksel_parent, + .set_parent = &omap2_clksel_set_parent, +}; + +static struct clk_hw_omap core_hsd_byp_clk_mux_ck_hw = { + .clk = { + .name = "core_hsd_byp_clk_mux_ck", + .ops = &core_hsd_byp_clk_mux_ck_ops, + }, + .fixed_parent = &sys_clkin_ck_hw.clk, .clksel = core_hsd_byp_clk_mux_sel, - .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_CORE, .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, };

/* DPLL_CORE */ static struct dpll_data dpll_core_dd = { .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_CORE, - .clk_bypass = &core_hsd_byp_clk_mux_ck, - .clk_ref = &sys_clkin_ck, + .clk_bypass = &core_hsd_byp_clk_mux_ck_hw.clk, + .clk_ref = &sys_clkin_ck_hw.clk, .control_reg = OMAP4430_CM_CLKMODE_DPLL_CORE, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_CORE, @@ -440,105 +563,158 @@ static struct dpll_data dpll_core_dd = { };

-static struct clk dpll_core_ck = { - .name = "dpll_core_ck", - .parent = &sys_clkin_ck, +static const struct clk_hw_ops dpll_core_ck_ops = { + .recalc_rate = &omap3_dpll_recalc, + .get_parent = &omap2_init_dpll_parent, +}; + +static struct clk_hw_omap dpll_core_ck_hw = { + .clk = { + .name = "dpll_core_ck", + .ops = &dpll_core_ck_ops, + }, + .fixed_parent = &sys_clkin_ck_hw.clk, .dpll_data = &dpll_core_dd, - .init = &omap2_init_dpll_parent, - .ops = &clkops_omap3_core_dpll_ops, - .recalc = &omap3_dpll_recalc, + .allow_idle = &omap3_dpll_allow_idle, + .deny_idle = &omap3_dpll_deny_idle, };

-static struct clk dpll_core_x2_ck = { - .name = "dpll_core_x2_ck", - .parent = &dpll_core_ck, - .flags = CLOCK_CLKOUTX2, - .ops = &clkops_null, - .recalc = &omap3_clkoutx2_recalc, +static const struct clk_hw_ops dpll_core_x2_ck_ops = { + .recalc_rate = &omap3_clkoutx2_recalc, + .get_parent = &omap2_get_parent_fixed, +}; + +static struct clk_hw_omap dpll_core_x2_ck_hw = { + .clk = { + .name = "dpll_core_x2_ck", + .ops = &dpll_core_x2_ck_ops, + }, + .fixed_parent = &dpll_core_ck_hw.clk, };

static const struct clksel dpll_core_m6x2_div[] = { - { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates }, + { .parent = &dpll_core_x2_ck_hw.clk, .rates = div31_1to31_rates }, { .parent = NULL }, };

-static struct clk dpll_core_m6x2_ck = { - .name = "dpll_core_m6x2_ck", - .parent = &dpll_core_x2_ck, +static const struct clk_hw_ops dpll_core_m6x2_ck_ops = { + .recalc_rate = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, + .get_parent = &omap2_get_parent_fixed, +}; + +static struct clk_hw_omap dpll_core_m6x2_ck_hw = { + .clk = { + .name = "dpll_core_m6x2_ck", + .ops = &dpll_core_m6x2_ck_ops, + }, + .fixed_parent = &dpll_core_x2_ck_hw.clk, .clksel = dpll_core_m6x2_div, .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_CORE, .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, + .allow_idle = &omap4_dpllmx_allow_gatectrl, + .deny_idle = &omap4_dpllmx_deny_gatectrl, };

static const struct clksel dbgclk_mux_sel[] = { - { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, - { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates }, + { .parent = &sys_clkin_ck_hw.clk, .rates = div_1_0_rates }, + { .parent = &dpll_core_m6x2_ck_hw.clk, .rates = div_1_1_rates }, { .parent = NULL }, };

-static struct clk dbgclk_mux_ck = { - .name = "dbgclk_mux_ck", - .parent = &sys_clkin_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, +static const struct clk_hw_ops dbgclk_mux_ck_ops = { + .get_parent = &omap2_get_parent_fixed, +}; + +static struct clk_hw_omap dbgclk_mux_ck_hw = { + .clk = { + .name = "dbgclk_mux_ck", + .ops = &dbgclk_mux_ck_ops, + }, + .fixed_parent = &sys_clkin_ck_hw.clk, };

static const struct clksel dpll_core_m2_div[] = { - { .parent = &dpll_core_ck, .rates = div31_1to31_rates }, + { .parent = &dpll_core_ck_hw.clk, .rates = div31_1to31_rates }, { .parent = NULL }, };

-static struct clk dpll_core_m2_ck = { - .name = "dpll_core_m2_ck", - .parent = &dpll_core_ck, +static const struct clk_hw_ops dpll_core_m2_ck_ops = { + .recalc_rate = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, + .get_parent = &omap2_get_parent_fixed, +}; + +static struct clk_hw_omap dpll_core_m2_ck_hw = { + .clk = { + .name = "dpll_core_m2_ck", + .ops = &dpll_core_m2_ck_ops, + }, + .fixed_parent = &dpll_core_ck_hw.clk, .clksel = dpll_core_m2_div, .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_CORE, .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, + .allow_idle = &omap4_dpllmx_allow_gatectrl, + .deny_idle = &omap4_dpllmx_deny_gatectrl, };

-static struct clk ddrphy_ck = { - .name = "ddrphy_ck", - .parent = &dpll_core_m2_ck, - .ops = &clkops_null, - .fixed_div = 2, - .recalc = &omap_fixed_divisor_recalc, +static const struct clk_hw_ops ddrphy_ck_ops = { + .recalc_rate = &omap_fixed_divisor_recalc, + .get_parent = &omap2_get_parent_fixed, };

-static struct clk dpll_core_m5x2_ck = { - .name = "dpll_core_m5x2_ck", - .parent = &dpll_core_x2_ck, +static struct clk_hw_omap ddrphy_ck_hw = { + .clk = { + .name = "ddrphy_ck", + .ops = &ddrphy_ck_ops, + }, + .fixed_parent = &dpll_core_m2_ck_hw.clk, + .fixed_div = 2, +}; + +static const struct clk_hw_ops dpll_core_m5x2_ck_ops = { + .recalc_rate = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, + .get_parent = &omap2_get_parent_fixed, +}; + +static struct clk_hw_omap dpll_core_m5x2_ck_hw = { + .clk = { + .name = "dpll_core_m5x2_ck", + .ops = &dpll_core_m5x2_ck_ops, + }, + .fixed_parent = &dpll_core_x2_ck_hw.clk, .clksel = dpll_core_m6x2_div, .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_CORE, .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, + .allow_idle = &omap4_dpllmx_allow_gatectrl, + .deny_idle = &omap4_dpllmx_deny_gatectrl, };

static const struct clksel div_core_div[] = { - { .parent = &dpll_core_m5x2_ck, .rates = div2_1to2_rates }, + { .parent = &dpll_core_m5x2_ck_hw.clk, .rates = div2_1to2_rates }, { .parent = NULL }, };

-static struct clk div_core_ck = { - .name = "div_core_ck", - .parent = &dpll_core_m5x2_ck, +static const struct clk_hw_ops div_core_ck_ops = { + .recalc_rate = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, + .get_parent = &omap2_get_parent_fixed, +}; + +static struct clk_hw_omap div_core_ck_hw = { + .clk = { + .name = "div_core_ck", + .ops = &div_core_ck_ops, + }, + .fixed_parent = &dpll_core_m5x2_ck_hw.clk, .clksel = div_core_div, .clksel_reg = OMAP4430_CM_CLKSEL_CORE, .clksel_mask = OMAP4430_CLKSEL_CORE_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, };

static const struct clksel_rate div4_1to8_rates[] = { @@ -550,119 +726,175 @@ static const struct clksel_rate div4_1to8_rates[] = { };

static const struct clksel div_iva_hs_clk_div[] = { - { .parent = &dpll_core_m5x2_ck, .rates = div4_1to8_rates }, + { .parent = &dpll_core_m5x2_ck_hw.clk, .rates = div4_1to8_rates }, { .parent = NULL }, };

-static struct clk div_iva_hs_clk = { - .name = "div_iva_hs_clk", - .parent = &dpll_core_m5x2_ck, +static const struct clk_hw_ops div_iva_hs_clk_ops = { + .recalc_rate = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, + .get_parent = &omap2_get_parent_fixed, +}; + +static struct clk_hw_omap div_iva_hs_clk_hw = { + .clk = { + .name = "div_iva_hs_clk", + .ops = &div_iva_hs_clk_ops, + }, + .fixed_parent = &dpll_core_m5x2_ck_hw.clk, .clksel = div_iva_hs_clk_div, .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_IVA, .clksel_mask = OMAP4430_CLKSEL_0_1_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, +}; + +static const struct clk_hw_ops div_mpu_hs_clk_ops = { + .recalc_rate = &omap2_clksel_recalc, .round_rate = &omap2_clksel_round_rate, .set_rate = &omap2_clksel_set_rate, + .get_parent = &omap2_get_parent_fixed, };

-static struct clk div_mpu_hs_clk = { - .name = "div_mpu_hs_clk", - .parent = &dpll_core_m5x2_ck, +static struct clk_hw_omap div_mpu_hs_clk_hw = { + .clk = { + .name = "div_mpu_hs_clk", + .ops = &div_mpu_hs_clk_ops, + }, + .fixed_parent = &dpll_core_m5x2_ck_hw.clk, .clksel = div_iva_hs_clk_div, .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_MPU, .clksel_mask = OMAP4430_CLKSEL_0_1_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, +}; + +static const struct clk_hw_ops dpll_core_m4x2_ck_ops = { + .recalc_rate = &omap2_clksel_recalc, .round_rate = &omap2_clksel_round_rate, .set_rate = &omap2_clksel_set_rate, + .get_parent = &omap2_get_parent_fixed, };

-static struct clk dpll_core_m4x2_ck = { - .name = "dpll_core_m4x2_ck", - .parent = &dpll_core_x2_ck, +static struct clk_hw_omap dpll_core_m4x2_ck_hw = { + .clk = { + .name = "dpll_core_m4x2_ck", + .ops = &dpll_core_m4x2_ck_ops, + }, + .fixed_parent = &dpll_core_x2_ck_hw.clk, .clksel = dpll_core_m6x2_div, .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_CORE, .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, + .allow_idle = &omap4_dpllmx_allow_gatectrl, + .deny_idle = &omap4_dpllmx_deny_gatectrl, +}; + +static const struct clk_hw_ops dll_clk_div_ck_ops = { + .recalc_rate = &omap_fixed_divisor_recalc, + .get_parent = &omap2_get_parent_fixed, };

-static struct clk dll_clk_div_ck = { - .name = "dll_clk_div_ck", - .parent = &dpll_core_m4x2_ck, - .ops = &clkops_null, - .fixed_div = 2, - .recalc = &omap_fixed_divisor_recalc, +static struct clk_hw_omap dll_clk_div_ck_hw = { + .clk = { + .name = "dll_clk_div_ck", + .ops = &dll_clk_div_ck_ops, + }, + .fixed_parent = &dpll_core_m4x2_ck_hw.clk, + .fixed_div = 2, };

static const struct clksel dpll_abe_m2_div[] = { - { .parent = &dpll_abe_ck, .rates = div31_1to31_rates }, + { .parent = &dpll_abe_ck_hw.clk, .rates = div31_1to31_rates }, { .parent = NULL }, };

-static struct clk dpll_abe_m2_ck = { - .name = "dpll_abe_m2_ck", - .parent = &dpll_abe_ck, +static const struct clk_hw_ops dpll_abe_m2_ck_ops = { + .recalc_rate = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, + .get_parent = &omap2_get_parent_fixed, +}; + +static struct clk_hw_omap dpll_abe_m2_ck_hw = { + .clk = { + .name = "dpll_abe_m2_ck", + .ops = &dpll_abe_m2_ck_ops, + }, + .fixed_parent = &dpll_abe_ck_hw.clk, .clksel = dpll_abe_m2_div, .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE, .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, + .allow_idle = &omap4_dpllmx_allow_gatectrl, + .deny_idle = &omap4_dpllmx_deny_gatectrl, +}; + +static const struct clk_hw_ops dpll_core_m3x2_ck_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .recalc_rate = &omap2_clksel_recalc, .round_rate = &omap2_clksel_round_rate, .set_rate = &omap2_clksel_set_rate, + .get_parent = &omap2_get_parent_fixed, };

-static struct clk dpll_core_m3x2_ck = { - .name = "dpll_core_m3x2_ck", - .parent = &dpll_core_x2_ck, +static struct clk_hw_omap dpll_core_m3x2_ck_hw = { + .clk = { + .name = "dpll_core_m3x2_ck", + .ops = &dpll_core_m3x2_ck_ops, + }, + .fixed_parent = &dpll_core_x2_ck_hw.clk, + .enable_reg = OMAP4430_CM_DIV_M3_DPLL_CORE, + .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, .clksel = dpll_core_m6x2_div, .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_CORE, .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, +}; + +static const struct clk_hw_ops dpll_core_m7x2_ck_ops = { + .recalc_rate = &omap2_clksel_recalc, .round_rate = &omap2_clksel_round_rate, .set_rate = &omap2_clksel_set_rate, - .enable_reg = OMAP4430_CM_DIV_M3_DPLL_CORE, - .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, + .get_parent = &omap2_get_parent_fixed, };

-static struct clk dpll_core_m7x2_ck = { - .name = "dpll_core_m7x2_ck", - .parent = &dpll_core_x2_ck, +static struct clk_hw_omap dpll_core_m7x2_ck_hw = { + .clk = { + .name = "dpll_core_m7x2_ck", + .ops = &dpll_core_m7x2_ck_ops, + }, + .fixed_parent = &dpll_core_x2_ck_hw.clk, .clksel = dpll_core_m6x2_div, .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_CORE, .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, + .allow_idle = &omap4_dpllmx_allow_gatectrl, + .deny_idle = &omap4_dpllmx_deny_gatectrl, };

static const struct clksel iva_hsd_byp_clk_mux_sel[] = { - { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, - { .parent = &div_iva_hs_clk, .rates = div_1_1_rates }, + { .parent = &sys_clkin_ck_hw.clk, .rates = div_1_0_rates }, + { .parent = &div_iva_hs_clk_hw.clk, .rates = div_1_1_rates }, { .parent = NULL }, };

-static struct clk iva_hsd_byp_clk_mux_ck = { - .name = "iva_hsd_byp_clk_mux_ck", - .parent = &sys_clkin_ck, +static const struct clk_hw_ops iva_hsd_byp_clk_mux_ck_ops = { + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_init_clksel_parent, + .set_parent = &omap2_clksel_set_parent, +}; + +static struct clk_hw_omap iva_hsd_byp_clk_mux_ck_hw = { + .clk = { + .name = "iva_hsd_byp_clk_mux_ck", + .ops = &iva_hsd_byp_clk_mux_ck_ops, + }, + .fixed_parent = &sys_clkin_ck_hw.clk, .clksel = iva_hsd_byp_clk_mux_sel, - .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_IVA, .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, };

/* DPLL_IVA */ static struct dpll_data dpll_iva_dd = { .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_IVA, - .clk_bypass = &iva_hsd_byp_clk_mux_ck, - .clk_ref = &sys_clkin_ck, + .clk_bypass = &iva_hsd_byp_clk_mux_ck_hw.clk, + .clk_ref = &sys_clkin_ck_hw.clk, .control_reg = OMAP4430_CM_CLKMODE_DPLL_IVA, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_IVA, @@ -678,59 +910,89 @@ static struct dpll_data dpll_iva_dd = { };

-static struct clk dpll_iva_ck = { - .name = "dpll_iva_ck", - .parent = &sys_clkin_ck, - .dpll_data = &dpll_iva_dd, - .init = &omap2_init_dpll_parent, - .ops = &clkops_omap3_noncore_dpll_ops, - .recalc = &omap3_dpll_recalc, +static const struct clk_hw_ops dpll_iva_ck_ops = { + .enable = &omap3_noncore_dpll_enable, + .disable = &omap3_noncore_dpll_disable, + .recalc_rate = &omap3_dpll_recalc, .round_rate = &omap2_dpll_round_rate, .set_rate = &omap3_noncore_dpll_set_rate, + .get_parent = &omap2_init_dpll_parent, };

-static struct clk dpll_iva_x2_ck = { - .name = "dpll_iva_x2_ck", - .parent = &dpll_iva_ck, - .flags = CLOCK_CLKOUTX2, - .ops = &clkops_null, - .recalc = &omap3_clkoutx2_recalc, +static struct clk_hw_omap dpll_iva_ck_hw = { + .clk = { + .name = "dpll_iva_ck", + .ops = &dpll_iva_ck_ops, + }, + .fixed_parent = &sys_clkin_ck_hw.clk, + .dpll_data = &dpll_iva_dd, + .allow_idle = &omap3_dpll_allow_idle, + .deny_idle = &omap3_dpll_deny_idle, +}; + +static const struct clk_hw_ops dpll_iva_x2_ck_ops = { + .recalc_rate = &omap3_clkoutx2_recalc, + .get_parent = &omap2_get_parent_fixed, +}; + +static struct clk_hw_omap dpll_iva_x2_ck_hw = { + .clk = { + .name = "dpll_iva_x2_ck", + .ops = &dpll_iva_x2_ck_ops, + }, + .fixed_parent = &dpll_iva_ck_hw.clk, };

static const struct clksel dpll_iva_m4x2_div[] = { - { .parent = &dpll_iva_x2_ck, .rates = div31_1to31_rates }, + { .parent = &dpll_iva_x2_ck_hw.clk, .rates = div31_1to31_rates }, { .parent = NULL }, };

-static struct clk dpll_iva_m4x2_ck = { - .name = "dpll_iva_m4x2_ck", - .parent = &dpll_iva_x2_ck, +static const struct clk_hw_ops dpll_iva_m4x2_ck_ops = { + .recalc_rate = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, + .get_parent = &omap2_get_parent_fixed, +}; + +static struct clk_hw_omap dpll_iva_m4x2_ck_hw = { + .clk = { + .name = "dpll_iva_m4x2_ck", + .ops = &dpll_iva_m4x2_ck_ops, + }, + .fixed_parent = &dpll_iva_x2_ck_hw.clk, .clksel = dpll_iva_m4x2_div, .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_IVA, .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, + .allow_idle = &omap4_dpllmx_allow_gatectrl, + .deny_idle = &omap4_dpllmx_deny_gatectrl, +}; + +static const struct clk_hw_ops dpll_iva_m5x2_ck_ops = { + .recalc_rate = &omap2_clksel_recalc, .round_rate = &omap2_clksel_round_rate, .set_rate = &omap2_clksel_set_rate, + .get_parent = &omap2_get_parent_fixed, };

-static struct clk dpll_iva_m5x2_ck = { - .name = "dpll_iva_m5x2_ck", - .parent = &dpll_iva_x2_ck, +static struct clk_hw_omap dpll_iva_m5x2_ck_hw = { + .clk = { + .name = "dpll_iva_m5x2_ck", + .ops = &dpll_iva_m5x2_ck_ops, + }, + .fixed_parent = &dpll_iva_x2_ck_hw.clk, .clksel = dpll_iva_m4x2_div, .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_IVA, .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, + .allow_idle = &omap4_dpllmx_allow_gatectrl, + .deny_idle = &omap4_dpllmx_deny_gatectrl, };

/* DPLL_MPU */ static struct dpll_data dpll_mpu_dd = { .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_MPU, - .clk_bypass = &div_mpu_hs_clk, - .clk_ref = &sys_clkin_ck, + .clk_bypass = &div_mpu_hs_clk_hw.clk, + .clk_ref = &sys_clkin_ck_hw.clk, .control_reg = OMAP4430_CM_CLKMODE_DPLL_MPU, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_MPU, @@ -746,64 +1008,93 @@ static struct dpll_data dpll_mpu_dd = { };

-static struct clk dpll_mpu_ck = { - .name = "dpll_mpu_ck", - .parent = &sys_clkin_ck, - .dpll_data = &dpll_mpu_dd, - .init = &omap2_init_dpll_parent, - .ops = &clkops_omap3_noncore_dpll_ops, - .recalc = &omap3_dpll_recalc, +static const struct clk_hw_ops dpll_mpu_ck_ops = { + .enable = &omap3_noncore_dpll_enable, + .disable = &omap3_noncore_dpll_disable, + .recalc_rate = &omap3_dpll_recalc, .round_rate = &omap2_dpll_round_rate, .set_rate = &omap3_noncore_dpll_set_rate, + .get_parent = &omap2_init_dpll_parent, +}; + +static struct clk_hw_omap dpll_mpu_ck_hw = { + .clk = { + .name = "dpll_mpu_ck", + .ops = &dpll_mpu_ck_ops, + }, + .fixed_parent = &sys_clkin_ck_hw.clk, + .dpll_data = &dpll_mpu_dd, + .allow_idle = &omap3_dpll_allow_idle, + .deny_idle = &omap3_dpll_deny_idle, };

static const struct clksel dpll_mpu_m2_div[] = { - { .parent = &dpll_mpu_ck, .rates = div31_1to31_rates }, + { .parent = &dpll_mpu_ck_hw.clk, .rates = div31_1to31_rates }, { .parent = NULL }, };

-static struct clk dpll_mpu_m2_ck = { - .name = "dpll_mpu_m2_ck", - .parent = &dpll_mpu_ck, +static const struct clk_hw_ops dpll_mpu_m2_ck_ops = { + .recalc_rate = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, + .get_parent = &omap2_get_parent_fixed, +}; + +static struct clk_hw_omap dpll_mpu_m2_ck_hw = { + .clk = { + .name = "dpll_mpu_m2_ck", + .ops = &dpll_mpu_m2_ck_ops, + }, + .fixed_parent = &dpll_mpu_ck_hw.clk, .clksel = dpll_mpu_m2_div, .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_MPU, .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, + .allow_idle = &omap4_dpllmx_allow_gatectrl, + .deny_idle = &omap4_dpllmx_deny_gatectrl, +}; + +static const struct clk_hw_ops per_hs_clk_div_ck_ops = { + .recalc_rate = &omap_fixed_divisor_recalc, + .get_parent = &omap2_get_parent_fixed, };

-static struct clk per_hs_clk_div_ck = { - .name = "per_hs_clk_div_ck", - .parent = &dpll_abe_m3x2_ck, - .ops = &clkops_null, - .fixed_div = 2, - .recalc = &omap_fixed_divisor_recalc, +static struct clk_hw_omap per_hs_clk_div_ck_hw = { + .clk = { + .name = "per_hs_clk_div_ck", + .ops = &per_hs_clk_div_ck_ops, + }, + .fixed_parent = &dpll_abe_m3x2_ck_hw.clk, + .fixed_div = 2, };

static const struct clksel per_hsd_byp_clk_mux_sel[] = { - { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, - { .parent = &per_hs_clk_div_ck, .rates = div_1_1_rates }, + { .parent = &sys_clkin_ck_hw.clk, .rates = div_1_0_rates }, + { .parent = &per_hs_clk_div_ck_hw.clk, .rates = div_1_1_rates }, { .parent = NULL }, };

-static struct clk per_hsd_byp_clk_mux_ck = { - .name = "per_hsd_byp_clk_mux_ck", - .parent = &sys_clkin_ck, +static const struct clk_hw_ops per_hsd_byp_clk_mux_ck_ops = { + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_init_clksel_parent, + .set_parent = &omap2_clksel_set_parent, +}; + +static struct clk_hw_omap per_hsd_byp_clk_mux_ck_hw = { + .clk = { + .name = "per_hsd_byp_clk_mux_ck", + .ops = &per_hsd_byp_clk_mux_ck_ops, + }, + .fixed_parent = &sys_clkin_ck_hw.clk, .clksel = per_hsd_byp_clk_mux_sel, - .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_PER, .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, };

/* DPLL_PER */ static struct dpll_data dpll_per_dd = { .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_PER, - .clk_bypass = &per_hsd_byp_clk_mux_ck, - .clk_ref = &sys_clkin_ck, + .clk_bypass = &per_hsd_byp_clk_mux_ck_hw.clk, + .clk_ref = &sys_clkin_ck_hw.clk, .control_reg = OMAP4430_CM_CLKMODE_DPLL_PER, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_PER, @@ -819,136 +1110,215 @@ static struct dpll_data dpll_per_dd = { };

-static struct clk dpll_per_ck = { - .name = "dpll_per_ck", - .parent = &sys_clkin_ck, - .dpll_data = &dpll_per_dd, - .init = &omap2_init_dpll_parent, - .ops = &clkops_omap3_noncore_dpll_ops, - .recalc = &omap3_dpll_recalc, +static const struct clk_hw_ops dpll_per_ck_ops = { + .enable = &omap3_noncore_dpll_enable, + .disable = &omap3_noncore_dpll_disable, + .recalc_rate = &omap3_dpll_recalc, .round_rate = &omap2_dpll_round_rate, .set_rate = &omap3_noncore_dpll_set_rate, + .get_parent = &omap2_init_dpll_parent, +}; + +static struct clk_hw_omap dpll_per_ck_hw = { + .clk = { + .name = "dpll_per_ck", + .ops = &dpll_per_ck_ops, + }, + .fixed_parent = &sys_clkin_ck_hw.clk, + .dpll_data = &dpll_per_dd, + .allow_idle = &omap3_dpll_allow_idle, + .deny_idle = &omap3_dpll_deny_idle, };

static const struct clksel dpll_per_m2_div[] = { - { .parent = &dpll_per_ck, .rates = div31_1to31_rates }, + { .parent = &dpll_per_ck_hw.clk, .rates = div31_1to31_rates }, { .parent = NULL }, };

-static struct clk dpll_per_m2_ck = { - .name = "dpll_per_m2_ck", - .parent = &dpll_per_ck, - .clksel = dpll_per_m2_div, - .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER, - .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, +static const struct clk_hw_ops dpll_per_m2_ck_ops = { + .recalc_rate = &omap2_clksel_recalc, .round_rate = &omap2_clksel_round_rate, .set_rate = &omap2_clksel_set_rate, + .get_parent = &omap2_get_parent_fixed, };

-static struct clk dpll_per_x2_ck = { - .name = "dpll_per_x2_ck", - .parent = &dpll_per_ck, +static struct clk_hw_omap dpll_per_m2_ck_hw = { + .clk = { + .name = "dpll_per_m2_ck", + .ops = &dpll_per_m2_ck_ops, + }, + .fixed_parent = &dpll_per_ck_hw.clk, + .clksel = dpll_per_m2_div, .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER, + .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, + .allow_idle = &omap4_dpllmx_allow_gatectrl, + .deny_idle = &omap4_dpllmx_deny_gatectrl, +}; + +static const struct clk_hw_ops dpll_per_x2_ck_ops = { + .recalc_rate = &omap3_clkoutx2_recalc, + .get_parent = &omap2_get_parent_fixed, +}; + +static struct clk_hw_omap dpll_per_x2_ck_hw = { + .clk = { + .name = "dpll_per_x2_ck", + .ops = &dpll_per_x2_ck_ops, + }, + .fixed_parent = &dpll_per_ck_hw.clk, .flags = CLOCK_CLKOUTX2, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap3_clkoutx2_recalc, + .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER, + .allow_idle = &omap4_dpllmx_allow_gatectrl, + .deny_idle = &omap4_dpllmx_deny_gatectrl, };

static const struct clksel dpll_per_m2x2_div[] = { - { .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates }, + { .parent = &dpll_per_x2_ck_hw.clk, .rates = div31_1to31_rates }, { .parent = NULL }, };

-static struct clk dpll_per_m2x2_ck = { - .name = "dpll_per_m2x2_ck", - .parent = &dpll_per_x2_ck, +static const struct clk_hw_ops dpll_per_m2x2_ck_ops = { + .recalc_rate = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, + .get_parent = &omap2_get_parent_fixed, +}; + +static struct clk_hw_omap dpll_per_m2x2_ck_hw = { + .clk = { + .name = "dpll_per_m2x2_ck", + .ops = &dpll_per_m2x2_ck_ops, + }, + .fixed_parent = &dpll_per_x2_ck_hw.clk, .clksel = dpll_per_m2x2_div, .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER, .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, + .allow_idle = &omap4_dpllmx_allow_gatectrl, + .deny_idle = &omap4_dpllmx_deny_gatectrl, +}; + +static const struct clk_hw_ops dpll_per_m3x2_ck_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .recalc_rate = &omap2_clksel_recalc, .round_rate = &omap2_clksel_round_rate, .set_rate = &omap2_clksel_set_rate, + .get_parent = &omap2_get_parent_fixed, };

-static struct clk dpll_per_m3x2_ck = { - .name = "dpll_per_m3x2_ck", - .parent = &dpll_per_x2_ck, +static struct clk_hw_omap dpll_per_m3x2_ck_hw = { + .clk = { + .name = "dpll_per_m3x2_ck", + .ops = &dpll_per_m3x2_ck_ops, + }, + .fixed_parent = &dpll_per_x2_ck_hw.clk, + .enable_reg = OMAP4430_CM_DIV_M3_DPLL_PER, + .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, .clksel = dpll_per_m2x2_div, .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_PER, .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, +}; + +static const struct clk_hw_ops dpll_per_m4x2_ck_ops = { + .recalc_rate = &omap2_clksel_recalc, .round_rate = &omap2_clksel_round_rate, .set_rate = &omap2_clksel_set_rate, - .enable_reg = OMAP4430_CM_DIV_M3_DPLL_PER, - .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, + .get_parent = &omap2_get_parent_fixed, };

-static struct clk dpll_per_m4x2_ck = { - .name = "dpll_per_m4x2_ck", - .parent = &dpll_per_x2_ck, +static struct clk_hw_omap dpll_per_m4x2_ck_hw = { + .clk = { + .name = "dpll_per_m4x2_ck", + .ops = &dpll_per_m4x2_ck_ops, + }, + .fixed_parent = &dpll_per_x2_ck_hw.clk, .clksel = dpll_per_m2x2_div, .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_PER, .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, + .allow_idle = &omap4_dpllmx_allow_gatectrl, + .deny_idle = &omap4_dpllmx_deny_gatectrl, +}; + +static const struct clk_hw_ops dpll_per_m5x2_ck_ops = { + .recalc_rate = &omap2_clksel_recalc, .round_rate = &omap2_clksel_round_rate, .set_rate = &omap2_clksel_set_rate, + .get_parent = &omap2_get_parent_fixed, };

-static struct clk dpll_per_m5x2_ck = { - .name = "dpll_per_m5x2_ck", - .parent = &dpll_per_x2_ck, +static struct clk_hw_omap dpll_per_m5x2_ck_hw = { + .clk = { + .name = "dpll_per_m5x2_ck", + .ops = &dpll_per_m5x2_ck_ops, + }, + .fixed_parent = &dpll_per_x2_ck_hw.clk, .clksel = dpll_per_m2x2_div, .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_PER, .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, + .allow_idle = &omap4_dpllmx_allow_gatectrl, + .deny_idle = &omap4_dpllmx_deny_gatectrl, +}; + +static const struct clk_hw_ops dpll_per_m6x2_ck_ops = { + .recalc_rate = &omap2_clksel_recalc, .round_rate = &omap2_clksel_round_rate, .set_rate = &omap2_clksel_set_rate, + .get_parent = &omap2_get_parent_fixed, };

-static struct clk dpll_per_m6x2_ck = { - .name = "dpll_per_m6x2_ck", - .parent = &dpll_per_x2_ck, +static struct clk_hw_omap dpll_per_m6x2_ck_hw = { + .clk = { + .name = "dpll_per_m6x2_ck", + .ops = &dpll_per_m6x2_ck_ops, + }, + .fixed_parent = &dpll_per_x2_ck_hw.clk, .clksel = dpll_per_m2x2_div, .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_PER, .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, + .allow_idle = &omap4_dpllmx_allow_gatectrl, + .deny_idle = &omap4_dpllmx_deny_gatectrl, +}; + +static const struct clk_hw_ops dpll_per_m7x2_ck_ops = { + .recalc_rate = &omap2_clksel_recalc, .round_rate = &omap2_clksel_round_rate, .set_rate = &omap2_clksel_set_rate, + .get_parent = &omap2_get_parent_fixed, };

-static struct clk dpll_per_m7x2_ck = { - .name = "dpll_per_m7x2_ck", - .parent = &dpll_per_x2_ck, +static struct clk_hw_omap dpll_per_m7x2_ck_hw = { + .clk = { + .name = "dpll_per_m7x2_ck", + .ops = &dpll_per_m7x2_ck_ops, + }, + .fixed_parent = &dpll_per_x2_ck_hw.clk, .clksel = dpll_per_m2x2_div, .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_PER, .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, + .allow_idle = &omap4_dpllmx_allow_gatectrl, + .deny_idle = &omap4_dpllmx_deny_gatectrl, +}; + +static const struct clk_hw_ops usb_hs_clk_div_ck_ops = { + .recalc_rate = &omap_fixed_divisor_recalc, + .get_parent = &omap2_get_parent_fixed, };

-static struct clk usb_hs_clk_div_ck = { - .name = "usb_hs_clk_div_ck", - .parent = &dpll_abe_m3x2_ck, - .ops = &clkops_null, - .fixed_div = 3, - .recalc = &omap_fixed_divisor_recalc, +static struct clk_hw_omap usb_hs_clk_div_ck_hw = { + .clk = { + .name = "usb_hs_clk_div_ck", + .ops = &usb_hs_clk_div_ck_ops, + }, + .fixed_parent = &dpll_abe_m3x2_ck_hw.clk, + .fixed_div = 3, };

/* DPLL_USB */ static struct dpll_data dpll_usb_dd = { .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_USB, - .clk_bypass = &usb_hs_clk_div_ck, + .clk_bypass = &usb_hs_clk_div_ck_hw.clk, .flags = DPLL_J_TYPE, - .clk_ref = &sys_clkin_ck, + .clk_ref = &sys_clkin_ck_hw.clk, .control_reg = OMAP4430_CM_CLKMODE_DPLL_USB, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_USB, @@ -965,81 +1335,129 @@ static struct dpll_data dpll_usb_dd = { };

-static struct clk dpll_usb_ck = { - .name = "dpll_usb_ck", - .parent = &sys_clkin_ck, - .dpll_data = &dpll_usb_dd, - .init = &omap2_init_dpll_parent, - .ops = &clkops_omap3_noncore_dpll_ops, - .recalc = &omap3_dpll_recalc, +static const struct clk_hw_ops dpll_usb_ck_ops = { + .enable = &omap3_noncore_dpll_enable, + .disable = &omap3_noncore_dpll_disable, + .recalc_rate = &omap3_dpll_recalc, .round_rate = &omap2_dpll_round_rate, .set_rate = &omap3_noncore_dpll_set_rate, + .get_parent = &omap2_init_dpll_parent, +}; + +static struct clk_hw_omap dpll_usb_ck_hw = { + .clk = { + .name = "dpll_usb_ck", + .ops = &dpll_usb_ck_ops, + }, + .fixed_parent = &sys_clkin_ck_hw.clk, + .dpll_data = &dpll_usb_dd, + .allow_idle = &omap3_dpll_allow_idle, + .deny_idle = &omap3_dpll_deny_idle, };

-static struct clk dpll_usb_clkdcoldo_ck = { - .name = "dpll_usb_clkdcoldo_ck", - .parent = &dpll_usb_ck, +static const struct clk_hw_ops dpll_usb_clkdcoldo_ck_ops = { + .get_parent = &omap2_get_parent_fixed, +}; + +static struct clk_hw_omap dpll_usb_clkdcoldo_ck_hw = { + .clk = { + .name = "dpll_usb_clkdcoldo_ck", + .ops = &dpll_usb_clkdcoldo_ck_ops, + }, + .fixed_parent = &dpll_usb_ck_hw.clk, .clksel_reg = OMAP4430_CM_CLKDCOLDO_DPLL_USB, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &followparent_recalc, + .allow_idle = &omap4_dpllmx_allow_gatectrl, + .deny_idle = &omap4_dpllmx_deny_gatectrl, };

static const struct clksel dpll_usb_m2_div[] = { - { .parent = &dpll_usb_ck, .rates = div31_1to31_rates }, + { .parent = &dpll_usb_ck_hw.clk, .rates = div31_1to31_rates }, { .parent = NULL }, };

-static struct clk dpll_usb_m2_ck = { - .name = "dpll_usb_m2_ck", - .parent = &dpll_usb_ck, +static const struct clk_hw_ops dpll_usb_m2_ck_ops = { + .recalc_rate = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, + .get_parent = &omap2_get_parent_fixed, +}; + +static struct clk_hw_omap dpll_usb_m2_ck_hw = { + .clk = { + .name = "dpll_usb_m2_ck", + .ops = &dpll_usb_m2_ck_ops, + }, + .fixed_parent = &dpll_usb_ck_hw.clk, .clksel = dpll_usb_m2_div, .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_USB, .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, + .allow_idle = &omap4_dpllmx_allow_gatectrl, + .deny_idle = &omap4_dpllmx_deny_gatectrl, };

static const struct clksel ducati_clk_mux_sel[] = { - { .parent = &div_core_ck, .rates = div_1_0_rates }, - { .parent = &dpll_per_m6x2_ck, .rates = div_1_1_rates }, + { .parent = &div_core_ck_hw.clk, .rates = div_1_0_rates }, + { .parent = &dpll_per_m6x2_ck_hw.clk, .rates = div_1_1_rates }, { .parent = NULL }, };

-static struct clk ducati_clk_mux_ck = { - .name = "ducati_clk_mux_ck", - .parent = &div_core_ck, +static const struct clk_hw_ops ducati_clk_mux_ck_ops = { + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_init_clksel_parent, + .set_parent = &omap2_clksel_set_parent, +}; + +static struct clk_hw_omap ducati_clk_mux_ck_hw = { + .clk = { + .name = "ducati_clk_mux_ck", + .ops = &ducati_clk_mux_ck_ops, + }, + .fixed_parent = &div_core_ck_hw.clk, .clksel = ducati_clk_mux_sel, - .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT, .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, };

-static struct clk func_12m_fclk = { - .name = "func_12m_fclk", - .parent = &dpll_per_m2x2_ck, - .ops = &clkops_null, - .fixed_div = 16, - .recalc = &omap_fixed_divisor_recalc, +static const struct clk_hw_ops func_12m_fclk_ops = { + .recalc_rate = &omap_fixed_divisor_recalc, + .get_parent = &omap2_get_parent_fixed, +}; + +static struct clk_hw_omap func_12m_fclk_hw = { + .clk = { + .name = "func_12m_fclk", + .ops = &func_12m_fclk_ops, + }, + .fixed_parent = &dpll_per_m2x2_ck_hw.clk, + .fixed_div = 16, };

-static struct clk func_24m_clk = { - .name = "func_24m_clk", - .parent = &dpll_per_m2_ck, - .ops = &clkops_null, - .fixed_div = 4, - .recalc = &omap_fixed_divisor_recalc, +static const struct clk_hw_ops func_24m_clk_ops = { + .recalc_rate = &omap_fixed_divisor_recalc, + .get_parent = &omap2_get_parent_fixed, };

-static struct clk func_24mc_fclk = { - .name = "func_24mc_fclk", - .parent = &dpll_per_m2x2_ck, - .ops = &clkops_null, - .fixed_div = 8, - .recalc = &omap_fixed_divisor_recalc, +static struct clk_hw_omap func_24m_clk_hw = { + .clk = { + .name = "func_24m_clk", + .ops = &func_24m_clk_ops, + }, + .fixed_parent = &dpll_per_m2_ck_hw.clk, + .fixed_div = 4, +}; + +static const struct clk_hw_ops func_24mc_fclk_ops = { + .recalc_rate = &omap_fixed_divisor_recalc, + .get_parent = &omap2_get_parent_fixed, +}; + +static struct clk_hw_omap func_24mc_fclk_hw = { + .clk = { + .name = "func_24mc_fclk", + .ops = &func_24mc_fclk_ops, + }, + .fixed_parent = &dpll_per_m2x2_ck_hw.clk, + .fixed_div = 8, };

static const struct clksel_rate div2_4to8_rates[] = { @@ -1049,28 +1467,40 @@ static const struct clksel_rate div2_4to8_rates[] = { };

static const struct clksel func_48m_fclk_div[] = { - { .parent = &dpll_per_m2x2_ck, .rates = div2_4to8_rates }, + { .parent = &dpll_per_m2x2_ck_hw.clk, .rates = div2_4to8_rates }, { .parent = NULL }, };

-static struct clk func_48m_fclk = { - .name = "func_48m_fclk", - .parent = &dpll_per_m2x2_ck, +static const struct clk_hw_ops func_48m_fclk_ops = { + .recalc_rate = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, + .get_parent = &omap2_get_parent_fixed, +}; + +static struct clk_hw_omap func_48m_fclk_hw = { + .clk = { + .name = "func_48m_fclk", + .ops = &func_48m_fclk_ops, + }, + .fixed_parent = &dpll_per_m2x2_ck_hw.clk, .clksel = func_48m_fclk_div, .clksel_reg = OMAP4430_CM_SCALE_FCLK, .clksel_mask = OMAP4430_SCALE_FCLK_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, };

-static struct clk func_48mc_fclk = { - .name = "func_48mc_fclk", - .parent = &dpll_per_m2x2_ck, - .ops = &clkops_null, - .fixed_div = 4, - .recalc = &omap_fixed_divisor_recalc, +static const struct clk_hw_ops func_48mc_fclk_ops = { + .recalc_rate = &omap_fixed_divisor_recalc, + .get_parent = &omap2_get_parent_fixed, +}; + +static struct clk_hw_omap func_48mc_fclk_hw = { + .clk = { + .name = "func_48mc_fclk", + .ops = &func_48mc_fclk_ops, + }, + .fixed_parent = &dpll_per_m2x2_ck_hw.clk, + .fixed_div = 4, };

static const struct clksel_rate div2_2to4_rates[] = { @@ -1080,37 +1510,49 @@ static const struct clksel_rate div2_2to4_rates[] = { };

static const struct clksel func_64m_fclk_div[] = { - { .parent = &dpll_per_m4x2_ck, .rates = div2_2to4_rates }, + { .parent = &dpll_per_m4x2_ck_hw.clk, .rates = div2_2to4_rates }, { .parent = NULL }, };

-static struct clk func_64m_fclk = { - .name = "func_64m_fclk", - .parent = &dpll_per_m4x2_ck, +static const struct clk_hw_ops func_64m_fclk_ops = { + .recalc_rate = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, + .get_parent = &omap2_get_parent_fixed, +}; + +static struct clk_hw_omap func_64m_fclk_hw = { + .clk = { + .name = "func_64m_fclk", + .ops = &func_64m_fclk_ops, + }, + .fixed_parent = &dpll_per_m4x2_ck_hw.clk, .clksel = func_64m_fclk_div, .clksel_reg = OMAP4430_CM_SCALE_FCLK, .clksel_mask = OMAP4430_SCALE_FCLK_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, };

static const struct clksel func_96m_fclk_div[] = { - { .parent = &dpll_per_m2x2_ck, .rates = div2_2to4_rates }, + { .parent = &dpll_per_m2x2_ck_hw.clk, .rates = div2_2to4_rates }, { .parent = NULL }, };

-static struct clk func_96m_fclk = { - .name = "func_96m_fclk", - .parent = &dpll_per_m2x2_ck, +static const struct clk_hw_ops func_96m_fclk_ops = { + .recalc_rate = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, + .get_parent = &omap2_get_parent_fixed, +}; + +static struct clk_hw_omap func_96m_fclk_hw = { + .clk = { + .name = "func_96m_fclk", + .ops = &func_96m_fclk_ops, + }, + .fixed_parent = &dpll_per_m2x2_ck_hw.clk, .clksel = func_96m_fclk_div, .clksel_reg = OMAP4430_CM_SCALE_FCLK, .clksel_mask = OMAP4430_SCALE_FCLK_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, };

static const struct clksel_rate div2_1to8_rates[] = { @@ -1120,1606 +1562,1944 @@ static const struct clksel_rate div2_1to8_rates[] = { };

static const struct clksel init_60m_fclk_div[] = { - { .parent = &dpll_usb_m2_ck, .rates = div2_1to8_rates }, + { .parent = &dpll_usb_m2_ck_hw.clk, .rates = div2_1to8_rates }, { .parent = NULL }, };

-static struct clk init_60m_fclk = { - .name = "init_60m_fclk", - .parent = &dpll_usb_m2_ck, +static const struct clk_hw_ops init_60m_fclk_ops = { + .recalc_rate = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, + .get_parent = &omap2_get_parent_fixed, +}; + +static struct clk_hw_omap init_60m_fclk_hw = { + .clk = { + .name = "init_60m_fclk", + .ops = &init_60m_fclk_ops, + }, + .fixed_parent = &dpll_usb_m2_ck_hw.clk, .clksel = init_60m_fclk_div, .clksel_reg = OMAP4430_CM_CLKSEL_USB_60MHZ, .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, };

static const struct clksel l3_div_div[] = { - { .parent = &div_core_ck, .rates = div2_1to2_rates }, + { .parent = &div_core_ck_hw.clk, .rates = div2_1to2_rates }, { .parent = NULL }, };

-static struct clk l3_div_ck = { - .name = "l3_div_ck", - .parent = &div_core_ck, +static const struct clk_hw_ops l3_div_ck_ops = { + .recalc_rate = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, + .get_parent = &omap2_get_parent_fixed, +}; + +static struct clk_hw_omap l3_div_ck_hw = { + .clk = { + .name = "l3_div_ck", + .ops = &l3_div_ck_ops, + }, + .fixed_parent = &div_core_ck_hw.clk, .clksel = l3_div_div, .clksel_reg = OMAP4430_CM_CLKSEL_CORE, .clksel_mask = OMAP4430_CLKSEL_L3_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, };

static const struct clksel l4_div_div[] = { - { .parent = &l3_div_ck, .rates = div2_1to2_rates }, + { .parent = &l3_div_ck_hw.clk, .rates = div2_1to2_rates }, { .parent = NULL }, };

-static struct clk l4_div_ck = { - .name = "l4_div_ck", - .parent = &l3_div_ck, +static const struct clk_hw_ops l4_div_ck_ops = { + .recalc_rate = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, + .get_parent = &omap2_get_parent_fixed, +}; + +static struct clk_hw_omap l4_div_ck_hw = { + .clk = { + .name = "l4_div_ck", + .ops = &l4_div_ck_ops, + }, + .fixed_parent = &l3_div_ck_hw.clk, .clksel = l4_div_div, .clksel_reg = OMAP4430_CM_CLKSEL_CORE, .clksel_mask = OMAP4430_CLKSEL_L4_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, };

-static struct clk lp_clk_div_ck = { - .name = "lp_clk_div_ck", - .parent = &dpll_abe_m2x2_ck, - .ops = &clkops_null, - .fixed_div = 16, - .recalc = &omap_fixed_divisor_recalc, +static const struct clk_hw_ops lp_clk_div_ck_ops = { + .recalc_rate = &omap_fixed_divisor_recalc, + .get_parent = &omap2_get_parent_fixed, +}; + +static struct clk_hw_omap lp_clk_div_ck_hw = { + .clk = { + .name = "lp_clk_div_ck", + .ops = &lp_clk_div_ck_ops, + }, + .fixed_parent = &dpll_abe_m2x2_ck_hw.clk, + .fixed_div = 16, };

static const struct clksel l4_wkup_clk_mux_sel[] = { - { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, - { .parent = &lp_clk_div_ck, .rates = div_1_1_rates }, + { .parent = &sys_clkin_ck_hw.clk, .rates = div_1_0_rates }, + { .parent = &lp_clk_div_ck_hw.clk, .rates = div_1_1_rates }, { .parent = NULL }, };

-static struct clk l4_wkup_clk_mux_ck = { - .name = "l4_wkup_clk_mux_ck", - .parent = &sys_clkin_ck, +static const struct clk_hw_ops l4_wkup_clk_mux_ck_ops = { + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_init_clksel_parent, + .set_parent = &omap2_clksel_set_parent, +}; + +static struct clk_hw_omap l4_wkup_clk_mux_ck_hw = { + .clk = { + .name = "l4_wkup_clk_mux_ck", + .ops = &l4_wkup_clk_mux_ck_ops, + }, + .fixed_parent = &sys_clkin_ck_hw.clk, .clksel = l4_wkup_clk_mux_sel, - .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM_L4_WKUP_CLKSEL, .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, };

-static const struct clksel_rate div2_2to1_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_4430 }, - { .div = 2, .val = 0, .flags = RATE_IN_4430 }, - { .div = 0 }, +static const struct clk_hw_ops ocp_abe_iclk_ops = { + .get_parent = &omap2_get_parent_fixed, };

-static const struct clksel ocp_abe_iclk_div[] = { - { .parent = &aess_fclk, .rates = div2_2to1_rates }, - { .parent = NULL }, +static struct clk_hw_omap ocp_abe_iclk_hw = { + .clk = { + .name = "ocp_abe_iclk", + .ops = &ocp_abe_iclk_ops, + }, + .fixed_parent = &aess_fclk_hw.clk, };

-static struct clk ocp_abe_iclk = { - .name = "ocp_abe_iclk", - .parent = &aess_fclk, - .clksel = ocp_abe_iclk_div, - .clksel_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_AESS_FCLK_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, +static const struct clk_hw_ops per_abe_24m_fclk_ops = { + .recalc_rate = &omap_fixed_divisor_recalc, + .get_parent = &omap2_get_parent_fixed, };

-static struct clk per_abe_24m_fclk = { - .name = "per_abe_24m_fclk", - .parent = &dpll_abe_m2_ck, - .ops = &clkops_null, - .fixed_div = 4, - .recalc = &omap_fixed_divisor_recalc, +static struct clk_hw_omap per_abe_24m_fclk_hw = { + .clk = { + .name = "per_abe_24m_fclk", + .ops = &per_abe_24m_fclk_ops, + }, + .fixed_parent = &dpll_abe_m2_ck_hw.clk, + .fixed_div = 4, };

static const struct clksel per_abe_nc_fclk_div[] = { - { .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates }, + { .parent = &dpll_abe_m2_ck_hw.clk, .rates = div2_1to2_rates }, { .parent = NULL }, };

-static struct clk per_abe_nc_fclk = { - .name = "per_abe_nc_fclk", - .parent = &dpll_abe_m2_ck, +static const struct clk_hw_ops per_abe_nc_fclk_ops = { + .recalc_rate = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, + .get_parent = &omap2_get_parent_fixed, +}; + +static struct clk_hw_omap per_abe_nc_fclk_hw = { + .clk = { + .name = "per_abe_nc_fclk", + .ops = &per_abe_nc_fclk_ops, + }, + .fixed_parent = &dpll_abe_m2_ck_hw.clk, .clksel = per_abe_nc_fclk_div, .clksel_reg = OMAP4430_CM_SCALE_FCLK, .clksel_mask = OMAP4430_SCALE_FCLK_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, };

static const struct clksel pmd_stm_clock_mux_sel[] = { - { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, - { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates }, - { .parent = &tie_low_clock_ck, .rates = div_1_2_rates }, + { .parent = &sys_clkin_ck_hw.clk, .rates = div_1_0_rates }, + { .parent = &dpll_core_m6x2_ck_hw.clk, .rates = div_1_1_rates }, + { .parent = &tie_low_clock_ck_hw.clk, .rates = div_1_2_rates }, { .parent = NULL }, };

-static struct clk pmd_stm_clock_mux_ck = { - .name = "pmd_stm_clock_mux_ck", - .parent = &sys_clkin_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, +static const struct clk_hw_ops pmd_stm_clock_mux_ck_ops = { + .get_parent = &omap2_get_parent_fixed, +}; + +static struct clk_hw_omap pmd_stm_clock_mux_ck_hw = { + .clk = { + .name = "pmd_stm_clock_mux_ck", + .ops = &pmd_stm_clock_mux_ck_ops, + }, + .fixed_parent = &sys_clkin_ck_hw.clk, +}; + +static const struct clk_hw_ops pmd_trace_clk_mux_ck_ops = { + .get_parent = &omap2_get_parent_fixed, };

-static struct clk pmd_trace_clk_mux_ck = { - .name = "pmd_trace_clk_mux_ck", - .parent = &sys_clkin_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, +static struct clk_hw_omap pmd_trace_clk_mux_ck_hw = { + .clk = { + .name = "pmd_trace_clk_mux_ck", + .ops = &pmd_trace_clk_mux_ck_ops, + }, + .fixed_parent = &sys_clkin_ck_hw.clk, };

static const struct clksel syc_clk_div_div[] = { - { .parent = &sys_clkin_ck, .rates = div2_1to2_rates }, + { .parent = &sys_clkin_ck_hw.clk, .rates = div2_1to2_rates }, { .parent = NULL }, };

-static struct clk syc_clk_div_ck = { - .name = "syc_clk_div_ck", - .parent = &sys_clkin_ck, +static const struct clk_hw_ops syc_clk_div_ck_ops = { + .recalc_rate = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, + .get_parent = &omap2_get_parent_fixed, +}; + +static struct clk_hw_omap syc_clk_div_ck_hw = { + .clk = { + .name = "syc_clk_div_ck", + .ops = &syc_clk_div_ck_ops, + }, + .fixed_parent = &sys_clkin_ck_hw.clk, .clksel = syc_clk_div_div, .clksel_reg = OMAP4430_CM_ABE_DSS_SYS_CLKSEL, .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, };

/* Leaf clocks controlled by modules */

-static struct clk aes1_fck = { - .name = "aes1_fck", - .ops = &clkops_omap2_dflt, +static struct clk_hw_ops leaf_ck_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .get_parent = &omap2_get_parent_fixed, +}; + +static struct clk_hw_omap aes1_fck_hw = { + .clk = { + .name = "aes1_fck", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L4SEC_AES1_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, .clkdm_name = "l4_secure_clkdm", - .parent = &l3_div_ck, - .recalc = &followparent_recalc, + .fixed_parent = &l3_div_ck_hw.clk, };

-static struct clk aes2_fck = { - .name = "aes2_fck", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap aes2_fck_hw = { + .clk = { + .name = "aes2_fck", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L4SEC_AES2_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, .clkdm_name = "l4_secure_clkdm", - .parent = &l3_div_ck, - .recalc = &followparent_recalc, + .fixed_parent = &l3_div_ck_hw.clk, };

-static struct clk aess_fck = { - .name = "aess_fck", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap aess_fck_hw = { + .clk = { + .name = "aess_fck", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, .clkdm_name = "abe_clkdm", - .parent = &aess_fclk, - .recalc = &followparent_recalc, + .fixed_parent = &aess_fclk_hw.clk, };

-static struct clk bandgap_fclk = { - .name = "bandgap_fclk", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap bandgap_fclk_hw = { + .clk = { + .name = "bandgap_fclk", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT, .clkdm_name = "l4_wkup_clkdm", - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, + .fixed_parent = &sys_32k_ck_hw.clk, };

-static struct clk des3des_fck = { - .name = "des3des_fck", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap des3des_fck_hw = { + .clk = { + .name = "des3des_fck", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L4SEC_DES3DES_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, .clkdm_name = "l4_secure_clkdm", - .parent = &l4_div_ck, - .recalc = &followparent_recalc, + .fixed_parent = &l4_div_ck_hw.clk, };

static const struct clksel dmic_sync_mux_sel[] = { - { .parent = &abe_24m_fclk, .rates = div_1_0_rates }, - { .parent = &syc_clk_div_ck, .rates = div_1_1_rates }, - { .parent = &func_24m_clk, .rates = div_1_2_rates }, + { .parent = &abe_24m_fclk_hw.clk, .rates = div_1_0_rates }, + { .parent = &syc_clk_div_ck_hw.clk, .rates = div_1_1_rates }, + { .parent = &func_24m_clk_hw.clk, .rates = div_1_2_rates }, { .parent = NULL }, };

-static struct clk dmic_sync_mux_ck = { - .name = "dmic_sync_mux_ck", - .parent = &abe_24m_fclk, +static const struct clk_hw_ops dmic_sync_mux_ck_ops = { + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_init_clksel_parent, + .set_parent = &omap2_clksel_set_parent, +}; + +static struct clk_hw_omap dmic_sync_mux_ck_hw = { + .clk = { + .name = "dmic_sync_mux_ck", + .ops = &dmic_sync_mux_ck_ops, + }, + .fixed_parent = &abe_24m_fclk_hw.clk, .clksel = dmic_sync_mux_sel, - .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, };

static const struct clksel func_dmic_abe_gfclk_sel[] = { - { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates }, - { .parent = &pad_clks_ck, .rates = div_1_1_rates }, - { .parent = &slimbus_clk, .rates = div_1_2_rates }, + { .parent = &dmic_sync_mux_ck_hw.clk, .rates = div_1_0_rates }, + { .parent = &pad_clks_ck_hw.clk, .rates = div_1_1_rates }, + { .parent = &slimbus_clk_hw.clk, .rates = div_1_2_rates }, { .parent = NULL }, };

+static const struct clk_hw_ops dmic_fck_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_init_clksel_parent, + .set_parent = &omap2_clksel_set_parent, +}; + /* Merged func_dmic_abe_gfclk into dmic */ -static struct clk dmic_fck = { - .name = "dmic_fck", - .parent = &dmic_sync_mux_ck, +static struct clk_hw_omap dmic_fck_hw = { + .clk = { + .name = "dmic_fck", + .ops = &dmic_fck_ops, + }, + .fixed_parent = &dmic_sync_mux_ck_hw.clk, + .clkdm_name = "abe_clkdm", + .enable_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, .clksel = func_dmic_abe_gfclk_sel, - .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", };

-static struct clk dsp_fck = { - .name = "dsp_fck", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap dsp_fck_hw = { + .clk = { + .name = "dsp_fck", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, + .enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT, .clkdm_name = "tesla_clkdm", - .parent = &dpll_iva_m4x2_ck, - .recalc = &followparent_recalc, + .fixed_parent = &dpll_iva_m4x2_ck_hw.clk, };

-static struct clk dss_sys_clk = { - .name = "dss_sys_clk", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap dss_sys_clk_hw = { + .clk = { + .name = "dss_sys_clk", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT, .clkdm_name = "l3_dss_clkdm", - .parent = &syc_clk_div_ck, - .recalc = &followparent_recalc, + .fixed_parent = &syc_clk_div_ck_hw.clk, };

-static struct clk dss_tv_clk = { - .name = "dss_tv_clk", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap dss_tv_clk_hw = { + .clk = { + .name = "dss_tv_clk", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, .clkdm_name = "l3_dss_clkdm", - .parent = &extalt_clkin_ck, - .recalc = &followparent_recalc, + .fixed_parent = &extalt_clkin_ck_hw.clk, };

-static struct clk dss_dss_clk = { - .name = "dss_dss_clk", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap dss_dss_clk_hw = { + .clk = { + .name = "dss_dss_clk", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_DSSCLK_SHIFT, .clkdm_name = "l3_dss_clkdm", - .parent = &dpll_per_m5x2_ck, - .recalc = &followparent_recalc, -}; - -static const struct clksel_rate div3_8to32_rates[] = { - { .div = 8, .val = 0, .flags = RATE_IN_4460 }, - { .div = 16, .val = 1, .flags = RATE_IN_4460 }, - { .div = 32, .val = 2, .flags = RATE_IN_4460 }, - { .div = 0 }, -}; - -static const struct clksel div_ts_div[] = { - { .parent = &l4_wkup_clk_mux_ck, .rates = div3_8to32_rates }, - { .parent = NULL }, -}; - -static struct clk div_ts_ck = { - .name = "div_ts_ck", - .parent = &l4_wkup_clk_mux_ck, - .clksel = div_ts_div, - .clksel_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_24_25_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, + .fixed_parent = &dpll_per_m5x2_ck_hw.clk, };

-static struct clk bandgap_ts_fclk = { - .name = "bandgap_ts_fclk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, - .enable_bit = OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT, - .clkdm_name = "l4_wkup_clkdm", - .parent = &div_ts_ck, - .recalc = &followparent_recalc, -}; - -static struct clk dss_48mhz_clk = { - .name = "dss_48mhz_clk", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap dss_48mhz_clk_hw = { + .clk = { + .name = "dss_48mhz_clk", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT, .clkdm_name = "l3_dss_clkdm", - .parent = &func_48mc_fclk, - .recalc = &followparent_recalc, + .fixed_parent = &func_48mc_fclk_hw.clk, };

-static struct clk dss_fck = { - .name = "dss_fck", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap dss_fck_hw = { + .clk = { + .name = "dss_fck", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, .clkdm_name = "l3_dss_clkdm", - .parent = &l3_div_ck, - .recalc = &followparent_recalc, + .fixed_parent = &l3_div_ck_hw.clk, };

-static struct clk efuse_ctrl_cust_fck = { - .name = "efuse_ctrl_cust_fck", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap efuse_ctrl_cust_fck_hw = { + .clk = { + .name = "efuse_ctrl_cust_fck", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, .clkdm_name = "l4_cefuse_clkdm", - .parent = &sys_clkin_ck, - .recalc = &followparent_recalc, + .fixed_parent = &sys_clkin_ck_hw.clk, };

-static struct clk emif1_fck = { - .name = "emif1_fck", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap emif1_fck_hw = { + .clk = { + .name = "emif1_fck", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, + .enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT, .flags = ENABLE_ON_INIT, .clkdm_name = "l3_emif_clkdm", - .parent = &ddrphy_ck, - .recalc = &followparent_recalc, + .fixed_parent = &ddrphy_ck_hw.clk, };

-static struct clk emif2_fck = { - .name = "emif2_fck", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap emif2_fck_hw = { + .clk = { + .name = "emif2_fck", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, + .enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT, .flags = ENABLE_ON_INIT, .clkdm_name = "l3_emif_clkdm", - .parent = &ddrphy_ck, - .recalc = &followparent_recalc, + .fixed_parent = &ddrphy_ck_hw.clk, };

static const struct clksel fdif_fclk_div[] = { - { .parent = &dpll_per_m4x2_ck, .rates = div3_1to4_rates }, + { .parent = &dpll_per_m4x2_ck_hw.clk, .rates = div3_1to4_rates }, { .parent = NULL }, };

+static const struct clk_hw_ops fdif_fck_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .recalc_rate = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, + .get_parent = &omap2_get_parent_fixed, +}; + /* Merged fdif_fclk into fdif */ -static struct clk fdif_fck = { - .name = "fdif_fck", - .parent = &dpll_per_m4x2_ck, +static struct clk_hw_omap fdif_fck_hw = { + .clk = { + .name = "fdif_fck", + .ops = &fdif_fck_ops, + }, + .fixed_parent = &dpll_per_m4x2_ck_hw.clk, + .clkdm_name = "iss_clkdm", + .enable_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, .clksel = fdif_fclk_div, .clksel_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_FCLK_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, - .enable_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "iss_clkdm", };

-static struct clk fpka_fck = { - .name = "fpka_fck", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap fpka_fck_hw = { + .clk = { + .name = "fpka_fck", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, .clkdm_name = "l4_secure_clkdm", - .parent = &l4_div_ck, - .recalc = &followparent_recalc, + .fixed_parent = &l4_div_ck_hw.clk, };

-static struct clk gpio1_dbclk = { - .name = "gpio1_dbclk", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap gpio1_dbclk_hw = { + .clk = { + .name = "gpio1_dbclk", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, .clkdm_name = "l4_wkup_clkdm", - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, + .fixed_parent = &sys_32k_ck_hw.clk, };

-static struct clk gpio1_ick = { - .name = "gpio1_ick", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap gpio1_ick_hw = { + .clk = { + .name = "gpio1_ick", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, + .enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT, .clkdm_name = "l4_wkup_clkdm", - .parent = &l4_wkup_clk_mux_ck, - .recalc = &followparent_recalc, + .fixed_parent = &l4_wkup_clk_mux_ck_hw.clk, };

-static struct clk gpio2_dbclk = { - .name = "gpio2_dbclk", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap gpio2_dbclk_hw = { + .clk = { + .name = "gpio2_dbclk", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, .clkdm_name = "l4_per_clkdm", - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, + .fixed_parent = &sys_32k_ck_hw.clk, };

-static struct clk gpio2_ick = { - .name = "gpio2_ick", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap gpio2_ick_hw = { + .clk = { + .name = "gpio2_ick", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, + .enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT, .clkdm_name = "l4_per_clkdm", - .parent = &l4_div_ck, - .recalc = &followparent_recalc, + .fixed_parent = &l4_div_ck_hw.clk, };

-static struct clk gpio3_dbclk = { - .name = "gpio3_dbclk", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap gpio3_dbclk_hw = { + .clk = { + .name = "gpio3_dbclk", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, .clkdm_name = "l4_per_clkdm", - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, + .fixed_parent = &sys_32k_ck_hw.clk, };

-static struct clk gpio3_ick = { - .name = "gpio3_ick", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap gpio3_ick_hw = { + .clk = { + .name = "gpio3_ick", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, + .enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT, .clkdm_name = "l4_per_clkdm", - .parent = &l4_div_ck, - .recalc = &followparent_recalc, + .fixed_parent = &l4_div_ck_hw.clk, };

-static struct clk gpio4_dbclk = { - .name = "gpio4_dbclk", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap gpio4_dbclk_hw = { + .clk = { + .name = "gpio4_dbclk", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, .clkdm_name = "l4_per_clkdm", - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, + .fixed_parent = &sys_32k_ck_hw.clk, };

-static struct clk gpio4_ick = { - .name = "gpio4_ick", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap gpio4_ick_hw = { + .clk = { + .name = "gpio4_ick", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, + .enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT, .clkdm_name = "l4_per_clkdm", - .parent = &l4_div_ck, - .recalc = &followparent_recalc, + .fixed_parent = &l4_div_ck_hw.clk, };

-static struct clk gpio5_dbclk = { - .name = "gpio5_dbclk", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap gpio5_dbclk_hw = { + .clk = { + .name = "gpio5_dbclk", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, .clkdm_name = "l4_per_clkdm", - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, + .fixed_parent = &sys_32k_ck_hw.clk, };

-static struct clk gpio5_ick = { - .name = "gpio5_ick", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap gpio5_ick_hw = { + .clk = { + .name = "gpio5_ick", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, + .enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT, .clkdm_name = "l4_per_clkdm", - .parent = &l4_div_ck, - .recalc = &followparent_recalc, + .fixed_parent = &l4_div_ck_hw.clk, };

-static struct clk gpio6_dbclk = { - .name = "gpio6_dbclk", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap gpio6_dbclk_hw = { + .clk = { + .name = "gpio6_dbclk", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, .clkdm_name = "l4_per_clkdm", - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, + .fixed_parent = &sys_32k_ck_hw.clk, };

-static struct clk gpio6_ick = { - .name = "gpio6_ick", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap gpio6_ick_hw = { + .clk = { + .name = "gpio6_ick", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, + .enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT, .clkdm_name = "l4_per_clkdm", - .parent = &l4_div_ck, - .recalc = &followparent_recalc, + .fixed_parent = &l4_div_ck_hw.clk, };

-static struct clk gpmc_ick = { - .name = "gpmc_ick", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap gpmc_ick_hw = { + .clk = { + .name = "gpmc_ick", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L3_2_GPMC_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, + .enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT, .flags = ENABLE_ON_INIT, .clkdm_name = "l3_2_clkdm", - .parent = &l3_div_ck, - .recalc = &followparent_recalc, + .fixed_parent = &l3_div_ck_hw.clk, };

static const struct clksel sgx_clk_mux_sel[] = { - { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates }, - { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates }, + { .parent = &dpll_core_m7x2_ck_hw.clk, .rates = div_1_0_rates }, + { .parent = &dpll_per_m7x2_ck_hw.clk, .rates = div_1_1_rates }, { .parent = NULL }, };

+static const struct clk_hw_ops gpu_fck_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_init_clksel_parent, + .set_parent = &omap2_clksel_set_parent, +}; + /* Merged sgx_clk_mux into gpu */ -static struct clk gpu_fck = { - .name = "gpu_fck", - .parent = &dpll_core_m7x2_ck, +static struct clk_hw_omap gpu_fck_hw = { + .clk = { + .name = "gpu_fck", + .ops = &gpu_fck_ops, + }, + .fixed_parent = &dpll_core_m7x2_ck_hw.clk, + .clkdm_name = "l3_gfx_clkdm", + .enable_reg = OMAP4430_CM_GFX_GFX_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, .clksel = sgx_clk_mux_sel, - .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_SGX_FCLK_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM_GFX_GFX_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l3_gfx_clkdm", };

-static struct clk hdq1w_fck = { - .name = "hdq1w_fck", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap hdq1w_fck_hw = { + .clk = { + .name = "hdq1w_fck", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L4PER_HDQ1W_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, .clkdm_name = "l4_per_clkdm", - .parent = &func_12m_fclk, - .recalc = &followparent_recalc, + .fixed_parent = &func_12m_fclk_hw.clk, };

static const struct clksel hsi_fclk_div[] = { - { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates }, + { .parent = &dpll_per_m2x2_ck_hw.clk, .rates = div3_1to4_rates }, { .parent = NULL }, };

+static const struct clk_hw_ops hsi_fck_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .recalc_rate = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, + .get_parent = &omap2_get_parent_fixed, +}; + /* Merged hsi_fclk into hsi */ -static struct clk hsi_fck = { - .name = "hsi_fck", - .parent = &dpll_per_m2x2_ck, +static struct clk_hw_omap hsi_fck_hw = { + .clk = { + .name = "hsi_fck", + .ops = &hsi_fck_ops, + }, + .fixed_parent = &dpll_per_m2x2_ck_hw.clk, + .clkdm_name = "l3_init_clkdm", + .enable_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT, .clksel = hsi_fclk_div, .clksel_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_24_25_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, - .enable_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "l3_init_clkdm", };

-static struct clk i2c1_fck = { - .name = "i2c1_fck", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap i2c1_fck_hw = { + .clk = { + .name = "i2c1_fck", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, .clkdm_name = "l4_per_clkdm", - .parent = &func_96m_fclk, - .recalc = &followparent_recalc, + .fixed_parent = &func_96m_fclk_hw.clk, };

-static struct clk i2c2_fck = { - .name = "i2c2_fck", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap i2c2_fck_hw = { + .clk = { + .name = "i2c2_fck", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, .clkdm_name = "l4_per_clkdm", - .parent = &func_96m_fclk, - .recalc = &followparent_recalc, + .fixed_parent = &func_96m_fclk_hw.clk, };

-static struct clk i2c3_fck = { - .name = "i2c3_fck", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap i2c3_fck_hw = { + .clk = { + .name = "i2c3_fck", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, .clkdm_name = "l4_per_clkdm", - .parent = &func_96m_fclk, - .recalc = &followparent_recalc, + .fixed_parent = &func_96m_fclk_hw.clk, };

-static struct clk i2c4_fck = { - .name = "i2c4_fck", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap i2c4_fck_hw = { + .clk = { + .name = "i2c4_fck", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, .clkdm_name = "l4_per_clkdm", - .parent = &func_96m_fclk, - .recalc = &followparent_recalc, + .fixed_parent = &func_96m_fclk_hw.clk, };

-static struct clk ipu_fck = { - .name = "ipu_fck", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap ipu_fck_hw = { + .clk = { + .name = "ipu_fck", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, + .enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT, .clkdm_name = "ducati_clkdm", - .parent = &ducati_clk_mux_ck, - .recalc = &followparent_recalc, + .fixed_parent = &ducati_clk_mux_ck_hw.clk, };

-static struct clk iss_ctrlclk = { - .name = "iss_ctrlclk", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap iss_ctrlclk_hw = { + .clk = { + .name = "iss_ctrlclk", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_CAM_ISS_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT, .clkdm_name = "iss_clkdm", - .parent = &func_96m_fclk, - .recalc = &followparent_recalc, + .fixed_parent = &func_96m_fclk_hw.clk, };

-static struct clk iss_fck = { - .name = "iss_fck", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap iss_fck_hw = { + .clk = { + .name = "iss_fck", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_CAM_ISS_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, .clkdm_name = "iss_clkdm", - .parent = &ducati_clk_mux_ck, - .recalc = &followparent_recalc, + .fixed_parent = &ducati_clk_mux_ck_hw.clk, };

-static struct clk iva_fck = { - .name = "iva_fck", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap iva_fck_hw = { + .clk = { + .name = "iva_fck", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, + .enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT, .clkdm_name = "ivahd_clkdm", - .parent = &dpll_iva_m5x2_ck, - .recalc = &followparent_recalc, + .fixed_parent = &dpll_iva_m5x2_ck_hw.clk, };

-static struct clk kbd_fck = { - .name = "kbd_fck", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap kbd_fck_hw = { + .clk = { + .name = "kbd_fck", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, .clkdm_name = "l4_wkup_clkdm", - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, + .fixed_parent = &sys_32k_ck_hw.clk, };

-static struct clk l3_instr_ick = { - .name = "l3_instr_ick", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap l3_instr_ick_hw = { + .clk = { + .name = "l3_instr_ick", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, + .enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT, .flags = ENABLE_ON_INIT, .clkdm_name = "l3_instr_clkdm", - .parent = &l3_div_ck, - .recalc = &followparent_recalc, + .fixed_parent = &l3_div_ck_hw.clk, };

-static struct clk l3_main_3_ick = { - .name = "l3_main_3_ick", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap l3_main_3_ick_hw = { + .clk = { + .name = "l3_main_3_ick", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, + .enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT, .flags = ENABLE_ON_INIT, .clkdm_name = "l3_instr_clkdm", - .parent = &l3_div_ck, - .recalc = &followparent_recalc, + .fixed_parent = &l3_div_ck_hw.clk, +}; + +static const struct clk_hw_ops mcasp_sync_mux_ck_ops = { + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_init_clksel_parent, + .set_parent = &omap2_clksel_set_parent, };

-static struct clk mcasp_sync_mux_ck = { - .name = "mcasp_sync_mux_ck", - .parent = &abe_24m_fclk, +static struct clk_hw_omap mcasp_sync_mux_ck_hw = { + .clk = { + .name = "mcasp_sync_mux_ck", + .ops = &mcasp_sync_mux_ck_ops, + }, + .fixed_parent = &abe_24m_fclk_hw.clk, .clksel = dmic_sync_mux_sel, - .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, };

static const struct clksel func_mcasp_abe_gfclk_sel[] = { - { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates }, - { .parent = &pad_clks_ck, .rates = div_1_1_rates }, - { .parent = &slimbus_clk, .rates = div_1_2_rates }, + { .parent = &mcasp_sync_mux_ck_hw.clk, .rates = div_1_0_rates }, + { .parent = &pad_clks_ck_hw.clk, .rates = div_1_1_rates }, + { .parent = &slimbus_clk_hw.clk, .rates = div_1_2_rates }, { .parent = NULL }, };

+static const struct clk_hw_ops mcasp_fck_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_init_clksel_parent, + .set_parent = &omap2_clksel_set_parent, +}; + /* Merged func_mcasp_abe_gfclk into mcasp */ -static struct clk mcasp_fck = { - .name = "mcasp_fck", - .parent = &mcasp_sync_mux_ck, +static struct clk_hw_omap mcasp_fck_hw = { + .clk = { + .name = "mcasp_fck", + .ops = &mcasp_fck_ops, + }, + .fixed_parent = &mcasp_sync_mux_ck_hw.clk, + .clkdm_name = "abe_clkdm", + .enable_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, .clksel = func_mcasp_abe_gfclk_sel, - .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", };

-static struct clk mcbsp1_sync_mux_ck = { - .name = "mcbsp1_sync_mux_ck", - .parent = &abe_24m_fclk, +static const struct clk_hw_ops mcbsp1_sync_mux_ck_ops = { + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_init_clksel_parent, + .set_parent = &omap2_clksel_set_parent, +}; + +static struct clk_hw_omap mcbsp1_sync_mux_ck_hw = { + .clk = { + .name = "mcbsp1_sync_mux_ck", + .ops = &mcbsp1_sync_mux_ck_ops, + }, + .fixed_parent = &abe_24m_fclk_hw.clk, .clksel = dmic_sync_mux_sel, - .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, };

static const struct clksel func_mcbsp1_gfclk_sel[] = { - { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates }, - { .parent = &pad_clks_ck, .rates = div_1_1_rates }, - { .parent = &slimbus_clk, .rates = div_1_2_rates }, + { .parent = &mcbsp1_sync_mux_ck_hw.clk, .rates = div_1_0_rates }, + { .parent = &pad_clks_ck_hw.clk, .rates = div_1_1_rates }, + { .parent = &slimbus_clk_hw.clk, .rates = div_1_2_rates }, { .parent = NULL }, };

+static const struct clk_hw_ops mcbsp1_fck_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_init_clksel_parent, + .set_parent = &omap2_clksel_set_parent, +}; + /* Merged func_mcbsp1_gfclk into mcbsp1 */ -static struct clk mcbsp1_fck = { - .name = "mcbsp1_fck", - .parent = &mcbsp1_sync_mux_ck, +static struct clk_hw_omap mcbsp1_fck_hw = { + .clk = { + .name = "mcbsp1_fck", + .ops = &mcbsp1_fck_ops, + }, + .fixed_parent = &mcbsp1_sync_mux_ck_hw.clk, + .clkdm_name = "abe_clkdm", + .enable_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, .clksel = func_mcbsp1_gfclk_sel, - .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", };

-static struct clk mcbsp2_sync_mux_ck = { - .name = "mcbsp2_sync_mux_ck", - .parent = &abe_24m_fclk, +static const struct clk_hw_ops mcbsp2_sync_mux_ck_ops = { + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_init_clksel_parent, + .set_parent = &omap2_clksel_set_parent, +}; + +static struct clk_hw_omap mcbsp2_sync_mux_ck_hw = { + .clk = { + .name = "mcbsp2_sync_mux_ck", + .ops = &mcbsp2_sync_mux_ck_ops, + }, + .fixed_parent = &abe_24m_fclk_hw.clk, .clksel = dmic_sync_mux_sel, - .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, };

static const struct clksel func_mcbsp2_gfclk_sel[] = { - { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates }, - { .parent = &pad_clks_ck, .rates = div_1_1_rates }, - { .parent = &slimbus_clk, .rates = div_1_2_rates }, + { .parent = &mcbsp2_sync_mux_ck_hw.clk, .rates = div_1_0_rates }, + { .parent = &pad_clks_ck_hw.clk, .rates = div_1_1_rates }, + { .parent = &slimbus_clk_hw.clk, .rates = div_1_2_rates }, { .parent = NULL }, };

+static const struct clk_hw_ops mcbsp2_fck_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_init_clksel_parent, + .set_parent = &omap2_clksel_set_parent, +}; + /* Merged func_mcbsp2_gfclk into mcbsp2 */ -static struct clk mcbsp2_fck = { - .name = "mcbsp2_fck", - .parent = &mcbsp2_sync_mux_ck, +static struct clk_hw_omap mcbsp2_fck_hw = { + .clk = { + .name = "mcbsp2_fck", + .ops = &mcbsp2_fck_ops, + }, + .fixed_parent = &mcbsp2_sync_mux_ck_hw.clk, + .clkdm_name = "abe_clkdm", + .enable_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, .clksel = func_mcbsp2_gfclk_sel, - .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", };

-static struct clk mcbsp3_sync_mux_ck = { - .name = "mcbsp3_sync_mux_ck", - .parent = &abe_24m_fclk, +static const struct clk_hw_ops mcbsp3_sync_mux_ck_ops = { + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_init_clksel_parent, + .set_parent = &omap2_clksel_set_parent, +}; + +static struct clk_hw_omap mcbsp3_sync_mux_ck_hw = { + .clk = { + .name = "mcbsp3_sync_mux_ck", + .ops = &mcbsp3_sync_mux_ck_ops, + }, + .fixed_parent = &abe_24m_fclk_hw.clk, .clksel = dmic_sync_mux_sel, - .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, };

static const struct clksel func_mcbsp3_gfclk_sel[] = { - { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates }, - { .parent = &pad_clks_ck, .rates = div_1_1_rates }, - { .parent = &slimbus_clk, .rates = div_1_2_rates }, + { .parent = &mcbsp3_sync_mux_ck_hw.clk, .rates = div_1_0_rates }, + { .parent = &pad_clks_ck_hw.clk, .rates = div_1_1_rates }, + { .parent = &slimbus_clk_hw.clk, .rates = div_1_2_rates }, { .parent = NULL }, };

+static const struct clk_hw_ops mcbsp3_fck_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_init_clksel_parent, + .set_parent = &omap2_clksel_set_parent, +}; + /* Merged func_mcbsp3_gfclk into mcbsp3 */ -static struct clk mcbsp3_fck = { - .name = "mcbsp3_fck", - .parent = &mcbsp3_sync_mux_ck, +static struct clk_hw_omap mcbsp3_fck_hw = { + .clk = { + .name = "mcbsp3_fck", + .ops = &mcbsp3_fck_ops, + }, + .fixed_parent = &mcbsp3_sync_mux_ck_hw.clk, + .clkdm_name = "abe_clkdm", + .enable_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, .clksel = func_mcbsp3_gfclk_sel, - .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", };

static const struct clksel mcbsp4_sync_mux_sel[] = { - { .parent = &func_96m_fclk, .rates = div_1_0_rates }, - { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates }, + { .parent = &func_96m_fclk_hw.clk, .rates = div_1_0_rates }, + { .parent = &per_abe_nc_fclk_hw.clk, .rates = div_1_1_rates }, { .parent = NULL }, };

-static struct clk mcbsp4_sync_mux_ck = { - .name = "mcbsp4_sync_mux_ck", - .parent = &func_96m_fclk, +static const struct clk_hw_ops mcbsp4_sync_mux_ck_ops = { + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_init_clksel_parent, + .set_parent = &omap2_clksel_set_parent, +}; + +static struct clk_hw_omap mcbsp4_sync_mux_ck_hw = { + .clk = { + .name = "mcbsp4_sync_mux_ck", + .ops = &mcbsp4_sync_mux_ck_ops, + }, + .fixed_parent = &func_96m_fclk_hw.clk, .clksel = mcbsp4_sync_mux_sel, - .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, };

static const struct clksel per_mcbsp4_gfclk_sel[] = { - { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates }, - { .parent = &pad_clks_ck, .rates = div_1_1_rates }, + { .parent = &mcbsp4_sync_mux_ck_hw.clk, .rates = div_1_0_rates }, + { .parent = &pad_clks_ck_hw.clk, .rates = div_1_1_rates }, { .parent = NULL }, };

+static const struct clk_hw_ops mcbsp4_fck_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_init_clksel_parent, + .set_parent = &omap2_clksel_set_parent, +}; + /* Merged per_mcbsp4_gfclk into mcbsp4 */ -static struct clk mcbsp4_fck = { - .name = "mcbsp4_fck", - .parent = &mcbsp4_sync_mux_ck, +static struct clk_hw_omap mcbsp4_fck_hw = { + .clk = { + .name = "mcbsp4_fck", + .ops = &mcbsp4_fck_ops, + }, + .fixed_parent = &mcbsp4_sync_mux_ck_hw.clk, + .clkdm_name = "l4_per_clkdm", + .enable_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, .clksel = per_mcbsp4_gfclk_sel, - .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_SOURCE_24_24_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", };

-static struct clk mcpdm_fck = { - .name = "mcpdm_fck", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap mcpdm_fck_hw = { + .clk = { + .name = "mcpdm_fck", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, .clkdm_name = "abe_clkdm", - .parent = &pad_clks_ck, - .recalc = &followparent_recalc, + .fixed_parent = &pad_clks_ck_hw.clk, };

-static struct clk mcspi1_fck = { - .name = "mcspi1_fck", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap mcspi1_fck_hw = { + .clk = { + .name = "mcspi1_fck", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, .clkdm_name = "l4_per_clkdm", - .parent = &func_48m_fclk, - .recalc = &followparent_recalc, + .fixed_parent = &func_48m_fclk_hw.clk, };

-static struct clk mcspi2_fck = { - .name = "mcspi2_fck", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap mcspi2_fck_hw = { + .clk = { + .name = "mcspi2_fck", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, .clkdm_name = "l4_per_clkdm", - .parent = &func_48m_fclk, - .recalc = &followparent_recalc, + .fixed_parent = &func_48m_fclk_hw.clk, };

-static struct clk mcspi3_fck = { - .name = "mcspi3_fck", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap mcspi3_fck_hw = { + .clk = { + .name = "mcspi3_fck", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, .clkdm_name = "l4_per_clkdm", - .parent = &func_48m_fclk, - .recalc = &followparent_recalc, + .fixed_parent = &func_48m_fclk_hw.clk, };

-static struct clk mcspi4_fck = { - .name = "mcspi4_fck", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap mcspi4_fck_hw = { + .clk = { + .name = "mcspi4_fck", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, .clkdm_name = "l4_per_clkdm", - .parent = &func_48m_fclk, - .recalc = &followparent_recalc, + .fixed_parent = &func_48m_fclk_hw.clk, };

static const struct clksel hsmmc1_fclk_sel[] = { - { .parent = &func_64m_fclk, .rates = div_1_0_rates }, - { .parent = &func_96m_fclk, .rates = div_1_1_rates }, + { .parent = &func_64m_fclk_hw.clk, .rates = div_1_0_rates }, + { .parent = &func_96m_fclk_hw.clk, .rates = div_1_1_rates }, { .parent = NULL }, };

+static const struct clk_hw_ops mmc1_fck_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_init_clksel_parent, + .set_parent = &omap2_clksel_set_parent, +}; + /* Merged hsmmc1_fclk into mmc1 */ -static struct clk mmc1_fck = { - .name = "mmc1_fck", - .parent = &func_64m_fclk, +static struct clk_hw_omap mmc1_fck_hw = { + .clk = { + .name = "mmc1_fck", + .ops = &mmc1_fck_ops, + }, + .fixed_parent = &func_64m_fclk_hw.clk, + .clkdm_name = "l3_init_clkdm", + .enable_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, .clksel = hsmmc1_fclk_sel, - .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l3_init_clkdm", +}; + +static const struct clk_hw_ops mmc2_fck_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_init_clksel_parent, + .set_parent = &omap2_clksel_set_parent, };

/* Merged hsmmc2_fclk into mmc2 */ -static struct clk mmc2_fck = { - .name = "mmc2_fck", - .parent = &func_64m_fclk, +static struct clk_hw_omap mmc2_fck_hw = { + .clk = { + .name = "mmc2_fck", + .ops = &mmc2_fck_ops, + }, + .fixed_parent = &func_64m_fclk_hw.clk, + .clkdm_name = "l3_init_clkdm", + .enable_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, .clksel = hsmmc1_fclk_sel, - .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l3_init_clkdm", };

-static struct clk mmc3_fck = { - .name = "mmc3_fck", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap mmc3_fck_hw = { + .clk = { + .name = "mmc3_fck", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, .clkdm_name = "l4_per_clkdm", - .parent = &func_48m_fclk, - .recalc = &followparent_recalc, + .fixed_parent = &func_48m_fclk_hw.clk, };

-static struct clk mmc4_fck = { - .name = "mmc4_fck", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap mmc4_fck_hw = { + .clk = { + .name = "mmc4_fck", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, .clkdm_name = "l4_per_clkdm", - .parent = &func_48m_fclk, - .recalc = &followparent_recalc, + .fixed_parent = &func_48m_fclk_hw.clk, };

-static struct clk mmc5_fck = { - .name = "mmc5_fck", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap mmc5_fck_hw = { + .clk = { + .name = "mmc5_fck", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, .clkdm_name = "l4_per_clkdm", - .parent = &func_48m_fclk, - .recalc = &followparent_recalc, + .fixed_parent = &func_48m_fclk_hw.clk, };

-static struct clk ocp2scp_usb_phy_phy_48m = { - .name = "ocp2scp_usb_phy_phy_48m", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap ocp2scp_usb_phy_phy_48m_hw = { + .clk = { + .name = "ocp2scp_usb_phy_phy_48m", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, .clkdm_name = "l3_init_clkdm", - .parent = &func_48m_fclk, - .recalc = &followparent_recalc, + .fixed_parent = &func_48m_fclk_hw.clk, };

-static struct clk ocp2scp_usb_phy_ick = { - .name = "ocp2scp_usb_phy_ick", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap ocp2scp_usb_phy_ick_hw = { + .clk = { + .name = "ocp2scp_usb_phy_ick", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, + .enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT, .clkdm_name = "l3_init_clkdm", - .parent = &l4_div_ck, - .recalc = &followparent_recalc, + .fixed_parent = &l4_div_ck_hw.clk, };

-static struct clk ocp_wp_noc_ick = { - .name = "ocp_wp_noc_ick", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap ocp_wp_noc_ick_hw = { + .clk = { + .name = "ocp_wp_noc_ick", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, + .enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT, .flags = ENABLE_ON_INIT, .clkdm_name = "l3_instr_clkdm", - .parent = &l3_div_ck, - .recalc = &followparent_recalc, + .fixed_parent = &l3_div_ck_hw.clk, };

-static struct clk rng_ick = { - .name = "rng_ick", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap rng_ick_hw = { + .clk = { + .name = "rng_ick", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L4SEC_RNG_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, + .enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT, .clkdm_name = "l4_secure_clkdm", - .parent = &l4_div_ck, - .recalc = &followparent_recalc, + .fixed_parent = &l4_div_ck_hw.clk, };

-static struct clk sha2md5_fck = { - .name = "sha2md5_fck", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap sha2md5_fck_hw = { + .clk = { + .name = "sha2md5_fck", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, .clkdm_name = "l4_secure_clkdm", - .parent = &l3_div_ck, - .recalc = &followparent_recalc, + .fixed_parent = &l3_div_ck_hw.clk, };

-static struct clk sl2if_ick = { - .name = "sl2if_ick", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap sl2if_ick_hw = { + .clk = { + .name = "sl2if_ick", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_IVAHD_SL2_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, + .enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT, .clkdm_name = "ivahd_clkdm", - .parent = &dpll_iva_m5x2_ck, - .recalc = &followparent_recalc, + .fixed_parent = &dpll_iva_m5x2_ck_hw.clk, };

-static struct clk slimbus1_fclk_1 = { - .name = "slimbus1_fclk_1", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap slimbus1_fclk_1_hw = { + .clk = { + .name = "slimbus1_fclk_1", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_FCLK1_SHIFT, .clkdm_name = "abe_clkdm", - .parent = &func_24m_clk, - .recalc = &followparent_recalc, + .fixed_parent = &func_24m_clk_hw.clk, };

-static struct clk slimbus1_fclk_0 = { - .name = "slimbus1_fclk_0", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap slimbus1_fclk_0_hw = { + .clk = { + .name = "slimbus1_fclk_0", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_FCLK0_SHIFT, .clkdm_name = "abe_clkdm", - .parent = &abe_24m_fclk, - .recalc = &followparent_recalc, + .fixed_parent = &abe_24m_fclk_hw.clk, };

-static struct clk slimbus1_fclk_2 = { - .name = "slimbus1_fclk_2", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap slimbus1_fclk_2_hw = { + .clk = { + .name = "slimbus1_fclk_2", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_FCLK2_SHIFT, .clkdm_name = "abe_clkdm", - .parent = &pad_clks_ck, - .recalc = &followparent_recalc, + .fixed_parent = &pad_clks_ck_hw.clk, };

-static struct clk slimbus1_slimbus_clk = { - .name = "slimbus1_slimbus_clk", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap slimbus1_slimbus_clk_hw = { + .clk = { + .name = "slimbus1_slimbus_clk", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT, .clkdm_name = "abe_clkdm", - .parent = &slimbus_clk, - .recalc = &followparent_recalc, + .fixed_parent = &slimbus_clk_hw.clk, };

-static struct clk slimbus1_fck = { - .name = "slimbus1_fck", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap slimbus1_fck_hw = { + .clk = { + .name = "slimbus1_fck", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, .clkdm_name = "abe_clkdm", - .parent = &ocp_abe_iclk, - .recalc = &followparent_recalc, + .fixed_parent = &ocp_abe_iclk_hw.clk, };

-static struct clk slimbus2_fclk_1 = { - .name = "slimbus2_fclk_1", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap slimbus2_fclk_1_hw = { + .clk = { + .name = "slimbus2_fclk_1", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT, .clkdm_name = "l4_per_clkdm", - .parent = &per_abe_24m_fclk, - .recalc = &followparent_recalc, + .fixed_parent = &per_abe_24m_fclk_hw.clk, };

-static struct clk slimbus2_fclk_0 = { - .name = "slimbus2_fclk_0", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap slimbus2_fclk_0_hw = { + .clk = { + .name = "slimbus2_fclk_0", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT, .clkdm_name = "l4_per_clkdm", - .parent = &func_24mc_fclk, - .recalc = &followparent_recalc, + .fixed_parent = &func_24mc_fclk_hw.clk, };

-static struct clk slimbus2_slimbus_clk = { - .name = "slimbus2_slimbus_clk", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap slimbus2_slimbus_clk_hw = { + .clk = { + .name = "slimbus2_slimbus_clk", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT, .clkdm_name = "l4_per_clkdm", - .parent = &pad_slimbus_core_clks_ck, - .recalc = &followparent_recalc, + .fixed_parent = &pad_slimbus_core_clks_ck_hw.clk, };

-static struct clk slimbus2_fck = { - .name = "slimbus2_fck", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap slimbus2_fck_hw = { + .clk = { + .name = "slimbus2_fck", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, .clkdm_name = "l4_per_clkdm", - .parent = &l4_div_ck, - .recalc = &followparent_recalc, + .fixed_parent = &l4_div_ck_hw.clk, };

-static struct clk smartreflex_core_fck = { - .name = "smartreflex_core_fck", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap smartreflex_core_fck_hw = { + .clk = { + .name = "smartreflex_core_fck", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, .clkdm_name = "l4_ao_clkdm", - .parent = &l4_wkup_clk_mux_ck, - .recalc = &followparent_recalc, + .fixed_parent = &l4_wkup_clk_mux_ck_hw.clk, };

-static struct clk smartreflex_iva_fck = { - .name = "smartreflex_iva_fck", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap smartreflex_iva_fck_hw = { + .clk = { + .name = "smartreflex_iva_fck", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, .clkdm_name = "l4_ao_clkdm", - .parent = &l4_wkup_clk_mux_ck, - .recalc = &followparent_recalc, + .fixed_parent = &l4_wkup_clk_mux_ck_hw.clk, };

-static struct clk smartreflex_mpu_fck = { - .name = "smartreflex_mpu_fck", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap smartreflex_mpu_fck_hw = { + .clk = { + .name = "smartreflex_mpu_fck", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, .clkdm_name = "l4_ao_clkdm", - .parent = &l4_wkup_clk_mux_ck, - .recalc = &followparent_recalc, + .fixed_parent = &l4_wkup_clk_mux_ck_hw.clk, +}; + +static const struct clk_hw_ops timer1_fck_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_init_clksel_parent, + .set_parent = &omap2_clksel_set_parent, };

/* Merged dmt1_clk_mux into timer1 */ -static struct clk timer1_fck = { - .name = "timer1_fck", - .parent = &sys_clkin_ck, +static struct clk_hw_omap timer1_fck_hw = { + .clk = { + .name = "timer1_fck", + .ops = &timer1_fck_ops, + }, + .fixed_parent = &sys_clkin_ck_hw.clk, + .clkdm_name = "l4_wkup_clkdm", + .enable_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, .clksel = abe_dpll_bypass_clk_mux_sel, - .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_wkup_clkdm", +}; + +static const struct clk_hw_ops timer10_fck_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_init_clksel_parent, + .set_parent = &omap2_clksel_set_parent, };

/* Merged cm2_dm10_mux into timer10 */ -static struct clk timer10_fck = { - .name = "timer10_fck", - .parent = &sys_clkin_ck, +static struct clk_hw_omap timer10_fck_hw = { + .clk = { + .name = "timer10_fck", + .ops = &timer10_fck_ops, + }, + .fixed_parent = &sys_clkin_ck_hw.clk, + .clkdm_name = "l4_per_clkdm", + .enable_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, .clksel = abe_dpll_bypass_clk_mux_sel, - .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", +}; + +static const struct clk_hw_ops timer11_fck_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_init_clksel_parent, + .set_parent = &omap2_clksel_set_parent, };

/* Merged cm2_dm11_mux into timer11 */ -static struct clk timer11_fck = { - .name = "timer11_fck", - .parent = &sys_clkin_ck, +static struct clk_hw_omap timer11_fck_hw = { + .clk = { + .name = "timer11_fck", + .ops = &timer11_fck_ops, + }, + .fixed_parent = &sys_clkin_ck_hw.clk, + .clkdm_name = "l4_per_clkdm", + .enable_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, .clksel = abe_dpll_bypass_clk_mux_sel, - .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", +}; + +static const struct clk_hw_ops timer2_fck_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_init_clksel_parent, + .set_parent = &omap2_clksel_set_parent, };

/* Merged cm2_dm2_mux into timer2 */ -static struct clk timer2_fck = { - .name = "timer2_fck", - .parent = &sys_clkin_ck, +static struct clk_hw_omap timer2_fck_hw = { + .clk = { + .name = "timer2_fck", + .ops = &timer2_fck_ops, + }, + .fixed_parent = &sys_clkin_ck_hw.clk, + .clkdm_name = "l4_per_clkdm", + .enable_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, .clksel = abe_dpll_bypass_clk_mux_sel, - .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", +}; + +static const struct clk_hw_ops timer3_fck_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_init_clksel_parent, + .set_parent = &omap2_clksel_set_parent, };

/* Merged cm2_dm3_mux into timer3 */ -static struct clk timer3_fck = { - .name = "timer3_fck", - .parent = &sys_clkin_ck, +static struct clk_hw_omap timer3_fck_hw = { + .clk = { + .name = "timer3_fck", + .ops = &timer3_fck_ops, + }, + .fixed_parent = &sys_clkin_ck_hw.clk, + .clkdm_name = "l4_per_clkdm", + .enable_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, .clksel = abe_dpll_bypass_clk_mux_sel, - .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", +}; + +static const struct clk_hw_ops timer4_fck_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_init_clksel_parent, + .set_parent = &omap2_clksel_set_parent, };

/* Merged cm2_dm4_mux into timer4 */ -static struct clk timer4_fck = { - .name = "timer4_fck", - .parent = &sys_clkin_ck, +static struct clk_hw_omap timer4_fck_hw = { + .clk = { + .name = "timer4_fck", + .ops = &timer4_fck_ops, + }, + .fixed_parent = &sys_clkin_ck_hw.clk, + .clkdm_name = "l4_per_clkdm", + .enable_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, .clksel = abe_dpll_bypass_clk_mux_sel, - .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", };

static const struct clksel timer5_sync_mux_sel[] = { - { .parent = &syc_clk_div_ck, .rates = div_1_0_rates }, - { .parent = &sys_32k_ck, .rates = div_1_1_rates }, + { .parent = &syc_clk_div_ck_hw.clk, .rates = div_1_0_rates }, + { .parent = &sys_32k_ck_hw.clk, .rates = div_1_1_rates }, { .parent = NULL }, };

+static const struct clk_hw_ops timer5_fck_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_init_clksel_parent, + .set_parent = &omap2_clksel_set_parent, +}; + /* Merged timer5_sync_mux into timer5 */ -static struct clk timer5_fck = { - .name = "timer5_fck", - .parent = &syc_clk_div_ck, +static struct clk_hw_omap timer5_fck_hw = { + .clk = { + .name = "timer5_fck", + .ops = &timer5_fck_ops, + }, + .fixed_parent = &syc_clk_div_ck_hw.clk, + .clkdm_name = "abe_clkdm", + .enable_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, .clksel = timer5_sync_mux_sel, - .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", +}; + +static const struct clk_hw_ops timer6_fck_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_init_clksel_parent, + .set_parent = &omap2_clksel_set_parent, };

/* Merged timer6_sync_mux into timer6 */ -static struct clk timer6_fck = { - .name = "timer6_fck", - .parent = &syc_clk_div_ck, +static struct clk_hw_omap timer6_fck_hw = { + .clk = { + .name = "timer6_fck", + .ops = &timer6_fck_ops, + }, + .fixed_parent = &syc_clk_div_ck_hw.clk, + .clkdm_name = "abe_clkdm", + .enable_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, .clksel = timer5_sync_mux_sel, - .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", +}; + +static const struct clk_hw_ops timer7_fck_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_init_clksel_parent, + .set_parent = &omap2_clksel_set_parent, };

/* Merged timer7_sync_mux into timer7 */ -static struct clk timer7_fck = { - .name = "timer7_fck", - .parent = &syc_clk_div_ck, +static struct clk_hw_omap timer7_fck_hw = { + .clk = { + .name = "timer7_fck", + .ops = &timer7_fck_ops, + }, + .fixed_parent = &syc_clk_div_ck_hw.clk, + .clkdm_name = "abe_clkdm", + .enable_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, .clksel = timer5_sync_mux_sel, - .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", +}; + +static const struct clk_hw_ops timer8_fck_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_init_clksel_parent, + .set_parent = &omap2_clksel_set_parent, };

/* Merged timer8_sync_mux into timer8 */ -static struct clk timer8_fck = { - .name = "timer8_fck", - .parent = &syc_clk_div_ck, +static struct clk_hw_omap timer8_fck_hw = { + .clk = { + .name = "timer8_fck", + .ops = &timer8_fck_ops, + }, + .fixed_parent = &syc_clk_div_ck_hw.clk, + .clkdm_name = "abe_clkdm", + .enable_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, .clksel = timer5_sync_mux_sel, - .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", +}; + +static const struct clk_hw_ops timer9_fck_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_init_clksel_parent, + .set_parent = &omap2_clksel_set_parent, };

/* Merged cm2_dm9_mux into timer9 */ -static struct clk timer9_fck = { - .name = "timer9_fck", - .parent = &sys_clkin_ck, +static struct clk_hw_omap timer9_fck_hw = { + .clk = { + .name = "timer9_fck", + .ops = &timer9_fck_ops, + }, + .fixed_parent = &sys_clkin_ck_hw.clk, + .clkdm_name = "l4_per_clkdm", + .enable_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, .clksel = abe_dpll_bypass_clk_mux_sel, - .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", };

-static struct clk uart1_fck = { - .name = "uart1_fck", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap uart1_fck_hw = { + .clk = { + .name = "uart1_fck", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, .clkdm_name = "l4_per_clkdm", - .parent = &func_48m_fclk, - .recalc = &followparent_recalc, + .fixed_parent = &func_48m_fclk_hw.clk, };

-static struct clk uart2_fck = { - .name = "uart2_fck", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap uart2_fck_hw = { + .clk = { + .name = "uart2_fck", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, .clkdm_name = "l4_per_clkdm", - .parent = &func_48m_fclk, - .recalc = &followparent_recalc, + .fixed_parent = &func_48m_fclk_hw.clk, };

-static struct clk uart3_fck = { - .name = "uart3_fck", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap uart3_fck_hw = { + .clk = { + .name = "uart3_fck", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, .clkdm_name = "l4_per_clkdm", - .parent = &func_48m_fclk, - .recalc = &followparent_recalc, + .fixed_parent = &func_48m_fclk_hw.clk, };

-static struct clk uart4_fck = { - .name = "uart4_fck", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap uart4_fck_hw = { + .clk = { + .name = "uart4_fck", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, .clkdm_name = "l4_per_clkdm", - .parent = &func_48m_fclk, - .recalc = &followparent_recalc, + .fixed_parent = &func_48m_fclk_hw.clk, };

-static struct clk usb_host_fs_fck = { - .name = "usb_host_fs_fck", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap usb_host_fs_fck_hw = { + .clk = { + .name = "usb_host_fs_fck", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, .clkdm_name = "l3_init_clkdm", - .parent = &func_48mc_fclk, - .recalc = &followparent_recalc, + .fixed_parent = &func_48mc_fclk_hw.clk, };

static const struct clksel utmi_p1_gfclk_sel[] = { - { .parent = &init_60m_fclk, .rates = div_1_0_rates }, - { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates }, + { .parent = &init_60m_fclk_hw.clk, .rates = div_1_0_rates }, + { .parent = &xclk60mhsp1_ck_hw.clk, .rates = div_1_1_rates }, { .parent = NULL }, };

-static struct clk utmi_p1_gfclk = { - .name = "utmi_p1_gfclk", - .parent = &init_60m_fclk, +static const struct clk_hw_ops utmi_p1_gfclk_ops = { + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_init_clksel_parent, + .set_parent = &omap2_clksel_set_parent, +}; + +static struct clk_hw_omap utmi_p1_gfclk_hw = { + .clk = { + .name = "utmi_p1_gfclk", + .ops = &utmi_p1_gfclk_ops, + }, + .fixed_parent = &init_60m_fclk_hw.clk, .clksel = utmi_p1_gfclk_sel, - .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_UTMI_P1_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, };

-static struct clk usb_host_hs_utmi_p1_clk = { - .name = "usb_host_hs_utmi_p1_clk", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap usb_host_hs_utmi_p1_clk_hw = { + .clk = { + .name = "usb_host_hs_utmi_p1_clk", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT, .clkdm_name = "l3_init_clkdm", - .parent = &utmi_p1_gfclk, - .recalc = &followparent_recalc, + .fixed_parent = &utmi_p1_gfclk_hw.clk, };

static const struct clksel utmi_p2_gfclk_sel[] = { - { .parent = &init_60m_fclk, .rates = div_1_0_rates }, - { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates }, + { .parent = &init_60m_fclk_hw.clk, .rates = div_1_0_rates }, + { .parent = &xclk60mhsp2_ck_hw.clk, .rates = div_1_1_rates }, { .parent = NULL }, };

-static struct clk utmi_p2_gfclk = { - .name = "utmi_p2_gfclk", - .parent = &init_60m_fclk, +static const struct clk_hw_ops utmi_p2_gfclk_ops = { + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_init_clksel_parent, + .set_parent = &omap2_clksel_set_parent, +}; + +static struct clk_hw_omap utmi_p2_gfclk_hw = { + .clk = { + .name = "utmi_p2_gfclk", + .ops = &utmi_p2_gfclk_ops, + }, + .fixed_parent = &init_60m_fclk_hw.clk, .clksel = utmi_p2_gfclk_sel, - .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_UTMI_P2_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, };

-static struct clk usb_host_hs_utmi_p2_clk = { - .name = "usb_host_hs_utmi_p2_clk", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap usb_host_hs_utmi_p2_clk_hw = { + .clk = { + .name = "usb_host_hs_utmi_p2_clk", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT, .clkdm_name = "l3_init_clkdm", - .parent = &utmi_p2_gfclk, - .recalc = &followparent_recalc, + .fixed_parent = &utmi_p2_gfclk_hw.clk, };

-static struct clk usb_host_hs_utmi_p3_clk = { - .name = "usb_host_hs_utmi_p3_clk", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap usb_host_hs_utmi_p3_clk_hw = { + .clk = { + .name = "usb_host_hs_utmi_p3_clk", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT, .clkdm_name = "l3_init_clkdm", - .parent = &init_60m_fclk, - .recalc = &followparent_recalc, + .fixed_parent = &init_60m_fclk_hw.clk, };

-static struct clk usb_host_hs_hsic480m_p1_clk = { - .name = "usb_host_hs_hsic480m_p1_clk", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap usb_host_hs_hsic480m_p1_clk_hw = { + .clk = { + .name = "usb_host_hs_hsic480m_p1_clk", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT, .clkdm_name = "l3_init_clkdm", - .parent = &dpll_usb_m2_ck, - .recalc = &followparent_recalc, + .fixed_parent = &dpll_usb_m2_ck_hw.clk, };

-static struct clk usb_host_hs_hsic60m_p1_clk = { - .name = "usb_host_hs_hsic60m_p1_clk", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap usb_host_hs_hsic60m_p1_clk_hw = { + .clk = { + .name = "usb_host_hs_hsic60m_p1_clk", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT, .clkdm_name = "l3_init_clkdm", - .parent = &init_60m_fclk, - .recalc = &followparent_recalc, + .fixed_parent = &init_60m_fclk_hw.clk, };

-static struct clk usb_host_hs_hsic60m_p2_clk = { - .name = "usb_host_hs_hsic60m_p2_clk", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap usb_host_hs_hsic60m_p2_clk_hw = { + .clk = { + .name = "usb_host_hs_hsic60m_p2_clk", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT, .clkdm_name = "l3_init_clkdm", - .parent = &init_60m_fclk, - .recalc = &followparent_recalc, + .fixed_parent = &init_60m_fclk_hw.clk, };

-static struct clk usb_host_hs_hsic480m_p2_clk = { - .name = "usb_host_hs_hsic480m_p2_clk", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap usb_host_hs_hsic480m_p2_clk_hw = { + .clk = { + .name = "usb_host_hs_hsic480m_p2_clk", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT, .clkdm_name = "l3_init_clkdm", - .parent = &dpll_usb_m2_ck, - .recalc = &followparent_recalc, + .fixed_parent = &dpll_usb_m2_ck_hw.clk, };

-static struct clk usb_host_hs_func48mclk = { - .name = "usb_host_hs_func48mclk", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap usb_host_hs_func48mclk_hw = { + .clk = { + .name = "usb_host_hs_func48mclk", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT, .clkdm_name = "l3_init_clkdm", - .parent = &func_48mc_fclk, - .recalc = &followparent_recalc, + .fixed_parent = &func_48mc_fclk_hw.clk, };

-static struct clk usb_host_hs_fck = { - .name = "usb_host_hs_fck", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap usb_host_hs_fck_hw = { + .clk = { + .name = "usb_host_hs_fck", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, .clkdm_name = "l3_init_clkdm", - .parent = &init_60m_fclk, - .recalc = &followparent_recalc, + .fixed_parent = &init_60m_fclk_hw.clk, };

static const struct clksel otg_60m_gfclk_sel[] = { - { .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates }, - { .parent = &xclk60motg_ck, .rates = div_1_1_rates }, + { .parent = &utmi_phy_clkout_ck_hw.clk, .rates = div_1_0_rates }, + { .parent = &xclk60motg_ck_hw.clk, .rates = div_1_1_rates }, { .parent = NULL }, };

-static struct clk otg_60m_gfclk = { - .name = "otg_60m_gfclk", - .parent = &utmi_phy_clkout_ck, +static const struct clk_hw_ops otg_60m_gfclk_ops = { + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_init_clksel_parent, + .set_parent = &omap2_clksel_set_parent, +}; + +static struct clk_hw_omap otg_60m_gfclk_hw = { + .clk = { + .name = "otg_60m_gfclk", + .ops = &otg_60m_gfclk_ops, + }, + .fixed_parent = &utmi_phy_clkout_ck_hw.clk, .clksel = otg_60m_gfclk_sel, - .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_60M_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, };

-static struct clk usb_otg_hs_xclk = { - .name = "usb_otg_hs_xclk", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap usb_otg_hs_xclk_hw = { + .clk = { + .name = "usb_otg_hs_xclk", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_XCLK_SHIFT, .clkdm_name = "l3_init_clkdm", - .parent = &otg_60m_gfclk, - .recalc = &followparent_recalc, + .fixed_parent = &otg_60m_gfclk_hw.clk, };

-static struct clk usb_otg_hs_ick = { - .name = "usb_otg_hs_ick", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap usb_otg_hs_ick_hw = { + .clk = { + .name = "usb_otg_hs_ick", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, + .enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT, .clkdm_name = "l3_init_clkdm", - .parent = &l3_div_ck, - .recalc = &followparent_recalc, + .fixed_parent = &l3_div_ck_hw.clk, };

-static struct clk usb_phy_cm_clk32k = { - .name = "usb_phy_cm_clk32k", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap usb_phy_cm_clk32k_hw = { + .clk = { + .name = "usb_phy_cm_clk32k", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_ALWON_USBPHY_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_CLK32K_SHIFT, .clkdm_name = "l4_ao_clkdm", - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, + .fixed_parent = &sys_32k_ck_hw.clk, };

-static struct clk usb_tll_hs_usb_ch2_clk = { - .name = "usb_tll_hs_usb_ch2_clk", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap usb_tll_hs_usb_ch2_clk_hw = { + .clk = { + .name = "usb_tll_hs_usb_ch2_clk", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT, .clkdm_name = "l3_init_clkdm", - .parent = &init_60m_fclk, - .recalc = &followparent_recalc, + .fixed_parent = &init_60m_fclk_hw.clk, };

-static struct clk usb_tll_hs_usb_ch0_clk = { - .name = "usb_tll_hs_usb_ch0_clk", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap usb_tll_hs_usb_ch0_clk_hw = { + .clk = { + .name = "usb_tll_hs_usb_ch0_clk", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT, .clkdm_name = "l3_init_clkdm", - .parent = &init_60m_fclk, - .recalc = &followparent_recalc, + .fixed_parent = &init_60m_fclk_hw.clk, };

-static struct clk usb_tll_hs_usb_ch1_clk = { - .name = "usb_tll_hs_usb_ch1_clk", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap usb_tll_hs_usb_ch1_clk_hw = { + .clk = { + .name = "usb_tll_hs_usb_ch1_clk", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT, .clkdm_name = "l3_init_clkdm", - .parent = &init_60m_fclk, - .recalc = &followparent_recalc, + .fixed_parent = &init_60m_fclk_hw.clk, };

-static struct clk usb_tll_hs_ick = { - .name = "usb_tll_hs_ick", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap usb_tll_hs_ick_hw = { + .clk = { + .name = "usb_tll_hs_ick", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, + .enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT, .clkdm_name = "l3_init_clkdm", - .parent = &l4_div_ck, - .recalc = &followparent_recalc, + .fixed_parent = &l4_div_ck_hw.clk, };

static const struct clksel_rate div2_14to18_rates[] = { @@ -2729,103 +3509,125 @@ static const struct clksel_rate div2_14to18_rates[] = { };

static const struct clksel usim_fclk_div[] = { - { .parent = &dpll_per_m4x2_ck, .rates = div2_14to18_rates }, + { .parent = &dpll_per_m4x2_ck_hw.clk, .rates = div2_14to18_rates }, { .parent = NULL }, };

-static struct clk usim_ck = { - .name = "usim_ck", - .parent = &dpll_per_m4x2_ck, +static const struct clk_hw_ops usim_ck_ops = { + .recalc_rate = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, + .get_parent = &omap2_get_parent_fixed, +}; + +static struct clk_hw_omap usim_ck_hw = { + .clk = { + .name = "usim_ck", + .ops = &usim_ck_ops, + }, + .fixed_parent = &dpll_per_m4x2_ck_hw.clk, .clksel = usim_fclk_div, .clksel_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_DIV_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, };

-static struct clk usim_fclk = { - .name = "usim_fclk", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap usim_fclk_hw = { + .clk = { + .name = "usim_fclk", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_FCLK_SHIFT, .clkdm_name = "l4_wkup_clkdm", - .parent = &usim_ck, - .recalc = &followparent_recalc, + .fixed_parent = &usim_ck_hw.clk, };

-static struct clk usim_fck = { - .name = "usim_fck", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap usim_fck_hw = { + .clk = { + .name = "usim_fck", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, + .enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT, .clkdm_name = "l4_wkup_clkdm", - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, + .fixed_parent = &sys_32k_ck_hw.clk, };

-static struct clk wd_timer2_fck = { - .name = "wd_timer2_fck", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap wd_timer2_fck_hw = { + .clk = { + .name = "wd_timer2_fck", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, .clkdm_name = "l4_wkup_clkdm", - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, + .fixed_parent = &sys_32k_ck_hw.clk, };

-static struct clk wd_timer3_fck = { - .name = "wd_timer3_fck", - .ops = &clkops_omap2_dflt, +static struct clk_hw_omap wd_timer3_fck_hw = { + .clk = { + .name = "wd_timer3_fck", + .ops = &leaf_ck_ops, + }, .enable_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, .clkdm_name = "abe_clkdm", - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, + .fixed_parent = &sys_32k_ck_hw.clk, };

/* Remaining optional clocks */ static const struct clksel stm_clk_div_div[] = { - { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates }, + { .parent = &pmd_stm_clock_mux_ck_hw.clk, .rates = div3_1to4_rates }, { .parent = NULL }, };

-static struct clk stm_clk_div_ck = { - .name = "stm_clk_div_ck", - .parent = &pmd_stm_clock_mux_ck, +static const struct clk_hw_ops stm_clk_div_ck_ops = { + .recalc_rate = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, + .get_parent = &omap2_get_parent_fixed, +}; + +static struct clk_hw_omap stm_clk_div_ck_hw = { + .clk = { + .name = "stm_clk_div_ck", + .ops = &stm_clk_div_ck_ops, + }, + .fixed_parent = &pmd_stm_clock_mux_ck_hw.clk, .clksel = stm_clk_div_div, .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_PMD_STM_CLK_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, };

static const struct clksel trace_clk_div_div[] = { - { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates }, + { .parent = &pmd_trace_clk_mux_ck_hw.clk, .rates = div3_1to4_rates }, { .parent = NULL }, };

-static struct clk trace_clk_div_ck = { - .name = "trace_clk_div_ck", - .parent = &pmd_trace_clk_mux_ck, +static const struct clk_hw_ops trace_clk_div_ck_ops = { + .recalc_rate = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, + .get_parent = &omap2_get_parent_fixed, +}; + +static struct clk_hw_omap trace_clk_div_ck_hw = { + .clk = { + .name = "trace_clk_div_ck", + .ops = &trace_clk_div_ck_ops, + }, + .fixed_parent = &pmd_trace_clk_mux_ck_hw.clk, .clksel = trace_clk_div_div, .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, };

/* SCRM aux clk nodes */

static const struct clksel auxclk_src_sel[] = { - { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, - { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates }, - { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates }, + { .parent = &sys_clkin_ck_hw.clk, .rates = div_1_0_rates }, + { .parent = &dpll_core_m3x2_ck_hw.clk, .rates = div_1_1_rates }, + { .parent = &dpll_per_m3x2_ck_hw.clk, .rates = div_1_2_rates }, { .parent = NULL }, };

@@ -2849,260 +3651,368 @@ static const struct clksel_rate div16_1to16_rates[] = { { .div = 0 }, };

-static struct clk auxclk0_src_ck = { - .name = "auxclk0_src_ck", - .parent = &sys_clkin_ck, - .init = &omap2_init_clksel_parent, - .ops = &clkops_omap2_dflt, +static const struct clk_hw_ops auxclk0_src_ck_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_init_clksel_parent, +}; + +static struct clk_hw_omap auxclk0_src_ck_hw = { + .clk = { + .name = "auxclk0_src_ck", + .ops = &auxclk0_src_ck_ops, + }, + .fixed_parent = &sys_clkin_ck_hw.clk, .clksel = auxclk_src_sel, .clksel_reg = OMAP4_SCRM_AUXCLK0, .clksel_mask = OMAP4_SRCSELECT_MASK, - .recalc = &omap2_clksel_recalc, .enable_reg = OMAP4_SCRM_AUXCLK0, .enable_bit = OMAP4_ENABLE_SHIFT, };

static const struct clksel auxclk0_sel[] = { - { .parent = &auxclk0_src_ck, .rates = div16_1to16_rates }, + { .parent = &auxclk0_src_ck_hw.clk, .rates = div16_1to16_rates }, { .parent = NULL }, };

-static struct clk auxclk0_ck = { - .name = "auxclk0_ck", - .parent = &auxclk0_src_ck, +static const struct clk_hw_ops auxclk0_ck_ops = { + .recalc_rate = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, + .get_parent = &omap2_get_parent_fixed, +}; + +static struct clk_hw_omap auxclk0_ck_hw = { + .clk = { + .name = "auxclk0_ck", + .ops = &auxclk0_ck_ops, + }, + .fixed_parent = &auxclk0_src_ck_hw.clk, .clksel = auxclk0_sel, .clksel_reg = OMAP4_SCRM_AUXCLK0, .clksel_mask = OMAP4_CLKDIV_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, };

-static struct clk auxclk1_src_ck = { - .name = "auxclk1_src_ck", - .parent = &sys_clkin_ck, - .init = &omap2_init_clksel_parent, - .ops = &clkops_omap2_dflt, +static const struct clk_hw_ops auxclk1_src_ck_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_init_clksel_parent, +}; + +static struct clk_hw_omap auxclk1_src_ck_hw = { + .clk = { + .name = "auxclk1_src_ck", + .ops = &auxclk1_src_ck_ops, + }, + .fixed_parent = &sys_clkin_ck_hw.clk, .clksel = auxclk_src_sel, .clksel_reg = OMAP4_SCRM_AUXCLK1, .clksel_mask = OMAP4_SRCSELECT_MASK, - .recalc = &omap2_clksel_recalc, .enable_reg = OMAP4_SCRM_AUXCLK1, .enable_bit = OMAP4_ENABLE_SHIFT, };

static const struct clksel auxclk1_sel[] = { - { .parent = &auxclk1_src_ck, .rates = div16_1to16_rates }, + { .parent = &auxclk1_src_ck_hw.clk, .rates = div16_1to16_rates }, { .parent = NULL }, };

-static struct clk auxclk1_ck = { - .name = "auxclk1_ck", - .parent = &auxclk1_src_ck, +static const struct clk_hw_ops auxclk1_ck_ops = { + .recalc_rate = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, + .get_parent = &omap2_get_parent_fixed, +}; + +static struct clk_hw_omap auxclk1_ck_hw = { + .clk = { + .name = "auxclk1_ck", + .ops = &auxclk1_ck_ops, + }, + .fixed_parent = &auxclk1_src_ck_hw.clk, .clksel = auxclk1_sel, .clksel_reg = OMAP4_SCRM_AUXCLK1, .clksel_mask = OMAP4_CLKDIV_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, };

-static struct clk auxclk2_src_ck = { - .name = "auxclk2_src_ck", - .parent = &sys_clkin_ck, - .init = &omap2_init_clksel_parent, - .ops = &clkops_omap2_dflt, +static const struct clk_hw_ops auxclk2_src_ck_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_init_clksel_parent, +}; + +static struct clk_hw_omap auxclk2_src_ck_hw = { + .clk = { + .name = "auxclk2_src_ck", + .ops = &auxclk2_src_ck_ops, + }, + .fixed_parent = &sys_clkin_ck_hw.clk, .clksel = auxclk_src_sel, .clksel_reg = OMAP4_SCRM_AUXCLK2, .clksel_mask = OMAP4_SRCSELECT_MASK, - .recalc = &omap2_clksel_recalc, .enable_reg = OMAP4_SCRM_AUXCLK2, .enable_bit = OMAP4_ENABLE_SHIFT, };

static const struct clksel auxclk2_sel[] = { - { .parent = &auxclk2_src_ck, .rates = div16_1to16_rates }, + { .parent = &auxclk2_src_ck_hw.clk, .rates = div16_1to16_rates }, { .parent = NULL }, };

-static struct clk auxclk2_ck = { - .name = "auxclk2_ck", - .parent = &auxclk2_src_ck, +static const struct clk_hw_ops auxclk2_ck_ops = { + .recalc_rate = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, + .get_parent = &omap2_get_parent_fixed, +}; + +static struct clk_hw_omap auxclk2_ck_hw = { + .clk = { + .name = "auxclk2_ck", + .ops = &auxclk2_ck_ops, + }, + .fixed_parent = &auxclk2_src_ck_hw.clk, .clksel = auxclk2_sel, .clksel_reg = OMAP4_SCRM_AUXCLK2, .clksel_mask = OMAP4_CLKDIV_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, };

-static struct clk auxclk3_src_ck = { - .name = "auxclk3_src_ck", - .parent = &sys_clkin_ck, - .init = &omap2_init_clksel_parent, - .ops = &clkops_omap2_dflt, +static const struct clk_hw_ops auxclk3_src_ck_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_init_clksel_parent, +}; + +static struct clk_hw_omap auxclk3_src_ck_hw = { + .clk = { + .name = "auxclk3_src_ck", + .ops = &auxclk3_src_ck_ops, + }, + .fixed_parent = &sys_clkin_ck_hw.clk, .clksel = auxclk_src_sel, .clksel_reg = OMAP4_SCRM_AUXCLK3, .clksel_mask = OMAP4_SRCSELECT_MASK, - .recalc = &omap2_clksel_recalc, .enable_reg = OMAP4_SCRM_AUXCLK3, .enable_bit = OMAP4_ENABLE_SHIFT, };

static const struct clksel auxclk3_sel[] = { - { .parent = &auxclk3_src_ck, .rates = div16_1to16_rates }, + { .parent = &auxclk3_src_ck_hw.clk, .rates = div16_1to16_rates }, { .parent = NULL }, };

-static struct clk auxclk3_ck = { - .name = "auxclk3_ck", - .parent = &auxclk3_src_ck, +static const struct clk_hw_ops auxclk3_ck_ops = { + .recalc_rate = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, + .get_parent = &omap2_get_parent_fixed, +}; + +static struct clk_hw_omap auxclk3_ck_hw = { + .clk = { + .name = "auxclk3_ck", + .ops = &auxclk3_ck_ops, + }, + .fixed_parent = &auxclk3_src_ck_hw.clk, .clksel = auxclk3_sel, .clksel_reg = OMAP4_SCRM_AUXCLK3, .clksel_mask = OMAP4_CLKDIV_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, };

-static struct clk auxclk4_src_ck = { - .name = "auxclk4_src_ck", - .parent = &sys_clkin_ck, - .init = &omap2_init_clksel_parent, - .ops = &clkops_omap2_dflt, +static const struct clk_hw_ops auxclk4_src_ck_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_init_clksel_parent, +}; + +static struct clk_hw_omap auxclk4_src_ck_hw = { + .clk = { + .name = "auxclk4_src_ck", + .ops = &auxclk4_src_ck_ops, + }, + .fixed_parent = &sys_clkin_ck_hw.clk, .clksel = auxclk_src_sel, .clksel_reg = OMAP4_SCRM_AUXCLK4, .clksel_mask = OMAP4_SRCSELECT_MASK, - .recalc = &omap2_clksel_recalc, .enable_reg = OMAP4_SCRM_AUXCLK4, .enable_bit = OMAP4_ENABLE_SHIFT, };

static const struct clksel auxclk4_sel[] = { - { .parent = &auxclk4_src_ck, .rates = div16_1to16_rates }, + { .parent = &auxclk4_src_ck_hw.clk, .rates = div16_1to16_rates }, { .parent = NULL }, };

-static struct clk auxclk4_ck = { - .name = "auxclk4_ck", - .parent = &auxclk4_src_ck, +static const struct clk_hw_ops auxclk4_ck_ops = { + .recalc_rate = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, + .get_parent = &omap2_get_parent_fixed, +}; + +static struct clk_hw_omap auxclk4_ck_hw = { + .clk = { + .name = "auxclk4_ck", + .ops = &auxclk4_ck_ops, + }, + .fixed_parent = &auxclk4_src_ck_hw.clk, .clksel = auxclk4_sel, .clksel_reg = OMAP4_SCRM_AUXCLK4, .clksel_mask = OMAP4_CLKDIV_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, };

-static struct clk auxclk5_src_ck = { - .name = "auxclk5_src_ck", - .parent = &sys_clkin_ck, - .init = &omap2_init_clksel_parent, - .ops = &clkops_omap2_dflt, +static const struct clk_hw_ops auxclk5_src_ck_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_init_clksel_parent, +}; + +static struct clk_hw_omap auxclk5_src_ck_hw = { + .clk = { + .name = "auxclk5_src_ck", + .ops = &auxclk5_src_ck_ops, + }, + .fixed_parent = &sys_clkin_ck_hw.clk, .clksel = auxclk_src_sel, .clksel_reg = OMAP4_SCRM_AUXCLK5, .clksel_mask = OMAP4_SRCSELECT_MASK, - .recalc = &omap2_clksel_recalc, .enable_reg = OMAP4_SCRM_AUXCLK5, .enable_bit = OMAP4_ENABLE_SHIFT, };

static const struct clksel auxclk5_sel[] = { - { .parent = &auxclk5_src_ck, .rates = div16_1to16_rates }, + { .parent = &auxclk5_src_ck_hw.clk, .rates = div16_1to16_rates }, { .parent = NULL }, };

-static struct clk auxclk5_ck = { - .name = "auxclk5_ck", - .parent = &auxclk5_src_ck, +static const struct clk_hw_ops auxclk5_ck_ops = { + .recalc_rate = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, + .get_parent = &omap2_get_parent_fixed, +}; + +static struct clk_hw_omap auxclk5_ck_hw = { + .clk = { + .name = "auxclk5_ck", + .ops = &auxclk5_ck_ops, + }, + .fixed_parent = &auxclk5_src_ck_hw.clk, .clksel = auxclk5_sel, .clksel_reg = OMAP4_SCRM_AUXCLK5, .clksel_mask = OMAP4_CLKDIV_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, };

static const struct clksel auxclkreq_sel[] = { - { .parent = &auxclk0_ck, .rates = div_1_0_rates }, - { .parent = &auxclk1_ck, .rates = div_1_1_rates }, - { .parent = &auxclk2_ck, .rates = div_1_2_rates }, - { .parent = &auxclk3_ck, .rates = div_1_3_rates }, - { .parent = &auxclk4_ck, .rates = div_1_4_rates }, - { .parent = &auxclk5_ck, .rates = div_1_5_rates }, + { .parent = &auxclk0_ck_hw.clk, .rates = div_1_0_rates }, + { .parent = &auxclk1_ck_hw.clk, .rates = div_1_1_rates }, + { .parent = &auxclk2_ck_hw.clk, .rates = div_1_2_rates }, + { .parent = &auxclk3_ck_hw.clk, .rates = div_1_3_rates }, + { .parent = &auxclk4_ck_hw.clk, .rates = div_1_4_rates }, + { .parent = &auxclk5_ck_hw.clk, .rates = div_1_5_rates }, { .parent = NULL }, };

-static struct clk auxclkreq0_ck = { - .name = "auxclkreq0_ck", - .parent = &auxclk0_ck, - .init = &omap2_init_clksel_parent, - .ops = &clkops_null, - .clksel = auxclkreq_sel, +static struct clk_hw_ops auxclkreq0_ck_ops = { + .get_parent = &omap2_init_clksel_parent, + .recalc_rate = &omap2_clksel_recalc, +}; + +static struct clk_hw_omap auxclkreq0_ck_hw = { + .clk = { + .name = "auxclkreq0_ck", + .ops = &auxclkreq0_ck_ops, + }, + .fixed_parent = &auxclk0_ck_hw.clk, + .clksel = auxclkreq_sel, .clksel_reg = OMAP4_SCRM_AUXCLKREQ0, .clksel_mask = OMAP4_MAPPING_MASK, - .recalc = &omap2_clksel_recalc, };

-static struct clk auxclkreq1_ck = { - .name = "auxclkreq1_ck", - .parent = &auxclk1_ck, - .init = &omap2_init_clksel_parent, - .ops = &clkops_null, - .clksel = auxclkreq_sel, +static struct clk_hw_ops auxclkreq1_ck_ops = { + .get_parent = &omap2_init_clksel_parent, + .recalc_rate = &omap2_clksel_recalc, +}; + +static struct clk_hw_omap auxclkreq1_ck_hw = { + .clk = { + .name = "auxclkreq1_ck", + .ops = &auxclkreq1_ck_ops, + }, + .fixed_parent = &auxclk1_ck_hw.clk, + .clksel = auxclkreq_sel, .clksel_reg = OMAP4_SCRM_AUXCLKREQ1, .clksel_mask = OMAP4_MAPPING_MASK, - .recalc = &omap2_clksel_recalc, };

-static struct clk auxclkreq2_ck = { - .name = "auxclkreq2_ck", - .parent = &auxclk2_ck, - .init = &omap2_init_clksel_parent, - .ops = &clkops_null, - .clksel = auxclkreq_sel, +static struct clk_hw_ops auxclkreq2_ck_ops = { + .get_parent = &omap2_init_clksel_parent, + .recalc_rate = &omap2_clksel_recalc, +}; + +static struct clk_hw_omap auxclkreq2_ck_hw = { + .clk = { + .name = "auxclkreq2_ck", + .ops = &auxclkreq2_ck_ops, + }, + .fixed_parent = &auxclk2_ck_hw.clk, + .clksel = auxclkreq_sel, .clksel_reg = OMAP4_SCRM_AUXCLKREQ2, .clksel_mask = OMAP4_MAPPING_MASK, - .recalc = &omap2_clksel_recalc, };

-static struct clk auxclkreq3_ck = { - .name = "auxclkreq3_ck", - .parent = &auxclk3_ck, - .init = &omap2_init_clksel_parent, - .ops = &clkops_null, - .clksel = auxclkreq_sel, +static struct clk_hw_ops auxclkreq3_ck_ops = { + .get_parent = &omap2_init_clksel_parent, + .recalc_rate = &omap2_clksel_recalc, +}; + +static struct clk_hw_omap auxclkreq3_ck_hw = { + .clk = { + .name = "auxclkreq3_ck", + .ops = &auxclkreq3_ck_ops, + }, + .fixed_parent = &auxclk3_ck_hw.clk, + .clksel = auxclkreq_sel, .clksel_reg = OMAP4_SCRM_AUXCLKREQ3, .clksel_mask = OMAP4_MAPPING_MASK, - .recalc = &omap2_clksel_recalc, };

-static struct clk auxclkreq4_ck = { - .name = "auxclkreq4_ck", - .parent = &auxclk4_ck, - .init = &omap2_init_clksel_parent, - .ops = &clkops_null, - .clksel = auxclkreq_sel, +static struct clk_hw_ops auxclkreq4_ck_ops = { + .get_parent = &omap2_init_clksel_parent, + .recalc_rate = &omap2_clksel_recalc, +}; + +static struct clk_hw_omap auxclkreq4_ck_hw = { + .clk = { + .name = "auxclkreq4_ck", + .ops = &auxclkreq4_ck_ops, + }, + .fixed_parent = &auxclk4_ck_hw.clk, + .clksel = auxclkreq_sel, .clksel_reg = OMAP4_SCRM_AUXCLKREQ4, .clksel_mask = OMAP4_MAPPING_MASK, - .recalc = &omap2_clksel_recalc, };

-static struct clk auxclkreq5_ck = { - .name = "auxclkreq5_ck", - .parent = &auxclk5_ck, - .init = &omap2_init_clksel_parent, - .ops = &clkops_null, - .clksel = auxclkreq_sel, +static struct clk_hw_ops auxclkreq5_ck_ops = { + .get_parent = &omap2_init_clksel_parent, + .recalc_rate = &omap2_clksel_recalc, +}; + +static struct clk_hw_omap auxclkreq5_ck_hw = { + .clk = { + .name = "auxclkreq5_ck", + .ops = &auxclkreq5_ck_ops, + }, + .fixed_parent = &auxclk5_ck_hw.clk, + .clksel = auxclkreq_sel, .clksel_reg = OMAP4_SCRM_AUXCLKREQ5, .clksel_mask = OMAP4_MAPPING_MASK, - .recalc = &omap2_clksel_recalc, };

/* @@ -3110,333 +4020,307 @@ static struct clk auxclkreq5_ck = { */

static struct omap_clk omap44xx_clks[] = { - CLK(NULL, "extalt_clkin_ck", &extalt_clkin_ck, CK_443X), - CLK(NULL, "pad_clks_ck", &pad_clks_ck, CK_443X), - CLK(NULL, "pad_slimbus_core_clks_ck", &pad_slimbus_core_clks_ck, CK_443X), - CLK(NULL, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck, CK_443X), - CLK(NULL, "slimbus_clk", &slimbus_clk, CK_443X), - CLK(NULL, "sys_32k_ck", &sys_32k_ck, CK_443X), - CLK(NULL, "virt_12000000_ck", &virt_12000000_ck, CK_443X), - CLK(NULL, "virt_13000000_ck", &virt_13000000_ck, CK_443X), - CLK(NULL, "virt_16800000_ck", &virt_16800000_ck, CK_443X), - CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_443X), - CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_443X), - CLK(NULL, "virt_27000000_ck", &virt_27000000_ck, CK_443X), - CLK(NULL, "virt_38400000_ck", &virt_38400000_ck, CK_443X), - CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_443X), - CLK(NULL, "tie_low_clock_ck", &tie_low_clock_ck, CK_443X), - CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck, CK_443X), - CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck, CK_443X), - CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck, CK_443X), - CLK(NULL, "xclk60motg_ck", &xclk60motg_ck, CK_443X), - CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck, CK_443X), - CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck, CK_443X), - CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_443X), - CLK(NULL, "dpll_abe_x2_ck", &dpll_abe_x2_ck, CK_443X), - CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_443X), - CLK(NULL, "abe_24m_fclk", &abe_24m_fclk, CK_443X), - CLK(NULL, "abe_clk", &abe_clk, CK_443X), - CLK(NULL, "aess_fclk", &aess_fclk, CK_443X), - CLK(NULL, "dpll_abe_m3x2_ck", &dpll_abe_m3x2_ck, CK_443X), - CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck, CK_443X), - CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_443X), - CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_443X), - CLK(NULL, "dpll_core_m6x2_ck", &dpll_core_m6x2_ck, CK_443X), - CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck, CK_443X), - CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck, CK_443X), - CLK(NULL, "ddrphy_ck", &ddrphy_ck, CK_443X), - CLK(NULL, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, CK_443X), - CLK(NULL, "div_core_ck", &div_core_ck, CK_443X), - CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk, CK_443X), - CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk, CK_443X), - CLK(NULL, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck, CK_443X), - CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck, CK_443X), - CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck, CK_443X), - CLK(NULL, "dpll_core_m3x2_ck", &dpll_core_m3x2_ck, CK_443X), - CLK(NULL, "dpll_core_m7x2_ck", &dpll_core_m7x2_ck, CK_443X), - CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck, CK_443X), - CLK(NULL, "dpll_iva_ck", &dpll_iva_ck, CK_443X), - CLK(NULL, "dpll_iva_x2_ck", &dpll_iva_x2_ck, CK_443X), - CLK(NULL, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck, CK_443X), - CLK(NULL, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, CK_443X), - CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_443X), - CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_443X), - CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck, CK_443X), - CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck, CK_443X), - CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_443X), - CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_443X), - CLK(NULL, "dpll_per_x2_ck", &dpll_per_x2_ck, CK_443X), - CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, CK_443X), - CLK(NULL, "dpll_per_m3x2_ck", &dpll_per_m3x2_ck, CK_443X), - CLK(NULL, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, CK_443X), - CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, CK_443X), - CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck, CK_443X), - CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck, CK_443X), - CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_443X), - CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_443X), - CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck, CK_443X), - CLK(NULL, "dpll_usb_m2_ck", &dpll_usb_m2_ck, CK_443X), - CLK(NULL, "ducati_clk_mux_ck", &ducati_clk_mux_ck, CK_443X), - CLK(NULL, "func_12m_fclk", &func_12m_fclk, CK_443X), - CLK(NULL, "func_24m_clk", &func_24m_clk, CK_443X), - CLK(NULL, "func_24mc_fclk", &func_24mc_fclk, CK_443X), - CLK(NULL, "func_48m_fclk", &func_48m_fclk, CK_443X), - CLK(NULL, "func_48mc_fclk", &func_48mc_fclk, CK_443X), - CLK(NULL, "func_64m_fclk", &func_64m_fclk, CK_443X), - CLK(NULL, "func_96m_fclk", &func_96m_fclk, CK_443X), - CLK(NULL, "init_60m_fclk", &init_60m_fclk, CK_443X), - CLK(NULL, "l3_div_ck", &l3_div_ck, CK_443X), - CLK(NULL, "l4_div_ck", &l4_div_ck, CK_443X), - CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_443X), - CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_443X), - CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_443X), - CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_443X), - CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X), - CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X), - CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X), - CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X), - CLK(NULL, "aes1_fck", &aes1_fck, CK_443X), - CLK(NULL, "aes2_fck", &aes2_fck, CK_443X), - CLK(NULL, "aess_fck", &aess_fck, CK_443X), - CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X), - CLK(NULL, "bandgap_ts_fclk", &bandgap_ts_fclk, CK_446X), - CLK(NULL, "des3des_fck", &des3des_fck, CK_443X), - CLK(NULL, "div_ts_ck", &div_ts_ck, CK_446X), - CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X), - CLK(NULL, "dmic_fck", &dmic_fck, CK_443X), - CLK(NULL, "dsp_fck", &dsp_fck, CK_443X), - CLK(NULL, "dss_sys_clk", &dss_sys_clk, CK_443X), - CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X), - CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X), - CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X), - CLK("omapdss_dss", "ick", &dss_fck, CK_443X), - CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X), - CLK(NULL, "emif1_fck", &emif1_fck, CK_443X), - CLK(NULL, "emif2_fck", &emif2_fck, CK_443X), - CLK(NULL, "fdif_fck", &fdif_fck, CK_443X), - CLK(NULL, "fpka_fck", &fpka_fck, CK_443X), - CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_443X), - CLK(NULL, "gpio1_ick", &gpio1_ick, CK_443X), - CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_443X), - CLK(NULL, "gpio2_ick", &gpio2_ick, CK_443X), - CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_443X), - CLK(NULL, "gpio3_ick", &gpio3_ick, CK_443X), - CLK(NULL, "gpio4_dbclk", &gpio4_dbclk, CK_443X), - CLK(NULL, "gpio4_ick", &gpio4_ick, CK_443X), - CLK(NULL, "gpio5_dbclk", &gpio5_dbclk, CK_443X), - CLK(NULL, "gpio5_ick", &gpio5_ick, CK_443X), - CLK(NULL, "gpio6_dbclk", &gpio6_dbclk, CK_443X), - CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X), - CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X), - CLK(NULL, "gpu_fck", &gpu_fck, CK_443X), - CLK(NULL, "hdq1w_fck", &hdq1w_fck, CK_443X), - CLK(NULL, "hsi_fck", &hsi_fck, CK_443X), - CLK(NULL, "i2c1_fck", &i2c1_fck, CK_443X), - CLK(NULL, "i2c2_fck", &i2c2_fck, CK_443X), - CLK(NULL, "i2c3_fck", &i2c3_fck, CK_443X), - CLK(NULL, "i2c4_fck", &i2c4_fck, CK_443X), - CLK(NULL, "ipu_fck", &ipu_fck, CK_443X), - CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X), - CLK(NULL, "iss_fck", &iss_fck, CK_443X), - CLK(NULL, "iva_fck", &iva_fck, CK_443X), - CLK(NULL, "kbd_fck", &kbd_fck, CK_443X), - CLK(NULL, "l3_instr_ick", &l3_instr_ick, CK_443X), - CLK(NULL, "l3_main_3_ick", &l3_main_3_ick, CK_443X), - CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X), - CLK(NULL, "mcasp_fck", &mcasp_fck, CK_443X), - CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X), - CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_443X), - CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_443X), - CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_443X), - CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_443X), - CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_443X), - CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X), - CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_443X), - CLK(NULL, "mcpdm_fck", &mcpdm_fck, CK_443X), - CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_443X), - CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_443X), - CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_443X), - CLK(NULL, "mcspi4_fck", &mcspi4_fck, CK_443X), - CLK(NULL, "mmc1_fck", &mmc1_fck, CK_443X), - CLK(NULL, "mmc2_fck", &mmc2_fck, CK_443X), - CLK(NULL, "mmc3_fck", &mmc3_fck, CK_443X), - CLK(NULL, "mmc4_fck", &mmc4_fck, CK_443X), - CLK(NULL, "mmc5_fck", &mmc5_fck, CK_443X), - CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X), - CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X), - CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X), - CLK("omap_rng", "ick", &rng_ick, CK_443X), - CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X), - CLK(NULL, "sl2if_ick", &sl2if_ick, CK_443X), - CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1, CK_443X), - CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0, CK_443X), - CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2, CK_443X), - CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk, CK_443X), - CLK(NULL, "slimbus1_fck", &slimbus1_fck, CK_443X), - CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1, CK_443X), - CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0, CK_443X), - CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk, CK_443X), - CLK(NULL, "slimbus2_fck", &slimbus2_fck, CK_443X), - CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_443X), - CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_443X), - CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck, CK_443X), - CLK(NULL, "gpt1_fck", &timer1_fck, CK_443X), - CLK(NULL, "gpt10_fck", &timer10_fck, CK_443X), - CLK(NULL, "gpt11_fck", &timer11_fck, CK_443X), - CLK(NULL, "gpt2_fck", &timer2_fck, CK_443X), - CLK(NULL, "gpt3_fck", &timer3_fck, CK_443X), - CLK(NULL, "gpt4_fck", &timer4_fck, CK_443X), - CLK(NULL, "gpt5_fck", &timer5_fck, CK_443X), - CLK(NULL, "gpt6_fck", &timer6_fck, CK_443X), - CLK(NULL, "gpt7_fck", &timer7_fck, CK_443X), - CLK(NULL, "gpt8_fck", &timer8_fck, CK_443X), - CLK(NULL, "gpt9_fck", &timer9_fck, CK_443X), - CLK(NULL, "uart1_fck", &uart1_fck, CK_443X), - CLK(NULL, "uart2_fck", &uart2_fck, CK_443X), - CLK(NULL, "uart3_fck", &uart3_fck, CK_443X), - CLK(NULL, "uart4_fck", &uart4_fck, CK_443X), - CLK("usbhs-omap.0", "fs_fck", &usb_host_fs_fck, CK_443X), - CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X), - CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X), - CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_443X), - CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk, CK_443X), - CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk, CK_443X), - CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk, CK_443X), - CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk, CK_443X), - CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X), - CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X), - CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X), - CLK("usbhs-omap.0", "hs_fck", &usb_host_hs_fck, CK_443X), - CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X), - CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X), - CLK("musb-omap2430", "ick", &usb_otg_hs_ick, CK_443X), - CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k, CK_443X), - CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X), - CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X), - CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X), - CLK("usbhs-omap.0", "usbtll_ick", &usb_tll_hs_ick, CK_443X), - CLK(NULL, "usim_ck", &usim_ck, CK_443X), - CLK(NULL, "usim_fclk", &usim_fclk, CK_443X), - CLK(NULL, "usim_fck", &usim_fck, CK_443X), - CLK(NULL, "wd_timer2_fck", &wd_timer2_fck, CK_443X), - CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X), - CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X), - CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X), - CLK(NULL, "auxclk0_src_ck", &auxclk0_src_ck, CK_443X), - CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_443X), - CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_443X), - CLK(NULL, "auxclk1_src_ck", &auxclk1_src_ck, CK_443X), - CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X), - CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_443X), - CLK(NULL, "auxclk2_src_ck", &auxclk2_src_ck, CK_443X), - CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X), - CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_443X), - CLK(NULL, "auxclk3_src_ck", &auxclk3_src_ck, CK_443X), - CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X), - CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_443X), - CLK(NULL, "auxclk4_src_ck", &auxclk4_src_ck, CK_443X), - CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X), - CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_443X), - CLK(NULL, "auxclk5_src_ck", &auxclk5_src_ck, CK_443X), - CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X), - CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X), - CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X), - CLK(NULL, "gpt1_ick", &dummy_ck, CK_443X), - CLK(NULL, "gpt2_ick", &dummy_ck, CK_443X), - CLK(NULL, "gpt3_ick", &dummy_ck, CK_443X), - CLK(NULL, "gpt4_ick", &dummy_ck, CK_443X), - CLK(NULL, "gpt5_ick", &dummy_ck, CK_443X), - CLK(NULL, "gpt6_ick", &dummy_ck, CK_443X), - CLK(NULL, "gpt7_ick", &dummy_ck, CK_443X), - CLK(NULL, "gpt8_ick", &dummy_ck, CK_443X), - CLK(NULL, "gpt9_ick", &dummy_ck, CK_443X), - CLK(NULL, "gpt10_ick", &dummy_ck, CK_443X), - CLK(NULL, "gpt11_ick", &dummy_ck, CK_443X), - CLK("omap_i2c.1", "ick", &dummy_ck, CK_443X), - CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X), - CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X), - CLK("omap_i2c.4", "ick", &dummy_ck, CK_443X), - CLK(NULL, "mailboxes_ick", &dummy_ck, CK_443X), - CLK("omap_hsmmc.0", "ick", &dummy_ck, CK_443X), - CLK("omap_hsmmc.1", "ick", &dummy_ck, CK_443X), - CLK("omap_hsmmc.2", "ick", &dummy_ck, CK_443X), - CLK("omap_hsmmc.3", "ick", &dummy_ck, CK_443X), - CLK("omap_hsmmc.4", "ick", &dummy_ck, CK_443X), - CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_443X), - CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X), - CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X), - CLK("omap-mcbsp.4", "ick", &dummy_ck, CK_443X), - CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_443X), - CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_443X), - CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_443X), - CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_443X), - CLK(NULL, "uart1_ick", &dummy_ck, CK_443X), - CLK(NULL, "uart2_ick", &dummy_ck, CK_443X), - CLK(NULL, "uart3_ick", &dummy_ck, CK_443X), - CLK(NULL, "uart4_ick", &dummy_ck, CK_443X), - CLK("usbhs-omap.0", "usbhost_ick", &dummy_ck, CK_443X), - CLK("usbhs-omap.0", "usbtll_fck", &dummy_ck, CK_443X), - CLK("omap_wdt", "ick", &dummy_ck, CK_443X), - CLK("omap_timer.1", "32k_ck", &sys_32k_ck, CK_443X), - CLK("omap_timer.2", "32k_ck", &sys_32k_ck, CK_443X), - CLK("omap_timer.3", "32k_ck", &sys_32k_ck, CK_443X), - CLK("omap_timer.4", "32k_ck", &sys_32k_ck, CK_443X), - CLK("omap_timer.5", "32k_ck", &sys_32k_ck, CK_443X), - CLK("omap_timer.6", "32k_ck", &sys_32k_ck, CK_443X), - CLK("omap_timer.7", "32k_ck", &sys_32k_ck, CK_443X), - CLK("omap_timer.8", "32k_ck", &sys_32k_ck, CK_443X), - CLK("omap_timer.9", "32k_ck", &sys_32k_ck, CK_443X), - CLK("omap_timer.10", "32k_ck", &sys_32k_ck, CK_443X), - CLK("omap_timer.11", "32k_ck", &sys_32k_ck, CK_443X), - CLK("omap_timer.1", "sys_ck", &sys_clkin_ck, CK_443X), - CLK("omap_timer.2", "sys_ck", &sys_clkin_ck, CK_443X), - CLK("omap_timer.3", "sys_ck", &sys_clkin_ck, CK_443X), - CLK("omap_timer.4", "sys_ck", &sys_clkin_ck, CK_443X), - CLK("omap_timer.9", "sys_ck", &sys_clkin_ck, CK_443X), - CLK("omap_timer.10", "sys_ck", &sys_clkin_ck, CK_443X), - CLK("omap_timer.11", "sys_ck", &sys_clkin_ck, CK_443X), - CLK("omap_timer.5", "sys_ck", &syc_clk_div_ck, CK_443X), - CLK("omap_timer.6", "sys_ck", &syc_clk_div_ck, CK_443X), - CLK("omap_timer.7", "sys_ck", &syc_clk_div_ck, CK_443X), - CLK("omap_timer.8", "sys_ck", &syc_clk_div_ck, CK_443X), + CLK(NULL, "extalt_clkin_ck", &extalt_clkin_ck_hw.clk, CK_443X), + CLK(NULL, "pad_clks_ck", &pad_clks_ck_hw.clk, CK_443X), + CLK(NULL, "pad_slimbus_core_clks_ck", &pad_slimbus_core_clks_ck_hw.clk, CK_443X), + CLK(NULL, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck_hw.clk, CK_443X), + CLK(NULL, "slimbus_clk", &slimbus_clk_hw.clk, CK_443X), + CLK(NULL, "sys_32k_ck", &sys_32k_ck_hw.clk, CK_443X), + CLK(NULL, "virt_12000000_ck", &virt_12000000_ck_hw.clk, CK_443X), + CLK(NULL, "virt_13000000_ck", &virt_13000000_ck_hw.clk, CK_443X), + CLK(NULL, "virt_16800000_ck", &virt_16800000_ck_hw.clk, CK_443X), + CLK(NULL, "virt_19200000_ck", &virt_19200000_ck_hw.clk, CK_443X), + CLK(NULL, "virt_26000000_ck", &virt_26000000_ck_hw.clk, CK_443X), + CLK(NULL, "virt_27000000_ck", &virt_27000000_ck_hw.clk, CK_443X), + CLK(NULL, "virt_38400000_ck", &virt_38400000_ck_hw.clk, CK_443X), + CLK(NULL, "sys_clkin_ck", &sys_clkin_ck_hw.clk, CK_443X), + CLK(NULL, "tie_low_clock_ck", &tie_low_clock_ck_hw.clk, CK_443X), + CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck_hw.clk, CK_443X), + CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck_hw.clk, CK_443X), + CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck_hw.clk, CK_443X), + CLK(NULL, "xclk60motg_ck", &xclk60motg_ck_hw.clk, CK_443X), + CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck_hw.clk, CK_443X), + CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck_hw.clk, CK_443X), + CLK(NULL, "dpll_abe_ck", &dpll_abe_ck_hw.clk, CK_443X), + CLK(NULL, "dpll_abe_x2_ck", &dpll_abe_x2_ck_hw.clk, CK_443X), + CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck_hw.clk, CK_443X), + CLK(NULL, "abe_24m_fclk", &abe_24m_fclk_hw.clk, CK_443X), + CLK(NULL, "abe_clk", &abe_clk_hw.clk, CK_443X), + CLK(NULL, "aess_fclk", &aess_fclk_hw.clk, CK_443X), + CLK(NULL, "dpll_abe_m3x2_ck", &dpll_abe_m3x2_ck_hw.clk, CK_443X), + CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck_hw.clk, CK_443X), + CLK(NULL, "dpll_core_ck", &dpll_core_ck_hw.clk, CK_443X), + CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck_hw.clk, CK_443X), + CLK(NULL, "dpll_core_m6x2_ck", &dpll_core_m6x2_ck_hw.clk, CK_443X), + CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck_hw.clk, CK_443X), + CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck_hw.clk, CK_443X), + CLK(NULL, "ddrphy_ck", &ddrphy_ck_hw.clk, CK_443X), + CLK(NULL, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck_hw.clk, CK_443X), + CLK(NULL, "div_core_ck", &div_core_ck_hw.clk, CK_443X), + CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk_hw.clk, CK_443X), + CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk_hw.clk, CK_443X), + CLK(NULL, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck_hw.clk, CK_443X), + CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck_hw.clk, CK_443X), + CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck_hw.clk, CK_443X), + CLK(NULL, "dpll_core_m3x2_ck", &dpll_core_m3x2_ck_hw.clk, CK_443X), + CLK(NULL, "dpll_core_m7x2_ck", &dpll_core_m7x2_ck_hw.clk, CK_443X), + CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck_hw.clk, CK_443X), + CLK(NULL, "dpll_iva_ck", &dpll_iva_ck_hw.clk, CK_443X), + CLK(NULL, "dpll_iva_x2_ck", &dpll_iva_x2_ck_hw.clk, CK_443X), + CLK(NULL, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck_hw.clk, CK_443X), + CLK(NULL, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck_hw.clk, CK_443X), + CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck_hw.clk, CK_443X), + CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck_hw.clk, CK_443X), + CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck_hw.clk, CK_443X), + CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck_hw.clk, CK_443X), + CLK(NULL, "dpll_per_ck", &dpll_per_ck_hw.clk, CK_443X), + CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck_hw.clk, CK_443X), + CLK(NULL, "dpll_per_x2_ck", &dpll_per_x2_ck_hw.clk, CK_443X), + CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck_hw.clk, CK_443X), + CLK(NULL, "dpll_per_m3x2_ck", &dpll_per_m3x2_ck_hw.clk, CK_443X), + CLK(NULL, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck_hw.clk, CK_443X), + CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck_hw.clk, CK_443X), + CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck_hw.clk, CK_443X), + CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck_hw.clk, CK_443X), + CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck_hw.clk, CK_443X), + CLK(NULL, "dpll_usb_ck", &dpll_usb_ck_hw.clk, CK_443X), + CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck_hw.clk, CK_443X), + CLK(NULL, "dpll_usb_m2_ck", &dpll_usb_m2_ck_hw.clk, CK_443X), + CLK(NULL, "ducati_clk_mux_ck", &ducati_clk_mux_ck_hw.clk, CK_443X), + CLK(NULL, "func_12m_fclk", &func_12m_fclk_hw.clk, CK_443X), + CLK(NULL, "func_24m_clk", &func_24m_clk_hw.clk, CK_443X), + CLK(NULL, "func_24mc_fclk", &func_24mc_fclk_hw.clk, CK_443X), + CLK(NULL, "func_48m_fclk", &func_48m_fclk_hw.clk, CK_443X), + CLK(NULL, "func_48mc_fclk", &func_48mc_fclk_hw.clk, CK_443X), + CLK(NULL, "func_64m_fclk", &func_64m_fclk_hw.clk, CK_443X), + CLK(NULL, "func_96m_fclk", &func_96m_fclk_hw.clk, CK_443X), + CLK(NULL, "init_60m_fclk", &init_60m_fclk_hw.clk, CK_443X), + CLK(NULL, "l3_div_ck", &l3_div_ck_hw.clk, CK_443X), + CLK(NULL, "l4_div_ck", &l4_div_ck_hw.clk, CK_443X), + CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck_hw.clk, CK_443X), + CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck_hw.clk, CK_443X), + CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk_hw.clk, CK_443X), + CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk_hw.clk, CK_443X), + CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk_hw.clk, CK_443X), + CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck_hw.clk, CK_443X), + CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck_hw.clk, CK_443X), + CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck_hw.clk, CK_443X), + CLK(NULL, "aes1_fck", &aes1_fck_hw.clk, CK_443X), + CLK(NULL, "aes2_fck", &aes2_fck_hw.clk, CK_443X), + CLK(NULL, "aess_fck", &aess_fck_hw.clk, CK_443X), + CLK(NULL, "bandgap_fclk", &bandgap_fclk_hw.clk, CK_443X), + CLK(NULL, "des3des_fck", &des3des_fck_hw.clk, CK_443X), + CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck_hw.clk, CK_443X), + CLK(NULL, "dmic_fck", &dmic_fck_hw.clk, CK_443X), + CLK(NULL, "dsp_fck", &dsp_fck_hw.clk, CK_443X), + CLK(NULL, "dss_sys_clk", &dss_sys_clk_hw.clk, CK_443X), + CLK(NULL, "dss_tv_clk", &dss_tv_clk_hw.clk, CK_443X), + CLK(NULL, "dss_dss_clk", &dss_dss_clk_hw.clk, CK_443X), + CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk_hw.clk, CK_443X), + CLK("omapdss_dss", "ick", &dss_fck_hw.clk, CK_443X), + CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck_hw.clk, CK_443X), + CLK(NULL, "emif1_fck", &emif1_fck_hw.clk, CK_443X), + CLK(NULL, "emif2_fck", &emif2_fck_hw.clk, CK_443X), + CLK(NULL, "fdif_fck", &fdif_fck_hw.clk, CK_443X), + CLK(NULL, "fpka_fck", &fpka_fck_hw.clk, CK_443X), + CLK(NULL, "gpio1_dbclk", &gpio1_dbclk_hw.clk, CK_443X), + CLK(NULL, "gpio1_ick", &gpio1_ick_hw.clk, CK_443X), + CLK(NULL, "gpio2_dbclk", &gpio2_dbclk_hw.clk, CK_443X), + CLK(NULL, "gpio2_ick", &gpio2_ick_hw.clk, CK_443X), + CLK(NULL, "gpio3_dbclk", &gpio3_dbclk_hw.clk, CK_443X), + CLK(NULL, "gpio3_ick", &gpio3_ick_hw.clk, CK_443X), + CLK(NULL, "gpio4_dbclk", &gpio4_dbclk_hw.clk, CK_443X), + CLK(NULL, "gpio4_ick", &gpio4_ick_hw.clk, CK_443X), + CLK(NULL, "gpio5_dbclk", &gpio5_dbclk_hw.clk, CK_443X), + CLK(NULL, "gpio5_ick", &gpio5_ick_hw.clk, CK_443X), + CLK(NULL, "gpio6_dbclk", &gpio6_dbclk_hw.clk, CK_443X), + CLK(NULL, "gpio6_ick", &gpio6_ick_hw.clk, CK_443X), + CLK(NULL, "gpmc_ick", &gpmc_ick_hw.clk, CK_443X), + CLK(NULL, "gpu_fck", &gpu_fck_hw.clk, CK_443X), + CLK(NULL, "hdq1w_fck", &hdq1w_fck_hw.clk, CK_443X), + CLK(NULL, "hsi_fck", &hsi_fck_hw.clk, CK_443X), + CLK(NULL, "i2c1_fck", &i2c1_fck_hw.clk, CK_443X), + CLK(NULL, "i2c2_fck", &i2c2_fck_hw.clk, CK_443X), + CLK(NULL, "i2c3_fck", &i2c3_fck_hw.clk, CK_443X), + CLK(NULL, "i2c4_fck", &i2c4_fck_hw.clk, CK_443X), + CLK(NULL, "ipu_fck", &ipu_fck_hw.clk, CK_443X), + CLK(NULL, "iss_ctrlclk", &iss_ctrlclk_hw.clk, CK_443X), + CLK(NULL, "iss_fck", &iss_fck_hw.clk, CK_443X), + CLK(NULL, "iva_fck", &iva_fck_hw.clk, CK_443X), + CLK(NULL, "kbd_fck", &kbd_fck_hw.clk, CK_443X), + CLK(NULL, "l3_instr_ick", &l3_instr_ick_hw.clk, CK_443X), + CLK(NULL, "l3_main_3_ick", &l3_main_3_ick_hw.clk, CK_443X), + CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck_hw.clk, CK_443X), + CLK(NULL, "mcasp_fck", &mcasp_fck_hw.clk, CK_443X), + CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck_hw.clk, CK_443X), + CLK(NULL, "mcbsp1_fck", &mcbsp1_fck_hw.clk, CK_443X), + CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck_hw.clk, CK_443X), + CLK(NULL, "mcbsp2_fck", &mcbsp2_fck_hw.clk, CK_443X), + CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck_hw.clk, CK_443X), + CLK(NULL, "mcbsp3_fck", &mcbsp3_fck_hw.clk, CK_443X), + CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck_hw.clk, CK_443X), + CLK(NULL, "mcbsp4_fck", &mcbsp4_fck_hw.clk, CK_443X), + CLK(NULL, "mcpdm_fck", &mcpdm_fck_hw.clk, CK_443X), + CLK(NULL, "mcspi1_fck", &mcspi1_fck_hw.clk, CK_443X), + CLK(NULL, "mcspi2_fck", &mcspi2_fck_hw.clk, CK_443X), + CLK(NULL, "mcspi3_fck", &mcspi3_fck_hw.clk, CK_443X), + CLK(NULL, "mcspi4_fck", &mcspi4_fck_hw.clk, CK_443X), + CLK(NULL, "mmc1_fck", &mmc1_fck_hw.clk, CK_443X), + CLK(NULL, "mmc2_fck", &mmc2_fck_hw.clk, CK_443X), + CLK(NULL, "mmc3_fck", &mmc3_fck_hw.clk, CK_443X), + CLK(NULL, "mmc4_fck", &mmc4_fck_hw.clk, CK_443X), + CLK(NULL, "mmc5_fck", &mmc5_fck_hw.clk, CK_443X), + CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m_hw.clk, CK_443X), + CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick_hw.clk, CK_443X), + CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick_hw.clk, CK_443X), + CLK("omap_rng", "ick", &rng_ick_hw.clk, CK_443X), + CLK(NULL, "sha2md5_fck", &sha2md5_fck_hw.clk, CK_443X), + CLK(NULL, "sl2if_ick", &sl2if_ick_hw.clk, CK_443X), + CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1_hw.clk, CK_443X), + CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0_hw.clk, CK_443X), + CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2_hw.clk, CK_443X), + CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk_hw.clk, CK_443X), + CLK(NULL, "slimbus1_fck", &slimbus1_fck_hw.clk, CK_443X), + CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1_hw.clk, CK_443X), + CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0_hw.clk, CK_443X), + CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk_hw.clk, CK_443X), + CLK(NULL, "slimbus2_fck", &slimbus2_fck_hw.clk, CK_443X), + CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck_hw.clk, CK_443X), + CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck_hw.clk, CK_443X), + CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck_hw.clk, CK_443X), + CLK(NULL, "gpt1_fck", &timer1_fck_hw.clk, CK_443X), + CLK(NULL, "gpt10_fck", &timer10_fck_hw.clk, CK_443X), + CLK(NULL, "gpt11_fck", &timer11_fck_hw.clk, CK_443X), + CLK(NULL, "gpt2_fck", &timer2_fck_hw.clk, CK_443X), + CLK(NULL, "gpt3_fck", &timer3_fck_hw.clk, CK_443X), + CLK(NULL, "gpt4_fck", &timer4_fck_hw.clk, CK_443X), + CLK(NULL, "gpt5_fck", &timer5_fck_hw.clk, CK_443X), + CLK(NULL, "gpt6_fck", &timer6_fck_hw.clk, CK_443X), + CLK(NULL, "gpt7_fck", &timer7_fck_hw.clk, CK_443X), + CLK(NULL, "gpt8_fck", &timer8_fck_hw.clk, CK_443X), + CLK(NULL, "gpt9_fck", &timer9_fck_hw.clk, CK_443X), + CLK(NULL, "uart1_fck", &uart1_fck_hw.clk, CK_443X), + CLK(NULL, "uart2_fck", &uart2_fck_hw.clk, CK_443X), + CLK(NULL, "uart3_fck", &uart3_fck_hw.clk, CK_443X), + CLK(NULL, "uart4_fck", &uart4_fck_hw.clk, CK_443X), + CLK("usbhs-omap.0", "fs_fck", &usb_host_fs_fck_hw.clk, CK_443X), + CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk_hw.clk, CK_443X), + CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk_hw.clk, CK_443X), + CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk_hw.clk, CK_443X), + CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk_hw.clk, CK_443X), + CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk_hw.clk, CK_443X), + CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk_hw.clk, CK_443X), + CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk_hw.clk, CK_443X), + CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk_hw.clk, CK_443X), + CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk_hw.clk, CK_443X), + CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk_hw.clk, CK_443X), + CLK("usbhs-omap.0", "hs_fck", &usb_host_hs_fck_hw.clk, CK_443X), + CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk_hw.clk, CK_443X), + CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk_hw.clk, CK_443X), + CLK("musb-omap2430", "ick", &usb_otg_hs_ick_hw.clk, CK_443X), + CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k_hw.clk, CK_443X), + CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk_hw.clk, CK_443X), + CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk_hw.clk, CK_443X), + CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk_hw.clk, CK_443X), + CLK("usbhs-omap.0", "usbtll_ick", &usb_tll_hs_ick_hw.clk, CK_443X), + CLK(NULL, "usim_ck", &usim_ck_hw.clk, CK_443X), + CLK(NULL, "usim_fclk", &usim_fclk_hw.clk, CK_443X), + CLK(NULL, "usim_fck", &usim_fck_hw.clk, CK_443X), + CLK(NULL, "wd_timer2_fck", &wd_timer2_fck_hw.clk, CK_443X), + CLK(NULL, "wd_timer3_fck", &wd_timer3_fck_hw.clk, CK_443X), + CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck_hw.clk, CK_443X), + CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck_hw.clk, CK_443X), + CLK(NULL, "auxclk0_src_ck", &auxclk0_src_ck_hw.clk, CK_443X), + CLK(NULL, "auxclk0_ck", &auxclk0_ck_hw.clk, CK_443X), + CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck_hw.clk, CK_443X), + CLK(NULL, "auxclk1_src_ck", &auxclk1_src_ck_hw.clk, CK_443X), + CLK(NULL, "auxclk1_ck", &auxclk1_ck_hw.clk, CK_443X), + CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck_hw.clk, CK_443X), + CLK(NULL, "auxclk2_src_ck", &auxclk2_src_ck_hw.clk, CK_443X), + CLK(NULL, "auxclk2_ck", &auxclk2_ck_hw.clk, CK_443X), + CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck_hw.clk, CK_443X), + CLK(NULL, "auxclk3_src_ck", &auxclk3_src_ck_hw.clk, CK_443X), + CLK(NULL, "auxclk3_ck", &auxclk3_ck_hw.clk, CK_443X), + CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck_hw.clk, CK_443X), + CLK(NULL, "auxclk4_src_ck", &auxclk4_src_ck_hw.clk, CK_443X), + CLK(NULL, "auxclk4_ck", &auxclk4_ck_hw.clk, CK_443X), + CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck_hw.clk, CK_443X), + CLK(NULL, "auxclk5_src_ck", &auxclk5_src_ck_hw.clk, CK_443X), + CLK(NULL, "auxclk5_ck", &auxclk5_ck_hw.clk, CK_443X), + CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck_hw.clk, CK_443X), + CLK(NULL, "gpmc_ck", &dummy_ck_hw.clk, CK_443X), + CLK(NULL, "gpt1_ick", &dummy_ck_hw.clk, CK_443X), + CLK(NULL, "gpt2_ick", &dummy_ck_hw.clk, CK_443X), + CLK(NULL, "gpt3_ick", &dummy_ck_hw.clk, CK_443X), + CLK(NULL, "gpt4_ick", &dummy_ck_hw.clk, CK_443X), + CLK(NULL, "gpt5_ick", &dummy_ck_hw.clk, CK_443X), + CLK(NULL, "gpt6_ick", &dummy_ck_hw.clk, CK_443X), + CLK(NULL, "gpt7_ick", &dummy_ck_hw.clk, CK_443X), + CLK(NULL, "gpt8_ick", &dummy_ck_hw.clk, CK_443X), + CLK(NULL, "gpt9_ick", &dummy_ck_hw.clk, CK_443X), + CLK(NULL, "gpt10_ick", &dummy_ck_hw.clk, CK_443X), + CLK(NULL, "gpt11_ick", &dummy_ck_hw.clk, CK_443X), + CLK("omap_i2c.1", "ick", &dummy_ck_hw.clk, CK_443X), + CLK("omap_i2c.2", "ick", &dummy_ck_hw.clk, CK_443X), + CLK("omap_i2c.3", "ick", &dummy_ck_hw.clk, CK_443X), + CLK("omap_i2c.4", "ick", &dummy_ck_hw.clk, CK_443X), + CLK(NULL, "mailboxes_ick", &dummy_ck_hw.clk, CK_443X), + CLK("omap_hsmmc.0", "ick", &dummy_ck_hw.clk, CK_443X), + CLK("omap_hsmmc.1", "ick", &dummy_ck_hw.clk, CK_443X), + CLK("omap_hsmmc.2", "ick", &dummy_ck_hw.clk, CK_443X), + CLK("omap_hsmmc.3", "ick", &dummy_ck_hw.clk, CK_443X), + CLK("omap_hsmmc.4", "ick", &dummy_ck_hw.clk, CK_443X), + CLK("omap-mcbsp.1", "ick", &dummy_ck_hw.clk, CK_443X), + CLK("omap-mcbsp.2", "ick", &dummy_ck_hw.clk, CK_443X), + CLK("omap-mcbsp.3", "ick", &dummy_ck_hw.clk, CK_443X), + CLK("omap-mcbsp.4", "ick", &dummy_ck_hw.clk, CK_443X), + CLK("omap2_mcspi.1", "ick", &dummy_ck_hw.clk, CK_443X), + CLK("omap2_mcspi.2", "ick", &dummy_ck_hw.clk, CK_443X), + CLK("omap2_mcspi.3", "ick", &dummy_ck_hw.clk, CK_443X), + CLK("omap2_mcspi.4", "ick", &dummy_ck_hw.clk, CK_443X), + CLK(NULL, "uart1_ick", &dummy_ck_hw.clk, CK_443X), + CLK(NULL, "uart2_ick", &dummy_ck_hw.clk, CK_443X), + CLK(NULL, "uart3_ick", &dummy_ck_hw.clk, CK_443X), + CLK(NULL, "uart4_ick", &dummy_ck_hw.clk, CK_443X), + CLK("usbhs-omap.0", "usbhost_ick", &dummy_ck_hw.clk, CK_443X), + CLK("usbhs-omap.0", "usbtll_fck", &dummy_ck_hw.clk, CK_443X), + CLK("omap_wdt", "ick", &dummy_ck_hw.clk, CK_443X), };

int __init omap4xxx_clk_init(void) { + struct clk_hw_omap *oclk; struct omap_clk *c; - u32 cpu_clkflg; + u32 cpu_clkflg = 0;

- if (cpu_is_omap443x()) { + if (cpu_is_omap44xx()) { cpu_mask = RATE_IN_4430; cpu_clkflg = CK_443X; } else if (cpu_is_omap446x()) { - cpu_mask = RATE_IN_4460 | RATE_IN_4430; - cpu_clkflg = CK_446X | CK_443X; + cpu_mask = RATE_IN_4460; + cpu_clkflg = CK_446X; } else { return 0; }

- clk_init(&omap2_clk_functions); - - /* - * Must stay commented until all OMAP SoC drivers are - * converted to runtime PM, or drivers may start crashing - * - * omap2_clk_disable_clkdm_control(); - */ - - for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks); - c++) - clk_preinit(c->lk.clk); - for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks); c++) if (c->cpu & cpu_clkflg) { clkdev_add(&c->lk); - clk_register(c->lk.clk); + + oclk = to_clk_hw_omap(c->lk.clk); + if (oclk->node.next || oclk->node.prev) { + continue; + } else { + mutex_lock(&omap_clocks_mutex); + list_add(&oclk->node, &omap_clocks); + mutex_unlock(&omap_clocks_mutex); + clk_init(NULL, c->lk.clk); + } omap2_init_clk_clkdm(c->lk.clk); }

+#if 0 /* Disable autoidle on all clocks; let the PM code enable it later */ omap_clk_disable_autoidle_all();

@@ -3447,6 +4331,7 @@ int __init omap4xxx_clk_init(void) * enable other clocks as necessary */ clk_enable_init_clocks(); +#endif

return 0; }

-- 1.7.5.4

Paul Walmsley

4:27 a.m.

New subject: [PATCH 3/7] HACK: omap: convert 44xx data to common struct clk

On Tue, 13 Dec 2011, Mike Turquette wrote:

...

omap_clk_get_by_name must die.

You do realize that it exists for a reason? That hardware clock names don't have anything to do with the Linux device model?

- Paul

Turquette, Mike

4:44 a.m.

New subject: [PATCH 3/7] HACK: omap: convert 44xx data to common struct clk

On Tue, Dec 13, 2011 at 8:27 PM, Paul Walmsley paul@pwsan.com wrote:

...

Hi

On Tue, 13 Dec 2011, Mike Turquette wrote:

...
omap_clk_get_by_name must die.

You do realize that it exists for a reason? That hardware clock names don't have anything to do with the Linux device model?

We have a tree structure of clks in the new common clk code, and a list of clks in clkdev (which admittedly is meant to be a subset, but in reality we register every OMAP clk with it), and then the omap clk list which is only really used by omap_get_clk_by_name for hwmod and some initialization stuff. What I'd really like to do is get rid of the OMAP clk code keeping track of it's clks in a separate list, which seems quite wasteful.

Regards, Mike

Paul Walmsley

5:29 a.m.

New subject: [PATCH 3/7] HACK: omap: convert 44xx data to common struct clk

On Tue, 13 Dec 2011, Turquette, Mike wrote:

...

On Tue, Dec 13, 2011 at 8:27 PM, Paul Walmsley paul@pwsan.com wrote:

...
On Tue, 13 Dec 2011, Mike Turquette wrote:

...
omap_clk_get_by_name must die.

You do realize that it exists for a reason? That hardware clock names don't have anything to do with the Linux device model?

We have a tree structure of clks in the new common clk code, and a list of clks in clkdev (which admittedly is meant to be a subset, but in reality we register every OMAP clk with it), and then the omap clk list which is only really used by omap_get_clk_by_name for hwmod and some initialization stuff. What I'd really like to do is get rid of the OMAP clk code keeping track of it's clks in a separate list, which seems quite wasteful.

Clock lookups that only involve a hardware clock name, with no device, should be the province of the clock code itself, not clkdev. The clkdev code may handle this today in the OMAP code, but this is simply due to legacy reasons.

In general, on OMAP, we've got much faster ways now to implement clk_get().

- Paul

Mike Turquette

4:11 a.m.

New subject: [PATCH 4/7] omap: hwmod: convert to use common struct clk

hwmod functions implicitly deal with hardware clks and must be updated to support the new common struct clk and accompanying functions.

Changes in this patch include adding clk_prepare/clk_unprepare to hwmod as well as using struct clk_hw_omap instead of the old OMAP-specific struct clk.

Signed-off-by: Mike Turquette mturquette@ti.com --- arch/arm/mach-omap2/omap_hwmod.c | 54 ++++++++++++++++++++++++++++--------- 1 files changed, 41 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 207a2ff..3e533c7 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -465,13 +465,19 @@ static int _disable_wakeup(struct omap_hwmod *oh, u32 *v) */ static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) { + struct clk_hw_omap *oclk; + struct clk_hw_omap *init_oclk; + if (!oh->_clk) return -EINVAL;

- if (oh->_clk->clkdm && oh->_clk->clkdm->flags & CLKDM_NO_AUTODEPS) + oclk = to_clk_hw_omap(oh->_clk); + init_oclk = to_clk_hw_omap(init_oh->_clk); + + if (oclk->clkdm && oclk->clkdm->flags & CLKDM_NO_AUTODEPS) return 0;

- return clkdm_add_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm); + return clkdm_add_sleepdep(oclk->clkdm, init_oclk->clkdm); }

/** @@ -489,13 +495,19 @@ static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) */ static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) { + struct clk_hw_omap *oclk; + struct clk_hw_omap *init_oclk; + if (!oh->_clk) return -EINVAL;

- return clkdm_del_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm); + return clkdm_del_sleepdep(oclk->clkdm, init_oclk->clkdm); }

/** @@ -509,10 +521,12 @@ static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) static int _init_main_clk(struct omap_hwmod *oh) { int ret = 0; + struct clk_hw_omap *oclk;

if (!oh->main_clk) return 0;

+ /* FIXME replace with common clk get_clk_by_name() */ oh->_clk = omap_clk_get_by_name(oh->main_clk); if (!oh->_clk) { pr_warning("omap_hwmod: %s: cannot clk_get main_clk %s\n", @@ -520,7 +534,9 @@ static int _init_main_clk(struct omap_hwmod *oh) return -EINVAL; }

- if (!oh->_clk->clkdm) + oclk = to_clk_hw_omap(oh->_clk); + + if (!oclk->clkdm) pr_warning("omap_hwmod: %s: missing clockdomain for %s.\n", oh->main_clk, oh->_clk->name);

@@ -601,16 +617,20 @@ static int _enable_clocks(struct omap_hwmod *oh)

pr_debug("omap_hwmod: %s: enabling clocks\n", oh->name);

- if (oh->_clk) + if (oh->_clk) { + clk_prepare(oh->_clk); clk_enable(oh->_clk); + }

if (oh->slaves_cnt > 0) { for (i = 0; i < oh->slaves_cnt; i++) { struct omap_hwmod_ocp_if *os = oh->slaves[i]; struct clk *c = os->_clk;

- if (c && (os->flags & OCPIF_SWSUP_IDLE)) + if (c && (os->flags & OCPIF_SWSUP_IDLE)) { + clk_prepare(c); clk_enable(c); + } } }

@@ -631,16 +651,20 @@ static int _disable_clocks(struct omap_hwmod *oh)

pr_debug("omap_hwmod: %s: disabling clocks\n", oh->name);

- if (oh->_clk) + if (oh->_clk) { clk_disable(oh->_clk); + clk_unprepare(oh->_clk); + }

if (oh->slaves_cnt > 0) { for (i = 0; i < oh->slaves_cnt; i++) { struct omap_hwmod_ocp_if *os = oh->slaves[i]; struct clk *c = os->_clk;

- if (c && (os->flags & OCPIF_SWSUP_IDLE)) + if (c && (os->flags & OCPIF_SWSUP_IDLE)) { clk_disable(c); + clk_unprepare(c); + } } }

@@ -660,6 +684,7 @@ static void _enable_optional_clocks(struct omap_hwmod *oh) if (oc->_clk) { pr_debug("omap_hwmod: enable %s:%s\n", oc->role, oc->_clk->name); + clk_prepare(oc->_clk); clk_enable(oc->_clk); } } @@ -676,6 +701,7 @@ static void _disable_optional_clocks(struct omap_hwmod *oh) pr_debug("omap_hwmod: disable %s:%s\n", oc->role, oc->_clk->name); clk_disable(oc->_clk); + clk_unprepare(oc->_clk); } }

@@ -1697,6 +1723,7 @@ static int _setup(struct omap_hwmod *oh, void *data) /* XXX omap_iclk_deny_idle(c); */ } else { /* XXX omap_iclk_allow_idle(c); */ + clk_prepare(c); clk_enable(c); } } @@ -1995,8 +2022,6 @@ int __init omap_hwmod_setup_one(const char *oh_name) struct omap_hwmod *oh; int r;

- pr_debug("omap_hwmod: %s: %s\n", oh_name, __func__); - if (!mpu_oh) { pr_err("omap_hwmod: %s: cannot setup_one: MPU initiator hwmod %s not yet registered\n", oh_name, MPU_INITIATOR_NAME); @@ -2304,6 +2329,7 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res) struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh) { struct clk *c; + struct clk_hw_omap *oclk;

if (!oh) return NULL; @@ -2316,10 +2342,12 @@ struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh) c = oh->slaves[oh->_mpu_port_index]->_clk; }

- if (!c->clkdm) + oclk = to_clk_hw_omap(oh->_clk); + + if (!oclk->clkdm) return NULL;

- return c->clkdm->pwrdm.ptr; + return oclk->clkdm->pwrdm.ptr;

}

-- 1.7.5.4

Mike Turquette

4:11 a.m.

New subject: [PATCH 5/7] omap: panda: use clk_prepare in ehci init

Signed-off-by: Mike Turquette mturquette@ti.com --- arch/arm/mach-omap2/board-omap4panda.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c index a8c2c42..3864d31 100644 --- a/arch/arm/mach-omap2/board-omap4panda.c +++ b/arch/arm/mach-omap2/board-omap4panda.c @@ -122,6 +122,7 @@ static void __init omap4_ehci_init(void) return; } clk_set_rate(phy_ref_clk, 19200000); + clk_prepare(phy_ref_clk); clk_enable(phy_ref_clk);

/* disable the power to the usb hub prior to init and reset phy+hub */

-- 1.7.5.4

Mike Turquette

4:11 a.m.

New subject: [PATCH 6/7] omap: dss: use clk_prepare in dss reset

Signed-off-by: Mike Turquette mturquette@ti.com --- arch/arm/mach-omap2/display.c | 4 +++- 1 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c index dce9905..21f8fcc 100644 --- a/arch/arm/mach-omap2/display.c +++ b/arch/arm/mach-omap2/display.c @@ -297,8 +297,10 @@ int omap_dss_reset(struct omap_hwmod *oh) }

for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) - if (oc->_clk) + if (oc->_clk) { + clk_prepare(oc->_clk); clk_enable(oc->_clk); + }

dispc_disable_outputs();

-- 1.7.5.4

Mike Turquette

4:11 a.m.

New subject: [PATCH 7/7] HACK: comment WARN_ON in _clkdm_clk_hwmod_disable

Not-signed-off-by: Mike Turquette mturquette@ti.com --- arch/arm/mach-omap2/clockdomain.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index ad07689..825248b 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c @@ -941,7 +941,7 @@ static int _clkdm_clk_hwmod_disable(struct clockdomain *clkdm) return -EINVAL;

if (atomic_read(&clkdm->usecount) == 0) { - WARN_ON(1); /* underflow */ + //WARN_ON(1); /* underflow */ return -ERANGE; }

-- 1.7.5.4

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Mike Turquette
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Turquette, Mike