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Re: [PATCH dri2proto] RFC: video support for dri2

by Rob Clark

On Fri, Aug 19, 2011 at 5:18 AM, Pauli Nieminen <pauli.nieminen(a)linux.intel.com> wrote: > On Thu, Aug 18, 2011 at 09:58:07PM -0500, Rob Clark wrote: >> From: Rob Clark <rob(a)ti.com> >> >> To allow the potential use of overlays to display video content, a few >> extra parameters are required: >> >> + source buffer in different format (for example, various YUV formats) >> and size as compared to destination drawable >> + multi-planar formats where discontiguous buffers are used for >> different planes. For example, luma and chroma split across >> multiple memory banks or with different tiled formats. >> + flipping between multiple back buffers, perhaps not in order (to >> handle video formats with B-frames) >> + cropping during swap.. in case of video, perhaps the required hw >> buffers are larger than the visible picture to account for codec >> borders (for example, reference frames where a block/macroblock >> moves past the edge of the visible picture, but back again in >> subsequent frames). >> >> Current solutions use the GPU to do a scaled/colorconvert into a DRI2 >> buffer from the client context. The goal of this protocol change is >> to push the decision to use overlay or GPU blit to the xorg driver. >> --- >> Eventually this should replace Xv. With a few additions, like attributes, >> it could perhaps be possible to implement the client side Xv API on top >> of dri2. >> >> Note: video is not exactly the same as 3d, there are a number of other >> things to consider (scaling, colorconvert, multi-planar formats). But >> on the other hand the principle is similar (direct rendering from hw >> video codecs). And a lot infrastructure of connection, authentication, >> is same. So there are two options, either extend DRI2 or add a new >> protocol which duplicates some parts. I'd like to consider extending >> DRI2 first, but if people think the requirements for video are too >> much different from 3d, then I could split this into a new protocol. >> >> In either case, I will implement the xserver side infrastructure, but >> I wanted to get some feel for what is the preferred approach (extend >> dri2 or new videoproto) first. >> > > XvPutVideo is already existing alternative to use for video playback > to overlays. But XvPutVideo API isn't perfect for the job either. We have until now actually used an unholy marriage of v4l2 and XvPutVideo.. part of the motivation to either extend dri2 or introduce a direct-video-rendering proto is have a better solution for some of the sort-comings of the current solution: + currently the client has to realize it is using an overlay.. and which overlay.. switching between overlay and GPU blitting is not transparent to the client + which results in a resource management issue if there are multiple videos playing, or if you need to scale beyond what can be done w/ overlay, etc + in some cases, you might want some way for the window-manager to signal to xorg driver to switch to blitting because there are some transformational effects.. ie. wobbly windows and that sort of thing.. (I'm thinking maybe setting some property on the root window?) Ideally this would be transparent to the video player app. some of this could be accomplished w/ XvPutImage, but then you are restricted to memory that can be obtained from shmem, which is not sufficient for hw video codecs in most cases. > How would client know which formats are supported by driver? Xv expose > list of supported image formats to client. well, in current version of the patch, the client would "just have to know".. which is sort of how it is on the 3d side for dri2. Although if there was an attribute mechanism, then I guess we could actually make it possible to have a completely generic client. One other issue to tackle then is what exactly is the buffer name. Currently for dri2 this is left as an implementation detail between the client and server. But we could decree that it is a GEM buffer flink name, or possibly that it is a dmabuf file-descriptor (see http://lists.linaro.org/pipermail/linaro-mm-sig/2011-August/000509.html ) For a first step, I was ok that the client side of the dri2 connection would have to know some implementation details of the xorg driver that it is talking too, since this is how it already is for dri2, and it could be handled by an approach like vaapi/vdpau where there is some driver specific code on the client side, above dri2. But on the other hand, allowing for a completely generic client using the video/dri2 proto could be interesting. I guess it depends on what folk's general feeling is.. if completely generic client side is important, then I'll go back and start adding attributes and this sort of thing. I think it is doable although it would require adding more to dri2proto than what I have proposed so far. >> dri2proto.txt | 60 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++- >> 1 files changed, 59 insertions(+), 1 deletions(-) >> >> diff --git a/dri2proto.txt b/dri2proto.txt >> index df763c7..aa83b1a 100644 >> --- a/dri2proto.txt >> +++ b/dri2proto.txt >> @@ -163,7 +163,8 @@ and DRI2InvalidateBuffers. >> 6. Protocol Types >> >> DRI2DRIVER { DRI2DriverDRI >> - DRI2DriverVDPAU } >> + DRI2DriverVDPAU, >> + DRI2DriverXV } >> >> These values describe the type of driver the client will want >> to load. The server sends back the name of the driver to use >> @@ -184,6 +185,10 @@ DRI2ATTACHMENT { DRI2BufferFrontLeft >> These values describe various attachment points for DRI2 >> buffers. >> >> + In the case of video driver (DRI2DriverXV) the attachment, >> + other than DRI2BufferFrontLeft, just indicates buffer >> + number and has no other special significance. >> + >> DRI2BUFFER { attachment: CARD32 >> name: CARD32 >> pitch: CARD32 >> @@ -203,6 +208,16 @@ DRI2ATTACH_FORMAT { attachment: CARD32 >> format. 'attachment' describes the attachment point for the buffer, >> 'format' describes an opaque, device-dependent format for the buffer. >> >> + >> +DRI2ATTACH_VIDEO { attachment: CARD32 >> + format: CARD32, >> + width, height: CARD32 } >> + >> + The DRI2ATTACH_VIDEO describes an attachment and the associated >> + format for video buffers. 'attachment' describes the attachment >> + point for the buffer, 'format' describes a fourcc value for the >> + buffer. >> + > > I think you will anyway need Xv port attribute like system to expose > HW features like color conversion. Width and height for buffers source > buffers could be one of attributes. > > If width and height are in attributes video can use > DRI2GetBuffersWithFormat. > > Format should include already information about excepted memory layout > in buffer. Format would also include information about memory layout > (packed/planar and tiled/linear) agreed, if we go the attribute route, then DRI2GetBuffersWithFormat would be enough >> ⚙ ⚙ ⚙ ⚙ ⚙ ⚙ >> >> >> @@ -367,6 +382,15 @@ The name of this extension is "DRI2". >> later. >> >> ┌─── >> + DRI2GetVideoBuffers >> + drawable: DRAWABLE >> + attachments: LISTofDRI2ATTACH_VIDEO >> + ▶ >> + width, height: CARD32 >> + buffers: LISTofDRI2BUFFER >> +└─── >> + >> +┌─── >> DRI2GetMSC >> drawable: DRAWABLE >> ▶ >> @@ -585,11 +609,21 @@ A.1 Common Types >> 4 CARD32 pitch >> 4 CARD32 cpp >> 4 CARD32 flags >> + 4 n extra names length >> + 4n LISTof extra names >> └─── >> A DRI2 buffer specifies the attachment, the kernel memory >> manager name, the pitch and chars per pixel for a buffer >> attached to a given drawable. >> >> + In case of multi-planar video formats, 'extra names' will give the >> + list of additional buffer names if there is one buffer per plane. >> + For example, I420 has one Y plane in with a 8bit luma value per >> + pixel, followed by one U plane subsampled 2x2 (with one 8bit U value >> + per 2x2 pixel block), followed by one V plane subsampled 2x2. This >> + could either be represented as a single buffer name, or three >> + separate buffer names, one each for Y, U, and V. >> + > > I think buffer format should already describe the internal memory > layout for buffer. > > Do you have example where client couldn't know memory layout from > format, width, height and stride? well, it isn't so much a format/width/height/stride issue. But it is likely that the different planes would not be contiguous in a single buffer. For example, some SoC's require that luma and chroma exist in different memory banks (different range of physical addresses). For TI OMAP, we use different tiling formats for luma and chroma in an NV12 buffer. Having the option for multiple buffer names per attachment point seemed to give the most flexibility in implementation. It would be possible to stuff these all under a single buffer name, although that brings some wrinkles.. for example, does plane n+1 start immediately after the previous plane (which it would for contiguous buffers) or on next page boundary (which would be more likely for non-contiguous buffers). And if different tiling formats are used, that further complicates the kernel side code in case the buffer is mmap'd to userspace. Having the option for either one buffer name, or one buffer name per plane avoids those complications. But I'm open to hear other opinions on the idea of 1 vs n names per attachment point. BR, -R >> ┌─── >> DRI2ATTACH_FORMAT >> 4 CARD32 attachment >> @@ -599,6 +633,17 @@ A.1 Common Types >> This data type is only available with protocol version 1.1 or >> later. >> >> +┌─── >> + DRI2ATTACH_VIDEO >> + 4 CARD32 attachment >> + 4 CARD32 format >> + 4 CARD32 width >> + 4 CARD32 height >> +└─── >> + Used to describe the attachment and format requested from the server. >> + This data type is only available with protocol version 1.? or >> + later. >> + >> A.2 Protocol Requests >> >> ┌─── >> @@ -745,6 +790,11 @@ A.2 Protocol Requests >> 4 CARD32 divisor_lo >> 4 CARD32 remainder_hi >> 4 CARD32 remainder_lo >> + 4 DRI2ATTACHMENT source >> + 4 CARD32 x1 >> + 4 CARD32 y1 >> + 4 CARD32 x2 >> + 4 CARD32 y2 >> ▶ >> 1 1 Reply >> 1 unused >> @@ -754,6 +804,14 @@ A.2 Protocol Requests >> 4 CARD32 swap_lo >> 5n LISTofDRI2BUFFER buffers >> └─── >> + The 'source', if not zero (DRI2BufferFrontLeft) indicates the >> + attachment point of the buffer to swap w/ DRI2BufferFrontLeft. >> + If zero is specified, DRI2BufferBackLeft is swapped with the >> + DRI2BufferFrontLeft buffer, for compatibility. >> + >> + If 'source' is not zero, (x1,y1), (x2,y2) specify the bounding >> + box in coordinates of the source buffer which should be scaled >> + to (0,0), (width,height) of the destination drawable. >> >> ┌─── >> DRI2GetMSC >> -- >> 1.7.5.4 >> >> _______________________________________________ >> xorg-devel(a)lists.x.org: X.Org development >> Archives: http://lists.x.org/archives/xorg-devel >> Info: http://lists.x.org/mailman/listinfo/xorg-devel >

13 years, 9 months

[PATCH v4] usb: gadget: storage_common: make FSG_NUM_BUFFERS variable size

by Per Forlin

From: Per Forlin <per.forlin(a)linaro.org> FSG_NUM_BUFFERS is set to 2 as default. Usually 2 buffers are enough to establish a good buffering pipeline. The number may be increased in order to compensate a for bursty VFS behaviour. Here follows a description of system that may require more than 2 buffers. * CPU ondemand governor active * latency cost for wake up and/or frequency change * DMA for IO Use case description. * Data transfer from MMC via VFS to USB. * DMA shuffles data from MMC and to USB. * The CPU wakes up every now and then to pass data in and out from VFS, which cause the bursty VFS behaviour. Test set up * Running dd on the host reading from the mass storage device * cmdline: dd if=/dev/sdb of=/dev/null bs=4k count=$((256*100)) * Caches are dropped on the host and on the device before each run Measurements on a Snowball board with ondemand_govenor active. FSG_NUM_BUFFERS 2 104857600 bytes (105 MB) copied, 5.62173 s, 18.7 MB/s 104857600 bytes (105 MB) copied, 5.61811 s, 18.7 MB/s 104857600 bytes (105 MB) copied, 5.57817 s, 18.8 MB/s FSG_NUM_BUFFERS 4 104857600 bytes (105 MB) copied, 5.26839 s, 19.9 MB/s 104857600 bytes (105 MB) copied, 5.2691 s, 19.9 MB/s 104857600 bytes (105 MB) copied, 5.2711 s, 19.9 MB/s There may not be one optimal number for all boards. This is why the number is added to Kconfig. If selecting USB_DEBUG this value may be set by a module parameter as well. Signed-off-by: Per Forlin <per.forlin(a)linaro.org> --- Change log. v2: Update after proofreading comments from Michal Nazarewicz v3: Clarify the description of this patch based on input from Alan Stern v4: - Introduce a module_param to set number of pipeline buffers if USB_DEBUG is set. In order to add this support fsg_common is allocated at runtime. The fsg_buffhd list size is appended to fsg_dev and fsg_common at runtime allocation. - The previous acks from Michal and Alan on v3 are not applicable for this version since it's a new implementation. drivers/usb/gadget/Kconfig | 16 ++++++++++++++++ drivers/usb/gadget/f_mass_storage.c | 10 +++++++--- drivers/usb/gadget/file_storage.c | 10 ++++++++-- drivers/usb/gadget/mass_storage.c | 16 +++++++++------- drivers/usb/gadget/storage_common.c | 20 ++++++++++++++++++-- 5 files changed, 58 insertions(+), 14 deletions(-) diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index 44b6b40..37ec2ce 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -96,6 +96,22 @@ config USB_GADGET_VBUS_DRAW This value will be used except for system-specific gadget drivers that have more specific information. +config USB_GADGET_STORAGE_NUM_BUFFERS + int "Number of storage pipeline buffers" + range 2 4 + default 2 + help + Usually 2 buffers are enough to establish a good buffering + pipeline. The number may be increased in order to compensate + for a bursty VFS behaviour. For instance there may be cpu wake up + latencies that makes the VFS to appear bursty in a system with + an cpu on-demand governor. Especially if DMA is doing IO to + offload the CPU. In this case the CPU will go into power + save often and spin up occasionally to move data within VFS. + If selecting USB_DEBUG this value may be set by a module + parameter as well. + If unsure, say 2. + # # USB Peripheral Controller Support # diff --git a/drivers/usb/gadget/f_mass_storage.c b/drivers/usb/gadget/f_mass_storage.c index 5b93395..3e546d9 100644 --- a/drivers/usb/gadget/f_mass_storage.c +++ b/drivers/usb/gadget/f_mass_storage.c @@ -363,7 +363,6 @@ struct fsg_common { struct fsg_buffhd *next_buffhd_to_fill; struct fsg_buffhd *next_buffhd_to_drain; - struct fsg_buffhd buffhds[FSG_NUM_BUFFERS]; int cmnd_size; u8 cmnd[MAX_COMMAND_SIZE]; @@ -407,6 +406,8 @@ struct fsg_common { char inquiry_string[8 + 16 + 4 + 1]; struct kref ref; + /* Must be the last entry */ + struct fsg_buffhd buffhds[0]; }; struct fsg_config { @@ -2728,12 +2729,15 @@ static struct fsg_common *fsg_common_init(struct fsg_common *common, /* Allocate? */ if (!common) { - common = kzalloc(sizeof *common, GFP_KERNEL); + common = kzalloc(sizeof(struct fsg_common) + + sizeof(struct fsg_buffhd) * FSG_NUM_BUFFERS, + GFP_KERNEL); if (!common) return ERR_PTR(-ENOMEM); common->free_storage_on_release = 1; } else { - memset(common, 0, sizeof *common); + memset(common, 0, sizeof(struct fsg_common) + + sizeof(struct fsg_buffhd) * FSG_NUM_BUFFERS); common->free_storage_on_release = 0; } diff --git a/drivers/usb/gadget/file_storage.c b/drivers/usb/gadget/file_storage.c index 639e14a..21d366d 100644 --- a/drivers/usb/gadget/file_storage.c +++ b/drivers/usb/gadget/file_storage.c @@ -461,7 +461,6 @@ struct fsg_dev { struct fsg_buffhd *next_buffhd_to_fill; struct fsg_buffhd *next_buffhd_to_drain; - struct fsg_buffhd buffhds[FSG_NUM_BUFFERS]; int thread_wakeup_needed; struct completion thread_notifier; @@ -488,6 +487,8 @@ struct fsg_dev { unsigned int nluns; struct fsg_lun *luns; struct fsg_lun *curlun; + /* Must be the last entry */ + struct fsg_buffhd buffhds[0]; }; typedef void (*fsg_routine_t)(struct fsg_dev *); @@ -3587,7 +3588,9 @@ static int __init fsg_alloc(void) { struct fsg_dev *fsg; - fsg = kzalloc(sizeof *fsg, GFP_KERNEL); + fsg = kzalloc(sizeof(struct fsg_dev) + + sizeof(struct fsg_buffhd) * FSG_NUM_BUFFERS, GFP_KERNEL); + if (!fsg) return -ENOMEM; spin_lock_init(&fsg->lock); @@ -3605,6 +3608,9 @@ static int __init fsg_init(void) int rc; struct fsg_dev *fsg; + if (!FSG_NUM_BUFFERS_IS_VALID(FSG_NUM_BUFFERS)) + return -EINVAL; + if ((rc = fsg_alloc()) != 0) return rc; fsg = the_fsg; diff --git a/drivers/usb/gadget/mass_storage.c b/drivers/usb/gadget/mass_storage.c index d3eb274..67c58d0 100644 --- a/drivers/usb/gadget/mass_storage.c +++ b/drivers/usb/gadget/mass_storage.c @@ -116,9 +116,8 @@ static int __init msg_do_config(struct usb_configuration *c) static const struct fsg_operations ops = { .thread_exits = msg_thread_exits, }; - static struct fsg_common common; + struct fsg_common *common = NULL; - struct fsg_common *retp; struct fsg_config config; int ret; @@ -130,12 +129,12 @@ static int __init msg_do_config(struct usb_configuration *c) fsg_config_from_params(&config, &mod_data); config.ops = &ops; - retp = fsg_common_init(&common, c->cdev, &config); - if (IS_ERR(retp)) - return PTR_ERR(retp); + common = fsg_common_init(common, c->cdev, &config); + if (IS_ERR(common)) + return PTR_ERR(common); - ret = fsg_bind_config(c->cdev, c, &common); - fsg_common_put(&common); + ret = fsg_bind_config(c->cdev, c, common); + fsg_common_put(common); return ret; } @@ -179,6 +178,9 @@ MODULE_LICENSE("GPL"); static int __init msg_init(void) { + if (!FSG_NUM_BUFFERS_IS_VALID(FSG_NUM_BUFFERS)) + return -EINVAL; + return usb_composite_probe(&msg_driver, msg_bind); } module_init(msg_init); diff --git a/drivers/usb/gadget/storage_common.c b/drivers/usb/gadget/storage_common.c index d3dd227..197eace 100644 --- a/drivers/usb/gadget/storage_common.c +++ b/drivers/usb/gadget/storage_common.c @@ -262,8 +262,24 @@ static struct fsg_lun *fsg_lun_from_dev(struct device *dev) #define EP0_BUFSIZE 256 #define DELAYED_STATUS (EP0_BUFSIZE + 999) /* An impossibly large value */ -/* Number of buffers we will use. 2 is enough for double-buffering */ -#define FSG_NUM_BUFFERS 2 +#ifdef CONFIG_USB_DEBUG + +static unsigned int fsg_num_buffers = CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS; +module_param(fsg_num_buffers, uint, S_IRUGO); +MODULE_PARM_DESC(fsg_num_buffers, "Number of pipeline buffers"); +#define FSG_NUM_BUFFERS fsg_num_buffers + +#else + +/* + * Number of buffers we will use. + * 2 is usually enough for good buffering pipeline + */ +#define FSG_NUM_BUFFERS CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS + +#endif /* CONFIG_USB_DEBUG */ + +#define FSG_NUM_BUFFERS_IS_VALID(num) (num >= 2 && num <= 4 ? true : false) /* Default size of buffer length. */ #define FSG_BUFLEN ((u32)16384) -- 1.7.4.1

13 years, 9 months

[PATCH 1/2] drivers: create a pinmux subsystem v3

by Linus Walleij

From: Linus Walleij <linus.walleij(a)linaro.org> This creates a subsystem for handling of pinmux devices. These are devices that enable and disable groups of pins on primarily PGA and BGA type of chip packages and common in embedded systems. This is being done to depopulate the arch/arm/* directory of such custom drivers and try to abstract the infrastructure they all need. See the Documentation/pinmux.txt file that is part of this patch for more details. Cc: Grant Likely <grant.likely(a)secretlab.ca> Cc: Stephen Warren <swarren(a)nvidia.com> Cc: Joe Perches <joe(a)perches.com> Cc: Russell King <linux(a)arm.linux.org.uk> Signed-off-by: Linus Walleij <linus.walleij(a)linaro.org> --- ChangeLog v2->v3: - Renamed subsystem folder to "pinctrl" since we will likely want to keep other pin control such as biasing in this subsystem too, so let us keep to something generic even though we're mainly doing pinmux now. - As a consequence, register pins as an abstract entity separate from the pinmux. The muxing functions will claim pins out of the pin pool and make sure they do not collide. Pins can now be named by the pinctrl core. - Converted the pin lookup from a static array into a radix tree, I agreed with Grant Likely to try to avoid any static allocation (which is crap for device tree stuff) so I just rewrote this to be dynamic, just like irq number descriptors. The platform-wide definition of number of pins goes away - this is now just the sum total of the pins registered to the subsystem. - Make sure mappings with only a function name and no device works properly. --- Documentation/ABI/testing/sysfs-class-pinmux | 11 + Documentation/pinctrl.txt | 397 ++++++++++ MAINTAINERS | 5 + drivers/Kconfig | 4 + drivers/Makefile | 2 + drivers/pinctrl/Kconfig | 29 + drivers/pinctrl/Makefile | 6 + drivers/pinctrl/core.c | 1028 ++++++++++++++++++++++++++ include/linux/pinctrl/machine.h | 57 ++ include/linux/pinctrl/pinmux.h | 180 +++++ 10 files changed, 1719 insertions(+), 0 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-class-pinmux create mode 100644 Documentation/pinctrl.txt create mode 100644 drivers/pinctrl/Kconfig create mode 100644 drivers/pinctrl/Makefile create mode 100644 drivers/pinctrl/core.c create mode 100644 include/linux/pinctrl/machine.h create mode 100644 include/linux/pinctrl/pinmux.h diff --git a/Documentation/ABI/testing/sysfs-class-pinmux b/Documentation/ABI/testing/sysfs-class-pinmux new file mode 100644 index 0000000..c2ea843 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-class-pinmux @@ -0,0 +1,11 @@ +What: /sys/class/pinmux/.../name +Date: May 2011 +KernelVersion: 3.1 +Contact: Linus Walleij <linus.walleij(a)linaro.org> +Description: + Each pinmux directory will contain a field called + name. This holds a string identifying the pinmux for + display purposes. + + NOTE: this will be empty if no suitable name is provided + by platform or pinmux drivers. diff --git a/Documentation/pinctrl.txt b/Documentation/pinctrl.txt new file mode 100644 index 0000000..c4b6f48 --- /dev/null +++ b/Documentation/pinctrl.txt @@ -0,0 +1,397 @@ +PINCTRL (PIN CONTROL) subsystem +This document outlines the pin control subsystem in Linux + +This subsystem deals with: + +- Multiplexing of pins, pads, fingers (etc) see below for details + +The intention is to also deal with: + +- Software-controlled biasing and driving mode specific pins, such as + pull-up/down, open drain etc, load capacitance configuration when controlled + by software, etc. + + +Top-level interface +=================== + +Definition of PIN: + +- PINS are equal to pads or fingers or whatever packaging output you want to + mux and these are denoted by unsigned integers in the range 0..MAX_INT. Every + pin on your system (or atleast every pin that can be muxed) should have a + unique number. The numberspace can span several chips if you have more chips + on your system that can be subject to muxing. + +All pins, pads, fingers, balls or other controllable units on the system shall +be given a unique number in the global number space beginning on zero. + +All pins on the system need to be registered, typically by board code or a +device tree. Board/machine code will #include <linux/pinctrl/machine.h> +and use one of: + + pinctrl_register_pins_sparse(); + pinctrl_register_pins_dense(); + +To register all the pins on the system. Both are supplied with a list of +descriptor items, the difference is that the _dense version will also +register anonymous pins for each "hole" in the pin map, from zero to the +supplied extra argument giving the number of pins. + +Here is an example of a PGA (Pin Grid Array) chip seen from underneath: + + A B C D E F G H + + 8 o o o o o o o o + + 7 o o o o o o o o + + 6 o o o o o o o o + + 5 o o o o o o o o + + 4 o o o o o o o o + + 3 o o o o o o o o + + 2 o o o o o o o o + + 1 o o o o o o o o + +To register and name all the pins on this package we can do this in a board +file: + +#include <linux/pinctrl/machine.h> + +const struct pinctrl_pin_desc __initdata my_pins[] = { + PINCTRL_PIN(0, "A1"), + PINCTRL_PIN(1, "A2"), + PINCTRL_PIN(2, "A3"), + ... + PINCTRL_PIN(61, "H6"), + PINCTRL_PIN(62, "H7"), + PINCTRL_PIN(63, "H8"), +}; + +int __init register_pins(void) +{ + pinctrl_register_pins_dense(&my_pins, ARRAY_SIZE(my_pins), 64); +} + +Pins usually have fancier names than this. You can find these in the dataheet +for your chip. Notice that the core machine.h file provides a fancy macro +called PINCTRL_PIN() to create the struct entries. + + +PINMUX interfaces +================= + +These calls use the pinmux_* naming prefix. No other calls should use that +prefix. + + +What is pinmuxing? +================== + +Pinmux, also known as padmux, ballmux, alternate functions or mission modes +is a way for chip vendors producing some kind of electrical packages to use +a certain physical bin (ball, pad, finger, etc) for multiple mutually exclusive +functions, depending on the application. By "application" in this context +we usually mean a way of soldering or wiring the package into an electronic +system, even though the framework makes it possible to handle also change the +function at runtime. + +Here is an example of a PGA (Pin Grid Array) chip seen from underneath: + + A B C D E F G H + +---+ + 8 | o | o o o o o o o + | | + 7 | o | o o o o o o o + | | + 6 | o | o o o o o o o + +---+---+ + 5 | o | o | o o o o o o + +---+---+ +---+ + 4 o o o o o o | o | o + | | + 3 o o o o o o | o | o + | | + 2 o o o o o o | o | o + | | + 1 o o o o o o | o | o + +---+ + +This is not tetris. The game to think of is chess. Not all PGA/BGA packages +are chessboard-like, big ones have "holes" in some arrangement according to +different design patterns, but we're using this as a simple example. Of the +pins you see some will be taken by things like a few VCC and GND to feed power +to the chip, and quite a few will be taken by large ports like an external +memory interface. The remaining pins will often be subject to pin multiplexing. + +The example 8x8 PGA package above will have pin numbers 0 thru 63 assigned to +its physical pins. It will name the pins { A1, A2, A3 ... H6, H7, H8 } using +pinctrl_register_pins_[sparse|dense]() and a suitable data set as shown +earlier. + +In this 8x8 BGA package the pins { A8, A7, A6, A5 } can be used as an SPI port +(these are four pins: CLK, RXD, TXD, FRM). In that case, pin B5 can be used as +some general-purpose GPIO pin. However, in another setting, pins { A5, B5 } can +be used as an I2C port (these are just two pins: SCL, SDA). Needless to say, +we cannot use the SPI port and I2C port at the same time. However in the inside +of the package the silicon performing the SPI logic can alternatively be routed +out on pins { G4, G3, G2, G1 }. + +This way the silicon blocks present inside the chip can be multiplexed "muxed" +out on different pin ranges. Often contemporary SoC (systems on chip) will +contain several I2C, SPI, SDIO/MMC, etc silicon blocks that can be routed to +different pins by pinmux settings. + +Since general-purpose I/O pins (GPIO) are typically always in shortage, it is +common to be able to use almost any pin as a GPIO pin if it is not currently +in use by some other I/O port. + + +Pinmux conventions +================== + +The purpose of the pinmux subsystem is to abstract and provide pinmux settings +to the devices you choose to instantiate in your machine configuration. It is +inspired by the clk, GPIO and regulator subsystems, so devices will request +their mux setting, but it's also possible to request a single pin for e.g. +GPIO. + +Definitions: + +- FUNCTIONS can be switched in and out by a driver residing with the pinmux + subsystem in the drivers/pinmux/* directory of the kernel. The pinmux driver + knows the possible functions. In the example above you can identify three + pinmux functions, two for spi and one for i2c. + +- FUNCTIONS are assumed to be enumerable from zero in a one-dimensional array. + In this case the array could be something like: { spi0-0, spi0-1, i2c0-0 } + for the three available settings. The knowledge of this one-dimensional array + and it's machine-specific particulars is kept inside the pinmux driver, + from the outside only these enumerators are known, and the driver core + can request the name or the list of pins belonging to a certain enumerator. + +- FUNCTIONS are MAPPED to a certain device by the board file, device tree or + similar machine setup configuration mechanism, similar to how regulators are + connected to devices, usually by name. In the example case we can define + that this particular machine shall use device spi0 with pinmux setting + spi0-1 and i2c0 on i2c0-1, something like the two-tuple: + { {spi0, spi0-1}, {i2c0, i2c0-1} } + +- FUNCTIONS are provided on a first-come first-serve basis, so if some other + device mux setting or GPIO pin request has already taken your physical pin, + you will be denied the use of it. To get (activate) a new setting, the old + one has to be put (deactivated) first. + +Sometimes the documentation and hardware registers will be oriented around +pads (or "fingers") rather than pins - these are the soldering surfaces on the +silicon inside the package, and may or may not match the actual number of +pins/balls underneath the capsule. Pick some enumeration that makes sense to +you. Define enumerators only for the pins you can control if that makes sense. + + +Pinmux drivers +============== + +The driver will for all calls be provided an offset pin number into its own +pin range. If you have 2 chips with 8x8 pins, the first chips pins will have +numbers 0 thru 63 and the second one pins 64 thru 127, but the driver for the +second chip will be passed numbers in the range 0 thru 63 anyway, base offset +subtracted. + +Pinmux drivers are required to supply a few callback functions, some are +optional. Usually the enable() and disable() functions are implemented, +writing values into some certain registers to activate a certain mux setting +for a certain pin. + +A simple driver for the above example will work by setting bits 0, 1 or 2 +into some register mamed MUX, so it enumerates its available settings and +their pin assignments, and expose them like this: + +#include <linux/pinctrl/pinmux.h> + +struct foo_pmx_func { + char *name; + const unsigned int *pins; + const unsigned num_pins; +}; + +static unsigned int spi0_0_pins[] = { 0, 8, 16, 24 }; +static unsigned int i2c0_pins[] = { 24, 25 }; +static unsigned int spi0_1_pins[] = { 38, 46, 54, 62 }; + +static struct foo_pmx_func myfuncs[] = { + { + .name = "spi0-0", + .pins = spi0_0_pins, + .num_pins = ARRAY_SIZE(spi0_1_pins), + }, + { + .name = "i2c0", + .pins = i2c0_pins, + .num_pins = ARRAY_SIZE(i2c0_pins), + }, + { + .name = "spi0-1", + .pins = spi0_1_pins, + .num_pins = ARRAY_SIZE(spi0_1_pins), + }, +}; + +int foo_list(struct pinmux_dev *pmxdev, unsigned selector) +{ + if (selector >= ARRAY_SIZE(myfuncs)) + return -EINVAL; + return 0; +} + +const char *foo_get_fname(struct pinmux_dev *pmxdev, unsigned selector) +{ + if (selector >= ARRAY_SIZE(myfuncs)) + return NULL; + return myfuncs[selector].name; +} + +static int foo_get_pins(struct pinmux_dev *pmxdev, unsigned selector, + unsigned ** const pins, unsigned * const num_pins) +{ + if (selector >= ARRAY_SIZE(myfuncs)) + return -EINVAL; + *pins = myfuncs[selector].pins; + *num_pins = myfuncs[selector].num_pins; + return 0; +} + + +int foo_enable(struct pinmux_dev *pmxdev, unsigned selector) +{ + if (selector < ARRAY_SIZE(myfuncs)) + write((read(MUX)|(1<<selector)), MUX) + return 0; + } + return -EINVAL; +} + +int foo_disable(struct pinmux_dev *pmxdev, unsigned selector) +{ + if (selector < ARRAY_SIZE(myfuncs)) + write((read(MUX) & ~(1<<selector)), MUX) + return 0; + } + return -EINVAL; +} + +struct pinmux_ops ops = { + .list_functions = foo_list, + .get_function_name = foo_get_fname, + .get_function_pins = foo_get_pins, + .enable = foo_enable, + .disable = foo_disable, +}; + +Now the able reader will say: "wait - the driver needs to make sure it +can set this and that bit at the same time, because else it will collide +and wreak havoc in my electronics, and make sure noone else is using the +other setting that it's incompatible with". + +In the example activating muxing 0 and 1 at the same time setting bits +0 and 1, uses one pin in common so they would collide. + +The beauty of the pinmux subsystem is that since it keeps track of all +pins and who is using them, it will already have denied an impossible +request like that, so the driver does not need to worry about such +things - when it gets a selector passed in, the pinmux subsystem makes +sure no other device or GPIO assignment is already using the selected +pins. + +The above functions are mandatory to implement for a pinmux driver. + +The function list could become long, especially if you can convert every +individual pin into a GPIO pin independent of any other pins, then your +function array can become 64 entries for each GPIO setting and then the +device functions. For this reason there is an additional function you +can implement to enable only GPIO on an individual pin: gpio_enable(). + + +Pinmux board/machine configuration +================================== + +Boards and machines define how a certain complete running system is put +together, including how GPIOs and devices are muxed, how regulators are +constrained and how the clock tree looks. Of course pinmux settings are also +part of this. + +A pinmux config for a machine looks pretty much like a simple regulator +configuration, so for the example array above we want to enable i2c and +spi on the second function mapping: + +#include <linux/pinctrl/machine.h> + +static struct pinmux_map pmx_mapping[] = { + { + .function = "spi0-1", + .dev_name = "foo-spi.0", + }, + { + .function = "i2c0", + .dev_name = "foo-i2c.0", + }, +}; + +Since the above construct is pretty common there is a helper macro to make +it even more compact: + +static struct pinmux_map pmx_mapping[] = { + PINMUX_MAP("spi0-1", "foo-spi.0"), + PINMUX_MAP("i2c0", "foo-i2c.0"), +}; + +The dev_name here matches to the unique device name that can be used to look +up the device struct (just like with clockdev or regulators). The function name +must match a function provided by the pinmux driver handling this pin range. +You register this pinmux mapping to the pinmux subsystem by simply: + + ret = pinmux_register_mappings(&pmx_mapping, ARRAY_SIZE(pmx_mapping)); + + +Pinmux requests from drivers +============================ + +A driver may request a certain mux to be activated, usually just the default +mux like this: + +#include <linux/pinctrl/pinmux.h> + +foo_probe() +{ + /* Allocate a state holder named "state" etc */ + struct pinmux pmx; + + pmx = pinmux_get(&device, NULL); + if IS_ERR(pmx) + return PTR_ERR(pmx); + pinmux_enable(pmx); + + state->pmx = pmx; +} + +foo_remove() +{ + pinmux_disable(state->pmx); + pinmux_put(state->pmx); +} + +If you want a specific mux setting and not just the first one found for this +device you can specify a specific mux setting, for example in the above example +the second i2c0 setting: pinmux_get(&device, "spi0-2"); + +This get/enable/disable/put sequence can just as well be handled by bus drivers +if you don't want each and every driver to handle it and you know the +arrangement on your bus. + +The pins are allocated for your device when you issue the pinmux_get() call, +after this you should be able to see this in the debugfs listing of all pins. diff --git a/MAINTAINERS b/MAINTAINERS index 29801f7..5caea5a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4933,6 +4933,11 @@ L: linux-mtd(a)lists.infradead.org S: Maintained F: drivers/mtd/devices/phram.c +PINMUX SUBSYSTEM +M: Linus Walleij <linus.walleij(a)linaro.org> +S: Maintained +F: drivers/pinmux/ + PKTCDVD DRIVER M: Peter Osterlund <petero2(a)telia.com> S: Maintained diff --git a/drivers/Kconfig b/drivers/Kconfig index 3bb154d..6998d78 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -56,6 +56,10 @@ source "drivers/pps/Kconfig" source "drivers/ptp/Kconfig" +# pinctrl before gpio - gpio drivers may need it + +source "drivers/pinctrl/Kconfig" + source "drivers/gpio/Kconfig" source "drivers/w1/Kconfig" diff --git a/drivers/Makefile b/drivers/Makefile index 09f3232..a590a01 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -5,6 +5,8 @@ # Rewritten to use lists instead of if-statements. # +# GPIO must come after pinctrl as gpios may need to mux pins etc +obj-y += pinctrl/ obj-y += gpio/ obj-$(CONFIG_PCI) += pci/ obj-$(CONFIG_PARISC) += parisc/ diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig new file mode 100644 index 0000000..8050fdf --- /dev/null +++ b/drivers/pinctrl/Kconfig @@ -0,0 +1,29 @@ +# +# PINCTRL infrastructure and drivers +# + +menuconfig PINCTRL + bool "PINCTRL Support" + depends on SYSFS && EXPERIMENTAL + help + This enables the PINCTRL subsystem for controlling pins + on chip packages, for example multiplexing pins on primarily + PGA and BGA packages for systems on chip. + + If unsure, say N. + +if PINCTRL + +config DEBUG_PINCTRL + bool "Debug PINCTRL calls" + depends on DEBUG_KERNEL + help + Say Y here to add some extra checks and diagnostics to PINCTRL calls. + +config PINMUX_U300 + bool "U300 pinmux driver" + depends on ARCH_U300 + help + Say Y here to enable the U300 pinmux driver + +endif diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile new file mode 100644 index 0000000..44d8933 --- /dev/null +++ b/drivers/pinctrl/Makefile @@ -0,0 +1,6 @@ +# generic pinmux support + +ccflags-$(CONFIG_DEBUG_PINMUX) += -DDEBUG + +obj-$(CONFIG_PINCTRL) += core.o +obj-$(CONFIG_PINMUX_U300) += pinmux-u300.o diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c new file mode 100644 index 0000000..8fd1437 --- /dev/null +++ b/drivers/pinctrl/core.c @@ -0,0 +1,1028 @@ +/* + * Core driver for the pinmux subsystem + * + * Copyright (C) 2011 ST-Ericsson SA + * Written on behalf of Linaro for ST-Ericsson + * Based on bits of regulator core, gpio core and clk core + * + * Author: Linus Walleij <linus.walleij(a)linaro.org> + * + * License terms: GNU General Public License (GPL) version 2 + */ +#define pr_fmt(fmt) "pinctrl core: " fmt + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/device.h> +#include <linux/slab.h> +#include <linux/radix-tree.h> +#include <linux/err.h> +#include <linux/list.h> +#include <linux/mutex.h> +#include <linux/spinlock.h> +#include <linux/sysfs.h> +#include <linux/debugfs.h> +#include <linux/seq_file.h> +#include <linux/pinctrl/machine.h> +#include <linux/pinctrl/pinmux.h> + +/* Global list of pinmuxes */ +static DEFINE_MUTEX(pinmux_list_mutex); +static LIST_HEAD(pinmux_list); + +/* Global list of pinmux devices */ +static DEFINE_MUTEX(pinmuxdev_list_mutex); +static LIST_HEAD(pinmuxdev_list); + +/** + * struct pin_desc - pin descriptor for each physical pin in the arch + * @pmxdev: corresponding pinmux device + * @requested: whether the pin is already requested by pinmux or not + * @name: a name for the pin, e.g. the name of the pin/pad/finger on a + * datasheet or such + * @function: a named muxing function for the pin that will be passed to + * subdrivers and shown in debugfs etc + */ +struct pin_desc { + struct pinmux_dev *pmxdev; + bool requested; + char name[16]; + char function[16]; +}; +/* Global lookup of per-pin descriptors, one for each physical pin */ +static DEFINE_SPINLOCK(pin_desc_tree_lock); +static RADIX_TREE(pin_desc_tree, GFP_KERNEL); +static unsigned int num_pins = 0; + +/** + * struct pinmux - per-device pinmux state holder + * @node: global list node - only for internal use + * @dev: the device using this pinmux + * @pmxdev: the pinmux device controlling this pinmux + * @map: corresponding pinmux map active for this pinmux setting + * @usecount: the number of active users of this mux setting, used to keep + * track of nested use cases + * @pins: an array of discrete physical pins used in this mapping, taken + * from the global pin enumeration space (copied from pinmux map) + * @num_pins: the number of pins in this mapping array, i.e. the number of + * elements in .pins so we can iterate over that array (copied from + * pinmux map) + * @pmxdev: pinmux device handling this pinmux + * @pmxdev_selector: the selector for the pinmux device handling this pinmux + * @mutex: a lock for the pinmux state holder + */ +struct pinmux { + struct list_head node; + struct device *dev; + struct pinmux_map const *map; + unsigned usecount; + struct pinmux_dev *pmxdev; + unsigned pmxdev_selector; + struct mutex mutex; +}; + +int pin_is_valid(int pin) +{ + return pin >= 0 && pin < num_pins; +} +EXPORT_SYMBOL_GPL(pin_is_valid); + +static ssize_t pinmux_name_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct pinmux_dev *pmxdev = dev_get_drvdata(dev); + + return sprintf(buf, "%s\n", pmxdev_get_name(pmxdev)); +} + +static struct device_attribute pinmux_dev_attrs[] = { + __ATTR(name, 0444, pinmux_name_show, NULL), + __ATTR_NULL, +}; + +static void pinmux_dev_release(struct device *dev) +{ + struct pinmux_dev *pmxdev = dev_get_drvdata(dev); + kfree(pmxdev); +} + +static struct class pinmux_class = { + .name = "pinmux", + .dev_release = pinmux_dev_release, + .dev_attrs = pinmux_dev_attrs, +}; + +/* Deletes a range of pin descriptors */ +static void pinctrl_free_pindescs(struct pinctrl_pin_desc const *pins, + unsigned num_pins) +{ + int i; + + for (i = 0; i < num_pins; i++) { + struct pin_desc *pindesc; + + spin_lock(&pin_desc_tree_lock); + pindesc = radix_tree_lookup(&pin_desc_tree, pins[i].number); + if (pindesc != NULL) { + radix_tree_delete(&pin_desc_tree, pins[i].number); + num_pins --; + } + spin_unlock(&pin_desc_tree_lock); + kfree(pindesc); + } +} + +static int pinctrl_register_one_pin(unsigned number, const char *name) +{ + struct pin_desc *pindesc; + + spin_lock(&pin_desc_tree_lock); + pindesc = radix_tree_lookup(&pin_desc_tree, number); + spin_unlock(&pin_desc_tree_lock); + + if (pindesc != NULL) { + pr_err("pin %d already registered\n", number); + return -EINVAL; + } + + pindesc = kzalloc(sizeof(*pindesc), GFP_KERNEL); + if (pindesc == NULL) + return -ENOMEM; + + /* Copy optional basic pin info */ + if (name) { + strncpy(pindesc->name, name, 16); + pindesc->name[15] = '\0'; + } + + spin_lock(&pin_desc_tree_lock); + radix_tree_insert(&pin_desc_tree, number, pindesc); + num_pins ++; + spin_unlock(&pin_desc_tree_lock); + return 0; +} + +/* Passing in 0 num_pins means "sparse" */ +static int pinctrl_register_pins(struct pinctrl_pin_desc const *pins, + unsigned num_descs, unsigned num_pins) +{ + unsigned i; + int ret = 0; + + for (i = 0; i < num_descs; i++) { + ret = pinctrl_register_one_pin(pins[i].number, pins[i].name); + if (ret) + return ret; + } + + if (num_pins == 0) + return 0; + + /* + * If we are registerering dense pinlists, fill in all holes with + * anonymous pins. + */ + for (i = 0; i < num_pins; i++) { + char pinname[16]; + struct pin_desc *pindesc; + + spin_lock(&pin_desc_tree_lock); + pindesc = radix_tree_lookup(&pin_desc_tree, i); + spin_unlock(&pin_desc_tree_lock); + /* Already registered this one, take next */ + if (pindesc) + continue; + + snprintf(pinname, 15, "anonymous %u", i); + pinname[15] = '\0'; + + ret = pinctrl_register_one_pin(i, pinname); + if (ret) + return ret; + } + + return 0; +} + +/** + * pinctrl_register_pins_sparse() - register a range of pins for a + * board/machine with potential holes in the pin map. The pins in + * the holes will not be usable. + * @pins: a range of pins to register + * @num_descs: the number of pins descriptors passed in through the previous + * pointer + */ +int pinctrl_register_pins_sparse(struct pinctrl_pin_desc const *pins, + unsigned num_descs) +{ + int ret; + + ret = pinctrl_register_pins(pins, num_descs, 0); + if (ret) + pinctrl_free_pindescs(pins, num_descs); + return ret; + +} +EXPORT_SYMBOL_GPL(pinctrl_register_pins); + +/** + * pinctrl_register_pins_dense() - register a range of pins for a + * board/machine, if there are holes in the pin map, they will be + * allocated by anonymous pins. + * @pins: a range of pins to register + * @num_descs: the number of pins descriptors passed in through the previous + * pointer + * @num_pins: the total number of pins including holes in the pin map and + * any "air" at the end of the map, all pins from 0 to this number + * will be allocated, the ones that does not have descriptors passed + * in will be marked "anonymous" + */ +int pinctrl_register_pins_dense(struct pinctrl_pin_desc const *pins, + unsigned num_descs, unsigned num_pins) +{ + int ret; + unsigned i; + + ret = pinctrl_register_pins(pins, num_descs, num_pins); + if (ret) { + for (i = 0; i < num_pins; i++) { + struct pin_desc *pindesc; + + spin_lock(&pin_desc_tree_lock); + pindesc = radix_tree_lookup(&pin_desc_tree, i); + if (pindesc != NULL) { + radix_tree_delete(&pin_desc_tree, i); + num_pins --; + } + spin_unlock(&pin_desc_tree_lock); + kfree(pindesc); + } + } + return ret; +} +EXPORT_SYMBOL_GPL(pinctrl_register_pins_sparse); + +/** + * pin_request() - request a single pin to be muxed in, typically for GPIO + * @pin: the pin number in the global pin space + * @function: a functional name to give to this pin, passed to the driver + * so it knows what function to mux in, e.g. the string "gpioNN" + * means that you want to mux in the pin for use as GPIO number NN + * @gpio: if this request concerns a single GPIO pin + */ +static int pin_request(int pin, const char *function, bool gpio) +{ + struct pin_desc *desc; + struct pinmux_dev *pmxdev; + const struct pinmux_ops *ops; + int status = -EINVAL; + unsigned long flags; + + pr_debug("request pin %d for %s\n", pin, function); + if (!pin_is_valid(pin)) { + pr_err("pin is invalid\n"); + return -EINVAL; + } + + if (!function) { + pr_err("no function name given\n"); + return -EINVAL; + } + + spin_lock_irqsave(&pin_desc_tree_lock, flags); + desc = radix_tree_lookup(&pin_desc_tree, pin); + if (desc == NULL) { + pr_err("pin is not registered so it cannot be requested\n"); + goto out; + } + pmxdev = desc->pmxdev; + if (desc->requested) { + pr_err("pin already requested\n"); + goto out; + } + if (!pmxdev) { + pr_warn("no pinmux device is handling pin %d\n", pin); + goto out; + } + ops = pmxdev->desc->ops; + + /* Let each pin increase references to this module */ + if (!try_module_get(pmxdev->owner)) { + pr_err("could not increase module refcount for pin %d\n", pin); + status = -EINVAL; + goto out; + } + + /* + * If there is no kind of request function for the pin we just assume + * we got it by default and proceed. + */ + if (gpio && ops->gpio_request_enable) + /* This requests and enables a single GPIO pin */ + status = ops->gpio_request_enable(pmxdev, + pin - pmxdev->desc->base); + else if (ops->request) + status = ops->request(pmxdev, + pin - pmxdev->desc->base); + else + status = 0; + + if (status) { + pr_err("->request on device %s failed " + "for pin %d (offset %d)\n", + pmxdev->desc->name, pin, + pin - pmxdev->desc->base); + goto out; + } + + desc->requested = true; + strncpy(desc->function, function, 16); + desc->function[15] = '\0'; + +out: + spin_unlock_irqrestore(&pin_desc_tree_lock, flags); + if (status) + pr_err("pin-%d (%s) status %d\n", + pin, function ? : "?", status); + + return status; +} + +/** + * pin_free() - release a single muxed in pin so something else can be muxed in + * instead + * @pin: the pin to free + */ +static void pin_free(int pin) +{ + struct pin_desc *desc; + struct pinmux_dev *pmxdev; + unsigned long flags; + + if (!pin_is_valid(pin)) + return; + + spin_lock_irqsave(&pin_desc_tree_lock, flags); + desc = radix_tree_lookup(&pin_desc_tree, pin); + if (desc == NULL) { + pr_err("pin is not registered so it cannot be freed\n"); + goto out; + } + pmxdev = desc->pmxdev; + if (pmxdev) { + const struct pinmux_ops *ops = pmxdev->desc->ops; + + if (ops->free) + ops->free(pmxdev, pin - pmxdev->desc->base); + } + desc->requested = false; + desc->function[0] = '\0'; + module_put(pmxdev->owner); +out: + spin_unlock_irqrestore(&pin_desc_tree_lock, flags); +} + +/** + * pinmux_request_gpio() - request a single pin to be muxed in to be used + * as a GPIO pin + * @pin: the pin to mux in as GPIO + * @gpio: the corresponding GPIO pin number + */ +int pinmux_request_gpio(int pin, unsigned gpio) +{ + char gpiostr[16]; + + snprintf(gpiostr, 15, "gpio%d", gpio); + return pin_request(pin, gpiostr, true); +} +EXPORT_SYMBOL_GPL(pinmux_request_gpio); + +/** + * pinmux_free_gpio() - free a single pin, currently muxed in to be used + * as a GPIO pin + * @pin: the pin to mux out from GPIO + */ +void pinmux_free_gpio(int pin) +{ + return pin_free(pin); +} +EXPORT_SYMBOL_GPL(pinmux_free_gpio); + +int pinmux_register_mappings(struct pinmux_map const *maps, unsigned num_maps) +{ + int ret = 0; + int i; + + pr_debug("add %d functions\n", num_maps); + for (i = 0; i < num_maps; i++) { + struct pinmux *pmx; + + /* Sanity check the mapping */ + if (!maps[i].function) { + pr_err("failed to register map %d - no function ID given\n", i); + ret = -EINVAL; + goto out; + } + if (!maps[i].dev && !maps[i].dev_name) { + pr_err("failed to register map %d - no device or device name given\n", i); + ret = -EINVAL; + goto out; + } + + /* + * create the state cookie holder struct pinmux for each + * mapping, this is what consumers will get when requesting + * a pinmux handle with pinmux_get() + */ + pmx = kzalloc(sizeof(struct pinmux), GFP_KERNEL); + if (pmx == NULL) { + ret = -ENOMEM; + goto out; + } + mutex_init(&pmx->mutex); + pmx->map = &maps[i]; + + /* Add the pinmux */ + mutex_lock(&pinmux_list_mutex); + list_add(&pmx->node, &pinmux_list); + mutex_unlock(&pinmux_list_mutex); + pr_debug("add function %s\n", maps[i].function); + } + +out: + return ret; +} + +/** + * acquire_pins() - acquire all the pins for a certain funcion on a certain + * pinmux device + * @pmxdev: the device to take the function on + * @selector: the selector to acquire the pins for + */ +int acquire_pins(struct pinmux_dev *pmxdev, unsigned selector) +{ + const struct pinmux_ops *ops = pmxdev->desc->ops; + unsigned *pins; + unsigned num_pins; + const char *func = ops->get_function_name(pmxdev, selector); + int ret; + int i; + + ret = ops->get_function_pins(pmxdev, selector, &pins, &num_pins); + if (ret) + return ret; + + /* Try to allocate all pins in this pinmux map, one by one */ + for (i = 0; i < num_pins; i++) { + ret = pin_request(pins[i], func, false); + if (ret) { + pr_err("could not get pin %d for function %s " + "on device %s - conflicting mux mappings?\n", + pins[i], func ? : "(undefined)", + pmxdev->desc->name); + /* On error release all taken pins */ + i--; /* this pin just failed */ + for (; i >= 0; i--) + pin_free(pins[i]); + return -ENODEV; + } + } + return 0; +} + +/** + * pinmux_get() - retrieves the pinmux for a certain device + * @dev: the device to get the pinmux for + * @func: an optional mux name or NULL, the name is only needed + * if a single device has multiple pinmux settings (i.e. if the + * same device can be muxed out on different sets of pins) or if + * you need an anonymous pinmux (not tied to any specific device) + */ +struct pinmux *pinmux_get(struct device *dev, const char *func) +{ + struct pinmux_map const *map = NULL; + struct pinmux_dev *pmxdev = NULL; + const char *devname = NULL; + struct pinmux *pmx; + bool found = false; + int ret = -ENODEV; + + /* We must have dev or ID or both */ + if (!dev && !func) + return ERR_PTR(-EINVAL); + + mutex_lock(&pinmux_list_mutex); + + if (dev) + devname = dev_name(dev); + + /* Locate the pinmux map */ + list_for_each_entry(pmx, &pinmux_list, node) { + map = pmx->map; + + /* If an function is given, it MUST match */ + if ((func != NULL) && strcmp(map->function, func)) + continue; + + /* + * This is for the case where no device name is given, we + * already know that the function name matches from above + * code. + */ + if (!map->dev_name && (func != NULL)) { + found = true; + break; + } + + /* If the mapping has a device set up it must match */ + if (map->dev_name && + (!devname || !strcmp(map->dev_name, devname))) { + /* MATCH! */ + found = true; + break; + } + } + + mutex_unlock(&pinmux_list_mutex); + + if (!found) { + pr_err("could not find mux map for device %s, ID %s\n", + devname ? : "(anonymous)", func ? : "(undefined)"); + goto out; + } + + /* Make sure that noone else is using this function mapping */ + mutex_lock(&pmx->mutex); + if (pmx->dev) { + if (pmx->dev != dev) { + mutex_unlock(&pmx->mutex); + pr_err("mapping already in use device %s, ID %s\n", + devname ? : "(anonymous)", func ? : "(undefined)"); + goto out; + } else { + /* We already fetched this and requested pins */ + mutex_unlock(&pmx->mutex); + ret = 0; + goto out; + } + } + mutex_unlock(&pmx->mutex); + + + /* + * Iterate over the drivers so see which ones that may handle this + * specific muxing. NOTE: there can be only one as of now. + */ + list_for_each_entry(pmxdev, &pinmuxdev_list, node) { + const struct pinmux_ops *ops = pmxdev->desc->ops; + unsigned selector = 0; + + /* See if this pmxdev has this function */ + while (ops->list_functions(pmxdev, selector) >= 0) { + const char *fname = ops->get_function_name(pmxdev, + selector); + + if (!strcmp(map->function, fname)) { + ret = acquire_pins(pmxdev, selector); + if (ret) + goto out; + /* Found it! */ + mutex_lock(&pmx->mutex); + pmx->dev = dev; + pmx->pmxdev = pmxdev; + pmx->pmxdev_selector = selector; + mutex_unlock(&pmx->mutex); + ret = 0; + goto out; + } + selector++; + } + } + /* We couldn't find the driver for this pinmux */ + ret = -ENODEV; + +out: + if (ret) + pmx = ERR_PTR(ret); + + return pmx; +} +EXPORT_SYMBOL_GPL(pinmux_get); + +/** + * pinmux_put() - release a previously claimed pinmux + * @pmx: a pinmux previously claimed by pinmux_get() + */ +void pinmux_put(struct pinmux *pmx) +{ + if (pmx == NULL) + return; + mutex_lock(&pmx->mutex); + if (pmx->usecount) + pr_warn("pinmux: releasing pinmux with active users!\n"); + pmx->dev = NULL; + pmx->pmxdev = NULL; + pmx->pmxdev_selector = 0; + mutex_unlock(&pmx->mutex); +} +EXPORT_SYMBOL_GPL(pinmux_put); + +/** + * pinmux_enable() - enable a certain pinmux setting + * @pmx: the pinmux to enable, previously claimed by pinmux_get() + */ +int pinmux_enable(struct pinmux *pmx) +{ + int ret = 0; + + if (pmx == NULL) + return -EINVAL; + mutex_lock(&pmx->mutex); + if (pmx->usecount++ == 0) { + struct pinmux_dev *pmxdev = pmx->pmxdev; + const struct pinmux_ops *ops = pmxdev->desc->ops; + + ret = ops->enable(pmxdev, pmx->pmxdev_selector); + if (ret) + pmx->usecount--; + } + mutex_unlock(&pmx->mutex); + return ret; +} +EXPORT_SYMBOL_GPL(pinmux_enable); + +/** + * pinmux_disable() - disable a certain pinmux setting + * @pmx: the pinmux to disable, previously claimed by pinmux_get() + */ +void pinmux_disable(struct pinmux *pmx) +{ + if (pmx == NULL) + return; + + mutex_lock(&pmx->mutex); + if (--pmx->usecount == 0) { + struct pinmux_dev *pmxdev = pmx->pmxdev; + const struct pinmux_ops *ops = pmxdev->desc->ops; + + ops->disable(pmxdev, pmx->pmxdev_selector); + } + mutex_unlock(&pmx->mutex); +} +EXPORT_SYMBOL_GPL(pinmux_disable); + +/** + * pinmux_config() - configure a certain pinmux setting + * @pmx: the pinmux setting to configure + * @param: the parameter to configure + * @data: extra data to be passed to the configuration, also works as a + * pointer to data returned from the function on success + */ +int pinmux_config(struct pinmux *pmx, u16 param, unsigned long *data) +{ + struct pinmux_dev *pmxdev; + const struct pinmux_ops *ops; + int ret = 0; + + if (pmx == NULL) + return -ENODEV; + + pmxdev = pmx->pmxdev; + ops = pmxdev->desc->ops; + + /* This operation is not mandatory to implement */ + if (ops->config) { + mutex_lock(&pmx->mutex); + ret = ops->config(pmxdev, pmx->pmxdev_selector, param, data); + mutex_unlock(&pmx->mutex); + } + + return 0; +} +EXPORT_SYMBOL_GPL(pinmux_config); + +static void pinmux_unclaim_pindescs(int first, int last) +{ + int i; + + for (i = first; i < last; i++) { + struct pin_desc *pindesc; + + spin_lock(&pin_desc_tree_lock); + pindesc = radix_tree_lookup(&pin_desc_tree, i); + spin_unlock(&pin_desc_tree_lock); + if (pindesc) { + /* Mark as unclaimed by drivers or functions */ + pindesc->pmxdev = NULL; + pindesc->function[0] = '\0'; + } + } +} + +/* Helper to claim the individual descs for each pin on a pinmux device */ +static int pinmux_claim_pindescs(struct pinmux_desc *pmxdesc, + struct pinmux_dev *pmxdev) +{ + int i; + + /* Put self as handler of the indicated pin range */ + for (i = pmxdesc->base; i < (pmxdesc->base + pmxdesc->npins); i++) { + struct pin_desc *pindesc; + + /* Check that none of the pins are already there */ + spin_lock(&pin_desc_tree_lock); + pindesc = radix_tree_lookup(&pin_desc_tree, i); + spin_unlock(&pin_desc_tree_lock); + if (pindesc == NULL) { + dev_err(&pmxdev->dev, "pin %d is not registered, yet " + "attempted to add pinmux driver for it\n", i); + return -EINVAL; + } + if (pindesc->pmxdev != NULL) { + dev_err(&pmxdev->dev, "pin %d taken by other pinmux " + "device\n", i); + return -EINVAL; + } + pindesc->pmxdev = pmxdev; + } + return 0; +} + +/** + * pinmux_register() - register a pinmux device + * @pmxdesc: descriptor for this pinmux + * @dev: parent device for this pinmux + * @driver_data: private pinmux data for this pinmux + */ +struct pinmux_dev *pinmux_register(struct pinmux_desc *pmxdesc, + struct device *dev, void *driver_data) +{ + static atomic_t pinmux_no = ATOMIC_INIT(0); + struct pinmux_dev *pmxdev; + int ret; + + if (pmxdesc == NULL) + return ERR_PTR(-EINVAL); + if (pmxdesc->name == NULL || pmxdesc->ops == NULL) + return ERR_PTR(-EINVAL); + /* These functions are mandatory */ + if (!pmxdesc->ops->list_functions || + !pmxdesc->ops->get_function_name || + !pmxdesc->ops->enable || + !pmxdesc->ops->disable) + return ERR_PTR(-EINVAL); + + pmxdev = kzalloc(sizeof(struct pinmux_dev), GFP_KERNEL); + if (pmxdev == NULL) + return ERR_PTR(-ENOMEM); + + mutex_lock(&pinmuxdev_list_mutex); + pmxdev->owner = pmxdesc->owner; + pmxdev->desc = pmxdesc; + pmxdev->driver_data = driver_data; + + /* Register device with sysfs */ + pmxdev->dev.class = &pinmux_class; + pmxdev->dev.parent = dev; + dev_set_name(&pmxdev->dev, "pinmux.%d", + atomic_inc_return(&pinmux_no) - 1); + ret = device_register(&pmxdev->dev); + if (ret != 0) { + put_device(&pmxdev->dev); + kfree(pmxdev); + goto out_err; + } + dev_set_drvdata(&pmxdev->dev, pmxdev); + + ret = pinmux_claim_pindescs(pmxdesc, pmxdev); + if (ret) + goto out_err; + + list_add(&pmxdev->node, &pinmuxdev_list); + mutex_unlock(&pinmuxdev_list_mutex); + return pmxdev; + +out_err: + mutex_unlock(&pinmuxdev_list_mutex); + put_device(&pmxdev->dev); + kfree(pmxdev); + return ERR_PTR(ret); +} +EXPORT_SYMBOL_GPL(pinmux_register); + +/** + * pinmux_unregister() - unregister pinmux + * @pmxdev: pinmux to unregister + * + * Called by pinmux drivers to unregister a pinmux. + */ +void pinmux_unregister(struct pinmux_dev *pmxdev) +{ + if (pmxdev == NULL) + return; + + mutex_lock(&pinmuxdev_list_mutex); + list_del(&pmxdev->node); + device_unregister(&pmxdev->dev); + mutex_unlock(&pinmuxdev_list_mutex); + pinmux_unclaim_pindescs(pmxdev->desc->base, + pmxdev->desc->base + pmxdev->desc->npins); +} +EXPORT_SYMBOL_GPL(pinmux_unregister); + +#ifdef CONFIG_DEBUG_FS + +static int pins_show(struct seq_file *s, void *what) +{ + unsigned pin; + + seq_puts(s, "Pins:\n"); + spin_lock(&pin_desc_tree_lock); + for (pin = 0; pin < num_pins; pin++) { + struct pin_desc *desc; + + desc = radix_tree_lookup(&pin_desc_tree, pin); + + seq_printf(s, "pin %d (%s)\n", pin, + desc->name ? desc->name : "(unnamed)"); + } + spin_unlock(&pin_desc_tree_lock); + + return 0; +} + +static int pinmux_devices_show(struct seq_file *s, void *what) +{ + struct pinmux_dev *pmxdev; + + seq_puts(s, "Available pinmux settings per pinmux device:\n"); + list_for_each_entry(pmxdev, &pinmuxdev_list, node) { + const struct pinmux_ops *ops = pmxdev->desc->ops; + unsigned selector = 0; + + seq_printf(s, "Device %s:\n", pmxdev->desc->name); + while (ops->list_functions(pmxdev, selector) >= 0) { + unsigned *pins; + unsigned num_pins; + const char *func = ops->get_function_name(pmxdev, + selector); + int ret; + int i; + + ret = ops->get_function_pins(pmxdev, selector, + &pins, &num_pins); + + if (ret) + seq_printf(s, "%s [ERROR GETTING PINS]\n", + func); + + else { + seq_printf(s, "function: %s, pins = [ ", func); + for (i = 0; i < num_pins; i++) + seq_printf(s, "%d ", pins[i]); + seq_puts(s, "]\n"); + } + + selector++; + + } + } + + return 0; +} + +static int pinmux_maps_show(struct seq_file *s, void *what) +{ + struct pinmux *pmx; + const struct pinmux_map *map; + + seq_puts(s, "Pinmux maps:\n"); + list_for_each_entry(pmx, &pinmux_list, node) { + map = pmx->map; + + seq_printf(s, "map: %s -> %s\n", map->function, + pmx->dev ? dev_name(pmx->dev) : "(unassigned)"); + } + + return 0; +} + +static int pinmux_pins_show(struct seq_file *s, void *what) +{ + unsigned pin; + + seq_puts(s, "Pinmux settings per pin\n"); + seq_puts(s, "Format: pin (name): pinmuxfunction pinmuxdriver\n"); + spin_lock(&pin_desc_tree_lock); + for (pin = 0; pin < num_pins; pin++) { + struct pin_desc *desc; + struct pinmux_dev *pmxdev; + + desc = radix_tree_lookup(&pin_desc_tree, pin); + pmxdev = desc->pmxdev; + + seq_printf(s, "pin %d (%s): %s", pin, + desc->name ? desc->name : "(unnamed)", + desc->requested ? desc->function : "(unclaimed)"); + + if (pmxdev && pmxdev->desc->ops->dbg_show) + pmxdev->desc->ops->dbg_show(pmxdev, s, + pin - pmxdev->desc->base); + + seq_puts(s, "\n"); + } + spin_unlock(&pin_desc_tree_lock); + + return 0; +} + +static int pins_open(struct inode *inode, struct file *file) +{ + return single_open(file, pins_show, NULL); +} + +static int pinmux_devices_open(struct inode *inode, struct file *file) +{ + return single_open(file, pinmux_devices_show, NULL); +} + +static int pinmux_maps_open(struct inode *inode, struct file *file) +{ + return single_open(file, pinmux_maps_show, NULL); +} + +static int pinmux_pins_open(struct inode *inode, struct file *file) +{ + return single_open(file, pinmux_pins_show, NULL); +} + +static const struct file_operations pins_ops = { + .open = pins_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static const struct file_operations pinmux_devices_ops = { + .open = pinmux_devices_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static const struct file_operations pinmux_maps_ops = { + .open = pinmux_maps_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static const struct file_operations pinmux_pins_ops = { + .open = pinmux_pins_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static struct dentry *debugfs_root; + +static void pinctrl_init_debugfs(void) +{ + debugfs_root = debugfs_create_dir("pinctrl", NULL); + if (IS_ERR(debugfs_root) || !debugfs_root) { + pr_warn("failed to create debugfs directory\n"); + debugfs_root = NULL; + return; + } + + debugfs_create_file("pins", S_IFREG | S_IRUGO, + debugfs_root, NULL, &pins_ops); + debugfs_create_file("pinmux-devices", S_IFREG | S_IRUGO, + debugfs_root, NULL, &pinmux_devices_ops); + debugfs_create_file("pinmux-maps", S_IFREG | S_IRUGO, + debugfs_root, NULL, &pinmux_maps_ops); + debugfs_create_file("pinmux-pins", S_IFREG | S_IRUGO, + debugfs_root, NULL, &pinmux_pins_ops); +} + +#else /* CONFIG_DEBUG_FS */ + +static void pinctrl_init_debugfs(void) +{ +} + +#endif + +static int __init pinctrl_init(void) +{ + int ret; + + ret = class_register(&pinmux_class); + pr_info("initialized pinctrl subsystem\n"); + + pinctrl_init_debugfs(); + return ret; +} + +/* init early since many drivers really need to initialized pinmux early */ +core_initcall(pinctrl_init); diff --git a/include/linux/pinctrl/machine.h b/include/linux/pinctrl/machine.h new file mode 100644 index 0000000..1bc29f7 --- /dev/null +++ b/include/linux/pinctrl/machine.h @@ -0,0 +1,57 @@ +/* + * Machine interface for the pinctrl subsystem. + * + * Copyright (C) 2011 ST-Ericsson SA + * Written on behalf of Linaro for ST-Ericsson + * Based on bits of regulator core, gpio core and clk core + * + * Author: Linus Walleij <linus.walleij(a)linaro.org> + * + * License terms: GNU General Public License (GPL) version 2 + */ +#ifndef __LINUX_PINMUX_MACHINE_H +#define __LINUX_PINMUX_MACHINE_H + +/** + * struct pinmux_map - boards/machines shall provide this map for devices + * @function: a functional name for this mapping so it can be passed down + * to the driver to invoke that function and be referenced by this ID + * in e.g. pinmux_get() + * @dev: the device using this specific mapping, may be NULL if you provide + * .dev_name instead (this is more common) + * @dev_name: the name of the device using this specific mapping, the name + * must be the same that will return your struct device* + */ +struct pinmux_map { + const char *function; + struct device *dev; + const char *dev_name; +}; + +/* Convenience macro to set a simple map from a function to a named device */ +#define PINMUX_MAP(a, b) { .function = a, .dev_name = b } + +/** + * struct pinctrl_pin_desc - boards/machines provide information on their + * pins, pads or other muxable units in this struct + * @number: unique pin number from the global pin number space + * @name: a name for this pin + */ +struct pinctrl_pin_desc { + unsigned number; + const char *name; +}; + +/* Convenience macro to define a single named or anonymous pin descriptor */ +#define PINCTRL_PIN(a, b) { .number = a, .name = b } +#define PINCTRL_PIN_ANON(a) { .number = a } + +extern int pinctrl_register_pins_sparse(struct pinctrl_pin_desc const *pins, + unsigned num_descs); +extern int pinctrl_register_pins_dense(struct pinctrl_pin_desc const *pins, + unsigned num_descs, unsigned num_pins); +extern int pinctrl_register_anon_pins(unsigned first, unsigned last); +extern int pinmux_register_mappings(struct pinmux_map const *map, + unsigned num_maps); + +#endif diff --git a/include/linux/pinctrl/pinmux.h b/include/linux/pinctrl/pinmux.h new file mode 100644 index 0000000..7b40893 --- /dev/null +++ b/include/linux/pinctrl/pinmux.h @@ -0,0 +1,180 @@ +/* + * Interface the pinmux subsystem + * + * Copyright (C) 2011 ST-Ericsson SA + * Written on behalf of Linaro for ST-Ericsson + * Based on bits of regulator core, gpio core and clk core + * + * Author: Linus Walleij <linus.walleij(a)linaro.org> + * + * License terms: GNU General Public License (GPL) version 2 + */ +#ifndef __LINUX_PINCTRL_PINMUX_H +#define __LINUX_PINCTRL_PINMUX_H + +#include <linux/list.h> +#include <linux/seq_file.h> + +struct pinmux; + +#ifdef CONFIG_PINCTRL + +struct pinmux_dev; + +/** + * struct pinmux_ops - pinmux operations, to be implemented by drivers + * @request: called by the core to see if a certain pin can be muxed in + * and made available in a certain mux setting The driver is allowed + * to answer "no" by returning a negative error code + * @list_functions: list the number of selectable named functions available + * in this pinmux driver, the core will begin on 0 and call this + * repeatedly as long as it returns >= 0 to enumerate mux settings + * @get_function_name: return the function name of the muxing selector, + * called by the core to figure out which mux setting it shall map a + * certain device to + * @get_function_pins: return an array of pins corresponding to a certain + * function selector in @pins, and the size of the array in @num_pins + * @enable: enable a certain muxing enumerator. The driver does not need to + * figure out whether enabling this function conflicts some other use + * of the pins, such collisions are handled by the pinmux subsystem + * @disable: disable a certain muxing enumerator + * @config: custom configuration function for a certain muxing enumerator - + * this works a bit like an ioctl() and can pass in and return arbitrary + * configuration data to the pinmux + * @gpio_request_enable: requests and enables GPIO on a certain pin. + * Implement this only if you can mux every pin individually as GPIO. If + * your gpio assignments are grouped, so you cannot control the GPIO + * muxing of every indvidual pin. + * @dbg_show: optional debugfs display hook that will provide per-device + * info for a certain pin in debugfs + */ +struct pinmux_ops { + int (*request) (struct pinmux_dev *pmxdev, unsigned offset); + int (*free) (struct pinmux_dev *pmxdev, unsigned offset); + int (*list_functions) (struct pinmux_dev *pmxdev, unsigned selector); + const char *(*get_function_name) (struct pinmux_dev *pmxdev, + unsigned selector); + int (*get_function_pins) (struct pinmux_dev *pmxdev, unsigned selector, + unsigned ** const pins, unsigned * const num_pins); + int (*enable) (struct pinmux_dev *pmxdev, unsigned selector); + void (*disable) (struct pinmux_dev *pmxdev, unsigned selector); + int (*config) (struct pinmux_dev *pmxdev, unsigned selector, + u16 param, unsigned long *data); + int (*gpio_request_enable) (struct pinmux_dev *pmxdev, unsigned offset); + void (*dbg_show) (struct pinmux_dev *pmxdev, struct seq_file *s, + unsigned offset); +}; + +/** + * struct pinmux_desc - pinmux descriptor, register this to pinmux subsystem + * @name: name for the pinmux + * @ops: pinmux operation table + * @owner: module providing the pinmux, used for refcounting + * @base: the number of the first pin handled by this pinmux, in the global + * pin space, subtracted from a given pin to get the offset into the range + * of a certain pinmux + * @npins: the number of pins handled by this pinmux - note that + * this is the number of possible pin settings, if your driver handles + * 8 pins that each can be muxed in 3 different ways, you reserve 24 + * pins in the global pin space and set this to 24 + */ +struct pinmux_desc { + const char *name; + struct pinmux_ops *ops; + struct module *owner; + int base; + int npins; +}; + +/** + * struct pinmux_dev - pinmux class device + * @desc: the descriptor supplied when initializing this pinmux + * @node: node to include this pinmux in the global pinmux list + * @dev: the device entry for this pinmux + * @owner: module providing the pinmux, used for refcounting + * @driver_data: driver data for drivers registering to the subsystem + * + * This should be dereferenced and used by the pinmux core ONLY + */ +struct pinmux_dev { + struct pinmux_desc *desc; + struct list_head node; + struct device dev; + struct module *owner; + void *driver_data; +}; + +/* These should only be used from drives */ +static inline const char *pmxdev_get_name(struct pinmux_dev *pmxdev) +{ + /* We're not allowed to register devices without name */ + return pmxdev->desc->name; +} + +static inline void *pmxdev_get_drvdata(struct pinmux_dev *pmxdev) +{ + return pmxdev->driver_data; +} + +/* External interface to pinmux */ +extern int pin_is_valid(int pin); +extern int pinmux_request_gpio(int pin, unsigned gpio); +extern void pinmux_free_gpio(int pin); +extern struct pinmux *pinmux_get(struct device *dev, const char *func); +extern void pinmux_put(struct pinmux *pmx); +extern int pinmux_enable(struct pinmux *pmx); +extern void pinmux_disable(struct pinmux *pmx); +extern int pinmux_config(struct pinmux *pmx, u16 param, unsigned long *data); +extern struct pinmux_dev *pinmux_register(struct pinmux_desc *pmxdesc, + struct device *dev, void *driver_data); +extern void pinmux_unregister(struct pinmux_dev *pmxdev); + +#else /* !CONFIG_PINMUX */ + +static inline int pin_is_valid(int pin) +{ + return pin >= 0; +} + +static inline int pinmux_request_gpio(int pin, unsigned gpio) +{ + return 0; +} + +static inline void pinmux_free_gpio(int pin) +{ +} + +static inline int pinmux_register_mappings(struct pinmux_map const *map, + unsigned num_maps) +{ + return 0; +} + +static inline struct pinmux *pinmux_get(struct device *dev, const char *func) +{ + return NULL; +} + +static inline void pinmux_put(struct pinmux *pmx) +{ +} + +static inline int pinmux_enable(struct pinmux *pmx) +{ + return 0; +} + +static inline void pinmux_disable(struct pinmux *pmx) +{ +} + +static inline int pinmux_config(struct pinmux *pmx, u16 param, + unsigned long *data) +{ + return 0; +} + +#endif /* CONFIG_PINMUX */ + +#endif /* __LINUX_PINCTRL_PINMUX_H */ -- 1.7.3.2

13 years, 9 months

Please register for Linaro Connect Q4.11

by Stephen Doel

Hi All, Please can I encourage you to register and organise your attendance at Linaro Connect Q4.11 as soon as possible. In particular: · if you're going to need a visa you should register now so we can get the process going with your respective embassy · if you need internal company approvals for attendance, make sure its underway - and let me know if you need any additional supporting information · if you are a Canonical secondee to Linaro, you should register to Linaro Connect (not UDS) The hotel registration and booking details are now here: http://connect.linaro.org/events/event/linaro-connect-q411/ Schedule information should be following in early September. We will archive the existing connect(a)linaro.org e-mail alias after this e-mail and switch over to a new list containing delegates who have registered for Q4.11 - an additional reason to register. Thx Stephen Doel Chief Operating Officer T: +44 1223 45 00 23 │ M: +44 77 66 014 247 <http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs Follow Linaro: <http://www.facebook.com/pages/Linaro/155974581091106> Facebook | <http://twitter.com/#!/linaroorg> Twitter | <http://www.linaro.org/linaro-blog/> Blog

13 years, 9 months

[PATCH 2/2] pinmux: add a driver for the U300 pinmux

by Linus Walleij

From: Linus Walleij <linus.walleij(a)linaro.org> This adds a driver for the U300 pinmux portions of the system controller "SYSCON". It also serves as an example of how to use the pinmux subsystem. This driver also houses the platform data for the only supported platform. Signed-off-by: Linus Walleij <linus.walleij(a)linaro.org> --- arch/arm/mach-u300/core.c | 19 ++ drivers/pinctrl/pinmux-u300.c | 433 +++++++++++++++++++++++++++++++++++++++++ drivers/pinctrl/pinmux-u300.h | 141 +++++++++++++ 3 files changed, 593 insertions(+), 0 deletions(-) create mode 100644 drivers/pinctrl/pinmux-u300.c create mode 100644 drivers/pinctrl/pinmux-u300.h diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c index 513d6ab..d52e0bd 100644 --- a/arch/arm/mach-u300/core.c +++ b/arch/arm/mach-u300/core.c @@ -25,6 +25,7 @@ #include <linux/err.h> #include <linux/mtd/nand.h> #include <linux/mtd/fsmc.h> +#include <linux/pinctrl/machine.h> #include <asm/types.h> #include <asm/setup.h> @@ -1630,6 +1631,20 @@ static struct platform_device dma_device = { }, }; +static struct platform_device pinmux_device = { + .name = "pinmux-u300", + .id = -1, + .num_resources = ARRAY_SIZE(pinmux_resources), + .resource = pinmux_resources, +}; + +/* Padmux settings */ +static struct pinmux_map u300_padmux_map[] = { + PINMUX_MAP("mmc0", "mmci"), + PINMUX_MAP("spi0", "pl022"), + PINMUX_MAP("uart0", "uart0"), +}; + /* * Notice that AMBA devices are initialized before platform devices. * @@ -1828,6 +1843,10 @@ void __init u300_init_devices(void) u300_assign_physmem(); + /* Initialize pinmuxing */ + pinmux_register_mappings(u300_padmux_map, + ARRAY_SIZE(u300_padmux_map)); + /* Register subdevices on the I2C buses */ u300_i2c_register_board_devices(); diff --git a/drivers/pinctrl/pinmux-u300.c b/drivers/pinctrl/pinmux-u300.c new file mode 100644 index 0000000..da26789 --- /dev/null +++ b/drivers/pinctrl/pinmux-u300.c @@ -0,0 +1,433 @@ +/* + * Driver for the U300 pinmux + * + * Based on the original U300 padmux functions + * Copyright (C) 2009-2011 ST-Ericsson AB + * Author: Martin Persson <martin.persson(a)stericsson.com> + * Author: Linus Walleij <linus.walleij(a)linaro.org> + * + * The DB3350 design and control registers are oriented around pads rather than + * pins, so we enumerate the pads we can mux rather than actual pins. The pads + * are connected to different pins in different packaging types, so it would + * be confusing. + */ +#include <linux/init.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/io.h> +#include <linux/slab.h> +#include <linux/err.h> +/* + * Usually you want the board to define the pins, but we have only one board, + * so let us do it all in this all-encompassing file. + */ +#include <linux/pinctrl/machine.h> +#include <linux/pinctrl/pinmux.h> + +#include "pinmux-u300.h" + +#define DRIVER_NAME "pinmux-u300" + +/* + * The DB3350 has 467 pads, I have enumerated the pads clockwise around the + * edges of the silicon, finger by finger. LTCORNER upper left is pad 0. + * Data taken from the PadRing chart, arranged like this: + * + * 0 ..... 104 + * 466 105 + * . . + * . . + * 358 224 + * 357 .... 225 + */ +#define U300_NUM_PADS 467 + +/* Pad names for the pinmux subsystem */ +const struct pinctrl_pin_desc __initdata u300_pads[] = { + PINCTRL_PIN(0, "P PAD VDD 28"), + PINCTRL_PIN(1, "P PAD GND 28"), + PINCTRL_PIN(2, "PO SIM RST N"), + PINCTRL_PIN(3, "VSSIO 25"), + PINCTRL_PIN(4, "VSSA ADDA ESDSUB"), + PINCTRL_PIN(5, "PWR VSSCOMMON"), + PINCTRL_PIN(6, "PI ADC I1 POS"), + PINCTRL_PIN(7, "PI ADC I1 NEG"), + PINCTRL_PIN(8, "PWR VSSAD0"), + PINCTRL_PIN(9, "PWR VCCAD0"), + PINCTRL_PIN(10, "PI ADC Q1 NEG"), + PINCTRL_PIN(11, "PI ADC Q1 POS"), + PINCTRL_PIN(12, "PWR VDDAD"), + PINCTRL_PIN(13, "PWR GNDAD"), + PINCTRL_PIN(14, "PI ADC I2 POS"), + PINCTRL_PIN(15, "PI ADC I2 NEG"), + PINCTRL_PIN(16, "PWR VSSAD1"), + PINCTRL_PIN(17, "PWR VCCAD1"), + PINCTRL_PIN(18, "PI ADC Q2 NEG"), + PINCTRL_PIN(19, "PI ADC Q2 POS"), + PINCTRL_PIN(20, "VSSA ADDA ESDSUB"), + PINCTRL_PIN(21, "PWR VCCGPAD"), + PINCTRL_PIN(22, "PI TX POW"), + PINCTRL_PIN(23, "PWR VSSGPAD"), + PINCTRL_PIN(24, "PO DAC I POS"), + PINCTRL_PIN(25, "PO DAC I NEG"), + PINCTRL_PIN(26, "PO DAC Q POS"), + PINCTRL_PIN(27, "PO DAC Q NEG"), + PINCTRL_PIN(28, "PWR VSSDA"), + PINCTRL_PIN(29, "PWR VCCDA"), + PINCTRL_PIN(30, "VSSA ADDA ESDSUB"), + PINCTRL_PIN(31, "P PAD VDDIO 11"), + PINCTRL_PIN(32, "PI PLL 26 FILTVDD"), + PINCTRL_PIN(33, "PI PLL 26 VCONT"), + PINCTRL_PIN(34, "PWR AGNDPLL2V5 32 13"), + PINCTRL_PIN(35, "PWR AVDDPLL2V5 32 13"), + PINCTRL_PIN(36, "VDDA PLL ESD"), + PINCTRL_PIN(37, "VSSA PLL ESD"), + PINCTRL_PIN(38, "VSS PLL"), + PINCTRL_PIN(39, "VDDC PLL"), + PINCTRL_PIN(40, "PWR AGNDPLL2V5 26 60"), + PINCTRL_PIN(41, "PWR AVDDPLL2V5 26 60"), + PINCTRL_PIN(42, "PWR AVDDPLL2V5 26 208"), + PINCTRL_PIN(43, "PWR AGNDPLL2V5 26 208"), + PINCTRL_PIN(44, "PWR AVDDPLL2V5 13 208"), + PINCTRL_PIN(45, "PWR AGNDPLL2V5 13 208"), + PINCTRL_PIN(46, "P PAD VSSIO 11"), + PINCTRL_PIN(47, "P PAD VSSIO 12"), + PINCTRL_PIN(48, "PI POW RST N"), + PINCTRL_PIN(49, "VDDC IO"), + PINCTRL_PIN(50, "P PAD VDDIO 16"), + PINCTRL_PIN(134, "UART0 RTS"), + PINCTRL_PIN(135, "UART0 CTS"), + PINCTRL_PIN(136, "UART0 TX"), + PINCTRL_PIN(137, "UART0 RX"), + PINCTRL_PIN(166, "MMC DATA DIR LS"), + PINCTRL_PIN(167, "MMC DATA 3"), + PINCTRL_PIN(168, "MMC DATA 2"), + PINCTRL_PIN(169, "MMC DATA 1"), + PINCTRL_PIN(170, "MMC DATA 0"), + PINCTRL_PIN(171, "MMC CMD DIR LS"), + PINCTRL_PIN(176, "MMC CMD"), + PINCTRL_PIN(177, "MMC CLK"), + PINCTRL_PIN(420, "SPI CLK"), + PINCTRL_PIN(421, "SPI DO"), + PINCTRL_PIN(422, "SPI DI"), + PINCTRL_PIN(423, "SPI CS0"), + PINCTRL_PIN(424, "SPI CS1"), + PINCTRL_PIN(425, "SPI CS2"), +}; + +/** + * @dev: a pointer back to containing device + * @virtbase: the offset to the controller in virtual memory + */ +struct u300_pmx { + struct device *dev; + struct pinmux_dev *pmx; + u32 phybase; + u32 physize; + void __iomem *virtbase; +}; + +/** + * u300_pmx_registers - the array of registers read/written for each pinmux + * shunt setting + */ +const u32 u300_pmx_registers[] = { + U300_SYSCON_PMC1LR, + U300_SYSCON_PMC1HR, + U300_SYSCON_PMC2R, + U300_SYSCON_PMC3R, + U300_SYSCON_PMC4R, +}; + +/** + * struct pmx_onmask - mask bits to enable/disable padmux + * @mask: mask bits to disable + * @val: mask bits to enable + * + * onmask lazy dog: + * onmask = { + * {"PMC1LR" mask, "PMC1LR" value}, + * {"PMC1HR" mask, "PMC1HR" value}, + * {"PMC2R" mask, "PMC2R" value}, + * {"PMC3R" mask, "PMC3R" value}, + * {"PMC4R" mask, "PMC4R" value} + * } + */ +struct u300_pmx_mask { + u16 mask; + u16 bits; +}; + +/** + * struct u300_pmx_func - describes a U300 pinmux function + * @name: the name of this specific function + * @pins: an array of discrete physical pins used in this mapping, taken + * from the global pin enumeration space + * @num_pins: the number of pins in this mapping array, i.e. the number of + * elements in .pins so we can iterate over that array + * @onmask: bits to set to enable this muxing + */ +struct u300_pmx_func { + const char *name; + const unsigned int *pins; + const unsigned num_pins; + const struct u300_pmx_mask *mask; +}; + +static const unsigned uart0_pins[] = { 134, 135, 136, 137 }; +static const unsigned mmc0_pins[] = { 166, 167, 168, 169, 170, 171, 176, 177 }; +static const unsigned spi0_pins[] = { 420, 421, 422, 423, 424, 425 }; + +static const struct u300_pmx_mask uart0_mask[] = { + {0, 0}, + { + U300_SYSCON_PMC1HR_APP_UART0_1_MASK | + U300_SYSCON_PMC1HR_APP_UART0_2_MASK, + U300_SYSCON_PMC1HR_APP_UART0_1_UART0 | + U300_SYSCON_PMC1HR_APP_UART0_2_UART0 + }, + {0, 0}, + {0, 0}, + {0, 0}, +}; + +static const struct u300_pmx_mask mmc0_mask[] = { + { U300_SYSCON_PMC1LR_MMCSD_MASK, U300_SYSCON_PMC1LR_MMCSD_MMCSD}, + {0, 0}, + {0, 0}, + {0, 0}, + { U300_SYSCON_PMC4R_APP_MISC_12_MASK, + U300_SYSCON_PMC4R_APP_MISC_12_APP_GPIO } +}; + +static const struct u300_pmx_mask spi0_mask[] = { + {0, 0}, + { + U300_SYSCON_PMC1HR_APP_SPI_2_MASK | + U300_SYSCON_PMC1HR_APP_SPI_CS_1_MASK | + U300_SYSCON_PMC1HR_APP_SPI_CS_2_MASK, + U300_SYSCON_PMC1HR_APP_SPI_2_SPI | + U300_SYSCON_PMC1HR_APP_SPI_CS_1_SPI | + U300_SYSCON_PMC1HR_APP_SPI_CS_2_SPI + }, + {0, 0}, + {0, 0}, + {0, 0} +}; + +static const struct u300_pmx_func u300_pmx_funcs[] = { + { + .name = "uart0", + .pins = uart0_pins, + .num_pins = ARRAY_SIZE(uart0_pins), + .mask = uart0_mask, + }, + { + .name = "mmc0", + .pins = mmc0_pins, + .num_pins = ARRAY_SIZE(mmc0_pins), + .mask = mmc0_mask, + }, + { + .name = "spi0", + .pins = spi0_pins, + .num_pins = ARRAY_SIZE(spi0_pins), + .mask = spi0_mask, + }, +}; + +static void u300_pmx_endisable(struct u300_pmx *upmx, unsigned selector, + bool enable) +{ + u16 regval, val, mask; + int i; + + for (i = 0; i < ARRAY_SIZE(u300_pmx_registers); i++) { + if (enable) + val = u300_pmx_funcs[selector].mask->bits; + else + val = 0; + + mask = u300_pmx_funcs[selector].mask->mask; + if (mask != 0) { + regval = readw(upmx->virtbase + u300_pmx_registers[i]); + regval &= ~mask; + regval |= val; + writew(regval, upmx->virtbase + u300_pmx_registers[i]); + } + } +} + +static int u300_pmx_enable(struct pinmux_dev *pmxdev, unsigned selector) +{ + struct u300_pmx *upmx; + + if (selector >= ARRAY_SIZE(u300_pmx_funcs)) + return -EINVAL; + upmx = pmxdev_get_drvdata(pmxdev); + u300_pmx_endisable(upmx, selector, true); + + return 0; +} + +static void u300_pmx_disable(struct pinmux_dev *pmxdev, unsigned selector) +{ + struct u300_pmx *upmx; + + if (selector >= ARRAY_SIZE(u300_pmx_funcs)) + return; + upmx = pmxdev_get_drvdata(pmxdev); + u300_pmx_endisable(upmx, selector, false); +} + +static int u300_pmx_list(struct pinmux_dev *pmxdev, unsigned selector) +{ + if (selector >= ARRAY_SIZE(u300_pmx_funcs)) + return -EINVAL; + return 0; +} + +static const char *u300_pmx_get_fname(struct pinmux_dev *pmxdev, + unsigned selector) +{ + if (selector >= ARRAY_SIZE(u300_pmx_funcs)) + return NULL; + return u300_pmx_funcs[selector].name; +} + +static int u300_pmx_get_pins(struct pinmux_dev *pmxdev, unsigned selector, + unsigned ** const pins, unsigned * const num_pins) +{ + if (selector >= ARRAY_SIZE(u300_pmx_funcs)) + return -EINVAL; + *pins = (unsigned *) u300_pmx_funcs[selector].pins; + *num_pins = u300_pmx_funcs[selector].num_pins; + return 0; +} + +static void u300_dbg_show(struct pinmux_dev *pmxdev, struct seq_file *s, + unsigned offset) +{ + seq_printf(s, " " DRIVER_NAME); +} + +static struct pinmux_ops u300_pmx_ops = { + .list_functions = u300_pmx_list, + .get_function_name = u300_pmx_get_fname, + .get_function_pins = u300_pmx_get_pins, + .enable = u300_pmx_enable, + .disable = u300_pmx_disable, + .dbg_show = u300_dbg_show, +}; + +static struct pinmux_desc u300_pmx_desc = { + .name = DRIVER_NAME, + .ops = &u300_pmx_ops, + .owner = THIS_MODULE, + .base = 0, + .npins = U300_NUM_PADS, +}; + +static int __init u300_pmx_probe(struct platform_device *pdev) +{ + int ret; + struct u300_pmx *upmx; + struct resource *res; + + /* First register all pads */ + ret = pinctrl_register_pins_dense(u300_pads, + ARRAY_SIZE(u300_pads), + U300_NUM_PADS); + if (ret) { + dev_err(&pdev->dev, "could not register U300 pads\n"); + return ret; + } + + /* Then create state holders etc for this driver */ + upmx = kzalloc(sizeof(struct u300_pmx), GFP_KERNEL); + if (!upmx) + return -ENOMEM; + + upmx->dev = &pdev->dev; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + ret = -ENOENT; + goto out_no_resource; + } + upmx->phybase = res->start; + upmx->physize = resource_size(res); + + if (request_mem_region(upmx->phybase, upmx->physize, + DRIVER_NAME) == NULL) { + ret = -EBUSY; + goto out_no_memregion; + } + + upmx->virtbase = ioremap(upmx->phybase, upmx->physize); + if (!upmx->virtbase) { + ret = -ENOMEM; + goto out_no_remap; + } + + upmx->pmx = pinmux_register(&u300_pmx_desc, &pdev->dev, upmx); + if (IS_ERR(upmx->pmx)) { + dev_err(&pdev->dev, "could not register U300 pinmux driver\n"); + ret = PTR_ERR(upmx->pmx); + goto out_no_pmx; + } + platform_set_drvdata(pdev, upmx); + + dev_info(&pdev->dev, "initialized U300 pinmux driver\n"); + + return 0; + +out_no_pmx: + iounmap(upmx->virtbase); +out_no_remap: + platform_set_drvdata(pdev, NULL); +out_no_memregion: + release_mem_region(upmx->phybase, upmx->physize); +out_no_resource: + kfree(upmx); + return ret; +} + +static int __exit u300_pmx_remove(struct platform_device *pdev) +{ + struct u300_pmx *upmx = platform_get_drvdata(pdev); + + if (upmx) { + pinmux_unregister(upmx->pmx); + iounmap(upmx->virtbase); + release_mem_region(upmx->phybase, upmx->physize); + platform_set_drvdata(pdev, NULL); + kfree(upmx); + } + + return 0; +} + +static struct platform_driver u300_pmx_driver = { + .driver = { + .name = DRIVER_NAME, + .owner = THIS_MODULE, + }, + .remove = __exit_p(u300_pmx_remove), +}; + +static int __init u300_pmx_init(void) +{ + return platform_driver_probe(&u300_pmx_driver, u300_pmx_probe); +} +arch_initcall(u300_pmx_init); + +static void __exit u300_pmx_exit(void) +{ + platform_driver_unregister(&u300_pmx_driver); +} +module_exit(u300_pmx_exit); + +MODULE_AUTHOR("Linus Walleij <linus.walleij(a)linaro.org>"); +MODULE_DESCRIPTION("U300 Padmux driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/pinmux-u300.h b/drivers/pinctrl/pinmux-u300.h new file mode 100644 index 0000000..c2ec260 --- /dev/null +++ b/drivers/pinctrl/pinmux-u300.h @@ -0,0 +1,141 @@ +/* + * Register definitions for the U300 Padmux control registers in the + * system controller + */ + +/* PAD MUX Control register 1 (LOW) 16bit (R/W) */ +#define U300_SYSCON_PMC1LR (0x007C) +#define U300_SYSCON_PMC1LR_MASK (0xFFFF) +#define U300_SYSCON_PMC1LR_CDI_MASK (0xC000) +#define U300_SYSCON_PMC1LR_CDI_CDI (0x0000) +#define U300_SYSCON_PMC1LR_CDI_EMIF (0x4000) +/* For BS335 */ +#define U300_SYSCON_PMC1LR_CDI_CDI2 (0x8000) +#define U300_SYSCON_PMC1LR_CDI_WCDMA_APP_GPIO (0xC000) +/* For BS365 */ +#define U300_SYSCON_PMC1LR_CDI_GPIO (0x8000) +#define U300_SYSCON_PMC1LR_CDI_WCDMA (0xC000) +/* Common defs */ +#define U300_SYSCON_PMC1LR_PDI_MASK (0x3000) +#define U300_SYSCON_PMC1LR_PDI_PDI (0x0000) +#define U300_SYSCON_PMC1LR_PDI_EGG (0x1000) +#define U300_SYSCON_PMC1LR_PDI_WCDMA (0x3000) +#define U300_SYSCON_PMC1LR_MMCSD_MASK (0x0C00) +#define U300_SYSCON_PMC1LR_MMCSD_MMCSD (0x0000) +#define U300_SYSCON_PMC1LR_MMCSD_MSPRO (0x0400) +#define U300_SYSCON_PMC1LR_MMCSD_DSP (0x0800) +#define U300_SYSCON_PMC1LR_MMCSD_WCDMA (0x0C00) +#define U300_SYSCON_PMC1LR_ETM_MASK (0x0300) +#define U300_SYSCON_PMC1LR_ETM_ACC (0x0000) +#define U300_SYSCON_PMC1LR_ETM_APP (0x0100) +#define U300_SYSCON_PMC1LR_EMIF_1_CS2_MASK (0x00C0) +#define U300_SYSCON_PMC1LR_EMIF_1_CS2_STATIC (0x0000) +#define U300_SYSCON_PMC1LR_EMIF_1_CS2_NFIF (0x0040) +#define U300_SYSCON_PMC1LR_EMIF_1_CS2_SDRAM (0x0080) +#define U300_SYSCON_PMC1LR_EMIF_1_CS2_STATIC_2GB (0x00C0) +#define U300_SYSCON_PMC1LR_EMIF_1_CS1_MASK (0x0030) +#define U300_SYSCON_PMC1LR_EMIF_1_CS1_STATIC (0x0000) +#define U300_SYSCON_PMC1LR_EMIF_1_CS1_NFIF (0x0010) +#define U300_SYSCON_PMC1LR_EMIF_1_CS1_SDRAM (0x0020) +#define U300_SYSCON_PMC1LR_EMIF_1_CS1_SEMI (0x0030) +#define U300_SYSCON_PMC1LR_EMIF_1_CS0_MASK (0x000C) +#define U300_SYSCON_PMC1LR_EMIF_1_CS0_STATIC (0x0000) +#define U300_SYSCON_PMC1LR_EMIF_1_CS0_NFIF (0x0004) +#define U300_SYSCON_PMC1LR_EMIF_1_CS0_SDRAM (0x0008) +#define U300_SYSCON_PMC1LR_EMIF_1_CS0_SEMI (0x000C) +#define U300_SYSCON_PMC1LR_EMIF_1_MASK (0x0003) +#define U300_SYSCON_PMC1LR_EMIF_1_STATIC (0x0000) +#define U300_SYSCON_PMC1LR_EMIF_1_SDRAM0 (0x0001) +#define U300_SYSCON_PMC1LR_EMIF_1_SDRAM1 (0x0002) +#define U300_SYSCON_PMC1LR_EMIF_1 (0x0003) +/* PAD MUX Control register 2 (HIGH) 16bit (R/W) */ +#define U300_SYSCON_PMC1HR (0x007E) +#define U300_SYSCON_PMC1HR_MASK (0xFFFF) +#define U300_SYSCON_PMC1HR_MISC_2_MASK (0xC000) +#define U300_SYSCON_PMC1HR_MISC_2_APP_GPIO (0x0000) +#define U300_SYSCON_PMC1HR_MISC_2_MSPRO (0x4000) +#define U300_SYSCON_PMC1HR_MISC_2_DSP (0x8000) +#define U300_SYSCON_PMC1HR_MISC_2_AAIF (0xC000) +#define U300_SYSCON_PMC1HR_APP_GPIO_2_MASK (0x3000) +#define U300_SYSCON_PMC1HR_APP_GPIO_2_APP_GPIO (0x0000) +#define U300_SYSCON_PMC1HR_APP_GPIO_2_NFIF (0x1000) +#define U300_SYSCON_PMC1HR_APP_GPIO_2_DSP (0x2000) +#define U300_SYSCON_PMC1HR_APP_GPIO_2_AAIF (0x3000) +#define U300_SYSCON_PMC1HR_APP_GPIO_1_MASK (0x0C00) +#define U300_SYSCON_PMC1HR_APP_GPIO_1_APP_GPIO (0x0000) +#define U300_SYSCON_PMC1HR_APP_GPIO_1_MMC (0x0400) +#define U300_SYSCON_PMC1HR_APP_GPIO_1_DSP (0x0800) +#define U300_SYSCON_PMC1HR_APP_GPIO_1_AAIF (0x0C00) +#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_MASK (0x0300) +#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_APP_GPIO (0x0000) +#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_SPI (0x0100) +#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_AAIF (0x0300) +#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_MASK (0x00C0) +#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_APP_GPIO (0x0000) +#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_SPI (0x0040) +#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_AAIF (0x00C0) +#define U300_SYSCON_PMC1HR_APP_SPI_2_MASK (0x0030) +#define U300_SYSCON_PMC1HR_APP_SPI_2_APP_GPIO (0x0000) +#define U300_SYSCON_PMC1HR_APP_SPI_2_SPI (0x0010) +#define U300_SYSCON_PMC1HR_APP_SPI_2_DSP (0x0020) +#define U300_SYSCON_PMC1HR_APP_SPI_2_AAIF (0x0030) +#define U300_SYSCON_PMC1HR_APP_UART0_2_MASK (0x000C) +#define U300_SYSCON_PMC1HR_APP_UART0_2_APP_GPIO (0x0000) +#define U300_SYSCON_PMC1HR_APP_UART0_2_UART0 (0x0004) +#define U300_SYSCON_PMC1HR_APP_UART0_2_NFIF_CS (0x0008) +#define U300_SYSCON_PMC1HR_APP_UART0_2_AAIF (0x000C) +#define U300_SYSCON_PMC1HR_APP_UART0_1_MASK (0x0003) +#define U300_SYSCON_PMC1HR_APP_UART0_1_APP_GPIO (0x0000) +#define U300_SYSCON_PMC1HR_APP_UART0_1_UART0 (0x0001) +#define U300_SYSCON_PMC1HR_APP_UART0_1_AAIF (0x0003) +/* Padmux 2 control */ +#define U300_SYSCON_PMC2R (0x100) +#define U300_SYSCON_PMC2R_APP_MISC_0_MASK (0x00C0) +#define U300_SYSCON_PMC2R_APP_MISC_0_APP_GPIO (0x0000) +#define U300_SYSCON_PMC2R_APP_MISC_0_EMIF_SDRAM (0x0040) +#define U300_SYSCON_PMC2R_APP_MISC_0_MMC (0x0080) +#define U300_SYSCON_PMC2R_APP_MISC_0_CDI2 (0x00C0) +#define U300_SYSCON_PMC2R_APP_MISC_1_MASK (0x0300) +#define U300_SYSCON_PMC2R_APP_MISC_1_APP_GPIO (0x0000) +#define U300_SYSCON_PMC2R_APP_MISC_1_EMIF_SDRAM (0x0100) +#define U300_SYSCON_PMC2R_APP_MISC_1_MMC (0x0200) +#define U300_SYSCON_PMC2R_APP_MISC_1_CDI2 (0x0300) +#define U300_SYSCON_PMC2R_APP_MISC_2_MASK (0x0C00) +#define U300_SYSCON_PMC2R_APP_MISC_2_APP_GPIO (0x0000) +#define U300_SYSCON_PMC2R_APP_MISC_2_EMIF_SDRAM (0x0400) +#define U300_SYSCON_PMC2R_APP_MISC_2_MMC (0x0800) +#define U300_SYSCON_PMC2R_APP_MISC_2_CDI2 (0x0C00) +#define U300_SYSCON_PMC2R_APP_MISC_3_MASK (0x3000) +#define U300_SYSCON_PMC2R_APP_MISC_3_APP_GPIO (0x0000) +#define U300_SYSCON_PMC2R_APP_MISC_3_EMIF_SDRAM (0x1000) +#define U300_SYSCON_PMC2R_APP_MISC_3_MMC (0x2000) +#define U300_SYSCON_PMC2R_APP_MISC_3_CDI2 (0x3000) +#define U300_SYSCON_PMC2R_APP_MISC_4_MASK (0xC000) +#define U300_SYSCON_PMC2R_APP_MISC_4_APP_GPIO (0x0000) +#define U300_SYSCON_PMC2R_APP_MISC_4_EMIF_SDRAM (0x4000) +#define U300_SYSCON_PMC2R_APP_MISC_4_MMC (0x8000) +#define U300_SYSCON_PMC2R_APP_MISC_4_ACC_GPIO (0xC000) +/* TODO: More SYSCON registers missing */ +#define U300_SYSCON_PMC3R (0x10c) +#define U300_SYSCON_PMC3R_APP_MISC_11_MASK (0xc000) +#define U300_SYSCON_PMC3R_APP_MISC_11_SPI (0x4000) +#define U300_SYSCON_PMC3R_APP_MISC_10_MASK (0x3000) +#define U300_SYSCON_PMC3R_APP_MISC_10_SPI (0x1000) +/* TODO: Missing other configs */ +#define U300_SYSCON_PMC4R (0x168) +#define U300_SYSCON_PMC4R_APP_MISC_12_MASK (0x0003) +#define U300_SYSCON_PMC4R_APP_MISC_12_APP_GPIO (0x0000) +#define U300_SYSCON_PMC4R_APP_MISC_13_MASK (0x000C) +#define U300_SYSCON_PMC4R_APP_MISC_13_CDI (0x0000) +#define U300_SYSCON_PMC4R_APP_MISC_13_SMIA (0x0004) +#define U300_SYSCON_PMC4R_APP_MISC_13_SMIA2 (0x0008) +#define U300_SYSCON_PMC4R_APP_MISC_13_APP_GPIO (0x000C) +#define U300_SYSCON_PMC4R_APP_MISC_14_MASK (0x0030) +#define U300_SYSCON_PMC4R_APP_MISC_14_CDI (0x0000) +#define U300_SYSCON_PMC4R_APP_MISC_14_SMIA (0x0010) +#define U300_SYSCON_PMC4R_APP_MISC_14_CDI2 (0x0020) +#define U300_SYSCON_PMC4R_APP_MISC_14_APP_GPIO (0x0030) +#define U300_SYSCON_PMC4R_APP_MISC_16_MASK (0x0300) +#define U300_SYSCON_PMC4R_APP_MISC_16_APP_GPIO_13 (0x0000) +#define U300_SYSCON_PMC4R_APP_MISC_16_APP_UART1_CTS (0x0100) +#define U300_SYSCON_PMC4R_APP_MISC_16_EMIF_1_STATIC_CS5_N (0x0200) -- 1.7.3.2

13 years, 9 months

[PATCH 01/11] MFD: DA9052/53 MFD core module v5

by ashishj3

The DA9052/53 is a highly integrated PMIC subsystem with supply domain flexibility to support wide range of high performance application. It provides voltage regulators, GPIO controller, Touch Screen, RTC, Battery control and other functionality. Signed-off-by: David Dajun Chen <dchen(a)diasemi.com> Signed-off-by: Ashish Jangam <ashish.jangam(a)kpitcummins.com> --- Changes since v5: - inline device I/O - Unhandle IRQ return RQ_NONE - Remove register address conversion Changes since v4: - Modify KConfig - Use device registration for detemining chip id - Remove preprocessor directive with runtime bustype variable - Replace module_init() for spi with subsys_initcall() - Remove platform string from MODULE_ALIAS of spi module. Changes since v3: - Code refactored to use REGMAP API. - Add Battery resources. - da9052_set_bits() and da9052_clear_bits() replaced by da9052_reg_update(). - Add support for DA9053 PMIC Changes since v2: - Drop da9052_irqs[] table. - Move struct da9052_subdev_info[]. - Remove initialization of static member. - Care for NULL pdata init(). - Check removal of subdevices on errors. - Remove open source spi code. - Remove '_spi' from the driver name. - Move tbat_lookup table from header file. - Remove irq.h - Remove num_gpio variable from pdata --- drivers/mfd/Kconfig | 26 ++ drivers/mfd/Makefile | 7 + drivers/mfd/da9052-core.c | 391 +++++++++++++++++++ drivers/mfd/da9052-i2c.c | 142 +++++++ drivers/mfd/da9052-irq.c | 173 ++++++++ drivers/mfd/da9052-spi.c | 166 ++++++++ include/linux/mfd/da9052/da9052.h | 93 +++++ include/linux/mfd/da9052/pdata.h | 42 ++ include/linux/mfd/da9052/reg.h | 777 +++++++++++++++++++++++++++++++++++++ 9 files changed, 1817 insertions(+), 0 deletions(-) create mode 100644 drivers/mfd/da9052-core.c create mode 100644 drivers/mfd/da9052-i2c.c create mode 100644 drivers/mfd/da9052-irq.c create mode 100644 drivers/mfd/da9052-spi.c create mode 100644 include/linux/mfd/da9052/da9052.h create mode 100644 include/linux/mfd/da9052/pdata.h create mode 100644 include/linux/mfd/da9052/reg.h diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 21574bd..572a6a8 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -343,6 +343,32 @@ config PMIC_DA903X individual components like LCD backlight, voltage regulators, LEDs and battery-charger under the corresponding menus. +config PMIC_DA9052 + bool + select MFD_CORE + +config MFD_DA9052_SPI + bool "Support Dialog Semiconductor DA9052/53 PMIC variants with SPI" + select REGMAP_SPI + select PMIC_DA9052 + depends on SPI_MASTER=y + help + Support for the Dialog Semiconductor DA9052 PMIC + when controlled using SPI. This driver provides common support + for accessing the device, additional drivers must be enabled in + order to use the functionality of the device. + +config MFD_DA9052_I2C + bool "Support Dialog Semiconductor DA9052/53 PMIC variants with I2C" + select REGMAP_I2C + select PMIC_DA9052 + depends on I2C=y + help + Support for the Dialog Semiconductor DA9052 PMIC + when controlled using I2C. This driver provides common support + for accessing the device, additional drivers must be enabled in + order to use the functionality of the device. + config PMIC_ADP5520 bool "Analog Devices ADP5520/01 MFD PMIC Core Support" depends on I2C=y diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index c580203..89a5837 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -67,6 +67,13 @@ endif obj-$(CONFIG_UCB1400_CORE) += ucb1400_core.o obj-$(CONFIG_PMIC_DA903X) += da903x.o + +da9052-objs := da9052-core.o da9052-irq.o +obj-$(CONFIG_PMIC_DA9052) += da9052.o + +obj-$(CONFIG_MFD_DA9052_SPI) += da9052-spi.o +obj-$(CONFIG_MFD_DA9052_I2C) += da9052-i2c.o + max8925-objs := max8925-core.o max8925-i2c.o obj-$(CONFIG_MFD_MAX8925) += max8925.o obj-$(CONFIG_MFD_MAX8997) += max8997.o max8997-irq.o diff --git a/drivers/mfd/da9052-core.c b/drivers/mfd/da9052-core.c new file mode 100644 index 0000000..e45a17a --- /dev/null +++ b/drivers/mfd/da9052-core.c @@ -0,0 +1,391 @@ +/* + * Device access for Dialog DA9052 PMICs. + * + * Copyright(c) 2011 Dialog Semiconductor Ltd. + * + * Author: David Dajun Chen <dchen(a)diasemi.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include <linux/device.h> +#include <linux/delay.h> +#include <linux/input.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/mutex.h> +#include <linux/mfd/core.h> +#include <linux/slab.h> + +#include <linux/mfd/da9052/da9052.h> +#include <linux/mfd/da9052/pdata.h> +#include <linux/mfd/da9052/reg.h> + +#define DA9052_IRQ_DCIN 0 +#define DA9052_IRQ_VBUS 1 +#define DA9052_IRQ_DCINREM 2 +#define DA9052_IRQ_VBUSREM 3 +#define DA9052_IRQ_ALARM 5 +#define DA9052_IRQ_NONKEY 8 +#define DA9052_IRQ_CHGEND 11 +#define DA9052_IRQ_TBAT 12 +#define DA9052_IRQ_PENDOWN 14 +#define DA9052_IRQ_TSIREADY 15 + +/* + * TBAT look-up table is computed from the R90 reg (8 bit register) + * reading as below. The battery temperature is in milliCentigrade + * TBAT = (1/(t1+1/298) - 273) * 1000 mC + * where t1 = (1/B)* ln(( ADCval * 2.5)/(R25*ITBAT*255)) + * Default values are R25 = 10e3, B = 3380, ITBAT = 50e-6 + * Example: + * R25=10E3, B=3380, ITBAT=50e-6, ADCVAL=62d calculates + * TBAT = 20015 mili degrees Centrigrade + * +*/ +static const int32_t tbat_lookup[255] = { + 183258, 144221, 124334, 111336, 101826, 94397, 88343, 83257, + 78889, 75071, 71688, 68656, 65914, 63414, 61120, 59001, + 570366, 55204, 53490, 51881, 50364, 48931, 47574, 46285, + 45059, 43889, 42772, 41703, 40678, 39694, 38748, 37838, + 36961, 36115, 35297, 34507, 33743, 33002, 32284, 31588, + 30911, 30254, 29615, 28994, 28389, 27799, 27225, 26664, + 26117, 25584, 25062, 24553, 24054, 23567, 23091, 22624, + 22167, 21719, 21281, 20851, 20429, 20015, 19610, 19211, + 18820, 18436, 18058, 17688, 17323, 16965, 16612, 16266, + 15925, 15589, 15259, 14933, 14613, 14298, 13987, 13681, + 13379, 13082, 12788, 12499, 12214, 11933, 11655, 11382, + 11112, 10845, 10582, 10322, 10066, 9812, 9562, 9315, + 9071, 8830, 8591, 8356, 8123, 7893, 7665, 7440, + 7218, 6998, 6780, 6565, 6352, 6141, 5933, 5726, + 5522, 5320, 5120, 4922, 4726, 4532, 4340, 4149, + 3961, 3774, 3589, 3406, 3225, 3045, 2867, 2690, + 2516, 2342, 2170, 2000, 1831, 1664, 1498, 1334, + 1171, 1009, 849, 690, 532, 376, 221, 67, + -84, -236, -386, -535, -683, -830, -975, -1119, + -1263, -1405, -1546, -1686, -1825, -1964, -2101, -2237, + -2372, -2506, -2639, -2771, -2902, -3033, -3162, -3291, + -3418, -3545, -3671, -3796, -3920, -4044, -4166, -4288, + -4409, -4529, -4649, -4767, -4885, -5002, -5119, -5235, + -5349, -5464, -5577, -5690, -5802, -5913, -6024, -6134, + -6244, -6352, -6461, -6568, -6675, -6781, -6887, -6992, + -7096, -7200, -7303, -7406, -7508, -7609, -7710, -7810, + -7910, -8009, -8108, -8206, -8304, -8401, -8497, -8593, + -8689, -8784, -8878, -8972, -9066, -9159, -9251, -9343, + -9435, -9526, -9617, -9707, -9796, -9886, -9975, -10063, + -10151, -10238, -10325, -10412, -10839, -10923, -11007, -11090, + -11173, -11256, -11338, -11420, -11501, -11583, -11663, -11744, + -11823, -11903, -11982 +}; + +static const u8 chan_mux[DA9052_ADC_VBBAT + 1] = { + [DA9052_ADC_VDDOUT] = DA9052_ADC_MAN_MUXSEL_VDDOUT, + [DA9052_ADC_ICH] = DA9052_ADC_MAN_MUXSEL_ICH, + [DA9052_ADC_TBAT] = DA9052_ADC_MAN_MUXSEL_TBAT, + [DA9052_ADC_VBAT] = DA9052_ADC_MAN_MUXSEL_VBAT, + [DA9052_ADC_IN4] = DA9052_ADC_MAN_MUXSEL_AD4, + [DA9052_ADC_IN5] = DA9052_ADC_MAN_MUXSEL_AD5, + [DA9052_ADC_IN6] = DA9052_ADC_MAN_MUXSEL_AD6, + [DA9052_ADC_VBBAT] = DA9052_ADC_MAN_MUXSEL_VBBAT +}; + +int da9052_adc_manual_read(struct da9052 *da9052, unsigned char channel) +{ + unsigned long timeout; + unsigned short calc_data; + unsigned short data; + int ret; + unsigned char mux_sel; + + if (channel > DA9052_ADC_VBBAT) + return -EINVAL; + + /* Channel gets activated on enabling the Conversion bit */ + mux_sel = chan_mux[channel] | DA9052_ADC_MAN_MAN_CONV; + + mutex_lock(&da9052->auxadc_lock); + + ret = da9052_reg_read(da9052, DA9052_ADC_MAN_REG); + if (ret < 0) + goto err; + + if (ret & DA9052_ADC_MAN_MAN_CONV) { + ret = -EBUSY; + goto err; + } + + ret = da9052_reg_write(da9052, DA9052_ADC_MAN_REG, mux_sel); + if (ret < 0) + goto err; + + mutex_unlock(&da9052->auxadc_lock); + + timeout = jiffies + msecs_to_jiffies(100); + do { + ret = da9052_reg_read(da9052, DA9052_ADC_MAN_REG); + if (ret < 0) + return ret; + + if (!(ret & DA9052_ADC_MAN_MAN_CONV)) { + timeout = 0; + break; + } + + } while (time_before(jiffies, timeout)); + + if (timeout != 0) + return -EBUSY; + + ret = da9052_reg_read(da9052, DA9052_ADC_RES_H_REG); + if (ret < 0) + return ret; + + calc_data = (unsigned short)ret; + data = calc_data << 2; + + ret = da9052_reg_read(da9052, DA9052_ADC_RES_L_REG); + if (ret < 0) + return ret; + + calc_data = (unsigned short)(ret & DA9052_ADC_RES_LSB); + data |= calc_data; + + return data; + +err: + mutex_unlock(&da9052->auxadc_lock); + return ret; +} +EXPORT_SYMBOL_GPL(da9052_adc_manual_read); + +int da9052_adc_temperature_read(struct da9052 *da9052) +{ + int tbat; + + tbat = da9052_reg_read(da9052, DA9052_TBAT_RES_REG); + + if (tbat < 0) + return tbat; + + if (tbat == 0) { + pr_debug("TBAT R[90] = 0 is undefined.\n"); + return -EINVAL; + } + + /* ARRAY_SIZE check is not needed since TBAT is a 8-bit register */ + return tbat_lookup[tbat - 1]; +} +EXPORT_SYMBOL_GPL(da9052_adc_temperature_read); + +inline int da9052_reg_read(struct da9052 *da9052, unsigned char reg) +{ + int val, ret; + + if (reg > DA9052_MAX_REG_CNT) { + dev_err(da9052->dev, "invalid reg %x\n", reg); + return -EINVAL; + } + + ret = regmap_read(da9052->regmap, reg, &val); + if (ret < 0) + return ret; + return val; +} +EXPORT_SYMBOL_GPL(da9052_reg_read); + +inline int da9052_reg_write(struct da9052 *da9052, unsigned char reg, + unsigned char val) +{ + if (reg > DA9052_MAX_REG_CNT) { + dev_err(da9052->dev, "invalid reg %x\n", reg); + return -EINVAL; + } + + return regmap_write(da9052->regmap, reg, val); +} +EXPORT_SYMBOL_GPL(da9052_reg_write); + +inline int da9052_group_read(struct da9052 *da9052, unsigned char reg, + unsigned reg_cnt, unsigned char *val) +{ + if (reg > DA9052_MAX_REG_CNT) { + dev_err(da9052->dev, "invalid reg %x\n", reg); + return -EINVAL; + } + + return regmap_bulk_read(da9052->regmap, reg, val, reg_cnt); +} +EXPORT_SYMBOL_GPL(da9052_group_read); + +inline int da9052_group_write(struct da9052 *da9052, unsigned char reg, + unsigned reg_cnt, unsigned char *val) +{ + return regmap_raw_write(da9052->regmap, reg, val, reg_cnt); +} +EXPORT_SYMBOL_GPL(da9052_group_write); + +inline int da9052_reg_update(struct da9052 *da9052, unsigned char reg, + unsigned char bit_mask, unsigned char reg_val) +{ + if (reg > DA9052_MAX_REG_CNT) { + dev_err(da9052->dev, "invalid reg %x\n", reg); + return -EINVAL; + } + + return regmap_update_bits(da9052->regmap, reg, bit_mask, reg_val); +} +EXPORT_SYMBOL_GPL(da9052_reg_update); + +static struct resource da9052_rtc_resource = { + .name = "ALM", + .start = DA9052_IRQ_ALARM, + .end = DA9052_IRQ_ALARM, + .flags = IORESOURCE_IRQ, +}; + +static struct resource da9052_onkey_resource = { + .name = "ONKEY", + .start = DA9052_IRQ_NONKEY, + .end = DA9052_IRQ_NONKEY, + .flags = IORESOURCE_IRQ, +}; + +static struct resource da9052_power_resources[] = { + { + .name = "BATT TEMP", + .start = DA9052_IRQ_TBAT, + .end = DA9052_IRQ_TBAT, + .flags = IORESOURCE_IRQ, + }, + { + .name = "DCIN DET", + .start = DA9052_IRQ_DCIN, + .end = DA9052_IRQ_DCIN, + .flags = IORESOURCE_IRQ, + }, + { + .name = "DCIN REM", + .start = DA9052_IRQ_DCINREM, + .end = DA9052_IRQ_DCINREM, + .flags = IORESOURCE_IRQ, + }, + { + .name = "VBUS DET", + .start = DA9052_IRQ_VBUS, + .end = DA9052_IRQ_VBUS, + .flags = IORESOURCE_IRQ, + }, + { + .name = "VBUS REM", + .start = DA9052_IRQ_VBUSREM, + .end = DA9052_IRQ_VBUSREM, + .flags = IORESOURCE_IRQ, + }, + { + .name = "CHG END", + .start = DA9052_IRQ_CHGEND, + .end = DA9052_IRQ_CHGEND, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource da9052_tsi_resources[] = { + { + .name = "PENDWN", + .start = DA9052_IRQ_PENDOWN, + .end = DA9052_IRQ_PENDOWN, + .flags = IORESOURCE_IRQ, + }, + { + .name = "TSIRDY", + .start = DA9052_IRQ_TSIREADY, + .end = DA9052_IRQ_TSIREADY, + .flags = IORESOURCE_IRQ, + }, +}; + +int da9052_add_regulator_devices(struct da9052 *da9052, + struct da9052_pdata *pdata) +{ + struct platform_device *pdev; + int i, ret; + + for (i = 0; i < pdata->num_regulators; i++) { + pdev = platform_device_alloc("da9052-regulator", i); + if (!pdev) + return -ENOMEM; + + pdev->dev.parent = da9052->dev; + ret = platform_device_add(pdev); + if (ret) { + platform_device_put(pdev); + return ret; + } + } + + return 0; +} + +static struct mfd_cell __initdata da9052_subdev_info[] = { + {"da9052-onkey", .resources = &da9052_onkey_resource, + .num_resources = 1}, + {"da9052-rtc", .resources = &da9052_rtc_resource, + .num_resources = 1}, + {"da9052-gpio"}, + {"da9052-hwmon"}, + {"da9052-leds"}, + {"da9052-wled1"}, + {"da9052-wled2"}, + {"da9052-wled3"}, + {"da9052-tsi", .resources = da9052_tsi_resources, + .num_resources = ARRAY_SIZE(da9052_tsi_resources)}, + {"da9052-bat", .resources = da9052_power_resources, + .num_resources = ARRAY_SIZE(da9052_power_resources)}, + {"da9052-watchdog"}, +}; + +int da9052_device_init(struct da9052 *da9052, u8 chip_id) +{ + struct da9052_pdata *pdata = da9052->dev->platform_data; + int ret; + + mutex_init(&da9052->io_lock); + mutex_init(&da9052->auxadc_lock); + + if (pdata->init != NULL) + pdata->init(da9052); + + da9052->chip_id = chip_id; + + ret = da9052_add_regulator_devices(da9052, pdata); + if (ret) + goto err; + + ret = mfd_add_devices(da9052->dev, -1, da9052_subdev_info, + ARRAY_SIZE(da9052_subdev_info), NULL, 0); + if (ret) + goto err; + + ret = da9052_irq_init(da9052, pdata); + if (ret != 0) + goto err; + + return 0; + +err: + mfd_remove_devices(da9052->dev); + return ret; +} + +void da9052_device_exit(struct da9052 *da9052) +{ + mfd_remove_devices(da9052->dev); + da9052_irq_exit(da9052); +} + +MODULE_AUTHOR("David Dajun Chen <dchen(a)diasemi.com>"); +MODULE_DESCRIPTION("DA9052 MFD Core"); +MODULE_LICENSE("GPL"); diff --git a/drivers/mfd/da9052-i2c.c b/drivers/mfd/da9052-i2c.c new file mode 100644 index 0000000..0124141 --- /dev/null +++ b/drivers/mfd/da9052-i2c.c @@ -0,0 +1,142 @@ +/* + * I2C access for DA9052 PMICs. + * + * Copyright(c) 2011 Dialog Semiconductor Ltd. + * + * Author: David Dajun Chen <dchen(a)diasemi.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ + +#include <linux/device.h> +#include <linux/input.h> +#include <linux/mfd/core.h> +#include <linux/i2c.h> +#include <linux/err.h> + +#include <linux/mfd/da9052/da9052.h> +#include <linux/mfd/da9052/reg.h> + +static int da9052_i2c_enable_multiwrite(struct da9052 *da9052) +{ + int reg_val, ret; + + ret = regmap_read(da9052->regmap, DA9052_CONTROL_B_REG, &reg_val); + if (ret < 0) + return ret; + + if (reg_val & DA9052_CONTROL_B_WRITEMODE) { + reg_val = ~DA9052_CONTROL_B_WRITEMODE; + ret = regmap_write(da9052->regmap, DA9052_CONTROL_B_REG, + reg_val); + if (ret < 0) + return ret; + } + + return 0; +} + +static struct regmap_config da9052_regmap_config = { + .reg_bits = 8, + .val_bits = 8, +}; + +static int __devinit da9052_i2c_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct da9052 *da9052_i2c; + int ret; + + da9052_i2c = kzalloc(sizeof(struct da9052), GFP_KERNEL); + if (!da9052_i2c) + return -ENOMEM; + + if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) { + dev_info(&client->dev, "Error in %s:i2c_check_functionality\n", + __func__); + return -ENODEV; + } + + da9052_i2c->bustype = BUS_I2C; + da9052_i2c->dev = &client->dev; + + i2c_set_clientdata(client, da9052_i2c); + + da9052_i2c->regmap = regmap_init_i2c(client, &da9052_regmap_config); + if (IS_ERR(da9052_i2c->regmap)) { + ret = PTR_ERR(da9052_i2c->regmap); + dev_err(&client->dev, "Failed to allocate register map: %d\n", + ret); + goto err; + } + + ret = da9052_i2c_enable_multiwrite(da9052_i2c); + if (ret < 0) + goto err; + + ret = da9052_device_init(da9052_i2c, id->driver_data); + if (ret != 0) + goto err; + + return 0; + +err: + kfree(da9052_i2c); + return ret; +} + +static int da9052_i2c_remove(struct i2c_client *client) +{ + struct da9052 *da9052 = i2c_get_clientdata(client); + + da9052_device_exit(da9052); + kfree(da9052); + + return 0; +} + +static struct i2c_device_id da9052_i2c_id[] = { + {"da9052", DA9052}, + {"da9053-aa", DA9053_AA}, + {"da9053-ba", DA9053_BA}, + {"da9053-bb", DA9053_BB}, + {} +}; + +static struct i2c_driver da9052_i2c_driver = { + .probe = da9052_i2c_probe, + .remove = da9052_i2c_remove, + .id_table = da9052_i2c_id, + .driver = { + .name = "da9052", + .owner = THIS_MODULE, + }, +}; + +static int __init da9052_i2c_init(void) +{ + int ret; + + ret = i2c_add_driver(&da9052_i2c_driver); + if (ret != 0) { + pr_err("DA9052 I2C registration failed %d\n", ret); + return ret; + } + + return 0; +} +subsys_initcall(da9052_i2c_init); + +static void __exit da9052_i2c_exit(void) +{ + i2c_del_driver(&da9052_i2c_driver); +} +module_exit(da9052_i2c_exit); + +MODULE_AUTHOR("David Dajun Chen <dchen(a)diasemi.com>"); +MODULE_DESCRIPTION("I2C driver for Dialog DA9052 PMIC"); +MODULE_LICENSE("GPL"); diff --git a/drivers/mfd/da9052-irq.c b/drivers/mfd/da9052-irq.c new file mode 100644 index 0000000..efbfd79 --- /dev/null +++ b/drivers/mfd/da9052-irq.c @@ -0,0 +1,173 @@ +/* + * Interrupt controller support for Dilaog DA9052 PMICs. + * + * Copyright(c) 2011 Dialog Semiconductor Ltd. + * + * Author: David Dajun Chen <dchen(a)diasemi.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/irq.h> +#include <linux/delay.h> +#include <linux/mfd/core.h> +#include <linux/interrupt.h> + +#include <linux/mfd/da9052/reg.h> +#include <linux/mfd/da9052/da9052.h> +#include <linux/mfd/da9052/pdata.h> + +#define DA9052_FIXME() {udelay(50); } + +static void da9052_irq_lock(struct irq_data *data) +{ + struct da9052 *da9052 = irq_data_get_irq_chip_data(data); + + mutex_lock(&da9052->irq_lock); +} + +static void da9052_irq_sync_unlock(struct irq_data *data) +{ + struct da9052 *da9052 = irq_data_get_irq_chip_data(data); + unsigned int offset, v; + + offset = (data->irq - da9052->irq_base) / 8; + v = (da9052->events_mask >> (offset * 8)) & 0xff; + + da9052_reg_write(da9052, DA9052_IRQ_MASK_A_REG + offset, v); + + mutex_unlock(&da9052->irq_lock); +} + +static void da9052_irq_unmask(struct irq_data *data) +{ + struct da9052 *da9052 = irq_data_get_irq_chip_data(data); + unsigned int mask; + + mask = 1 << ((data->irq - da9052->irq_base) % 8); + + da9052->events_mask &= ~mask; +} + +static void da9052_irq_mask(struct irq_data *data) +{ + struct da9052 *da9052 = irq_data_get_irq_chip_data(data); + unsigned int mask; + + mask = 1 << ((data->irq - da9052->irq_base) % 8); + + da9052->events_mask |= mask; +} + +int da9052_read_events(struct da9052 *da9052, unsigned char reg, + unsigned int *events) +{ + uint8_t v[4] = {0, 0, 0, 0}; + int ret; + + ret = da9052_group_read(da9052, reg, 4, v); + if (ret < 0) + return ret; + + *events = (v[3] << 24) | (v[2] << 16) | (v[1] << 8) | v[0]; + + return 0; +} + +static irqreturn_t da9052_irq_thread(int irq, void *data) +{ + struct da9052 *da9052 = data; + uint8_t v[4] = {0xFF, 0xFF, 0xFF, 0xFF}; + unsigned short i; + unsigned int events; + + if (da9052_read_events(da9052, DA9052_EVENT_A_REG, &events)) + goto err; + + events &= ~da9052->events_mask; + + if (events == 0) + goto err; + + for (i = 0; i < 32; i++) { + if (events & (1 << i)) + handle_nested_irq(da9052->irq_base + i); + } + + da9052_group_write(da9052, DA9052_EVENT_A_REG, 4, v); + + if (da9052->chip_id == DA9052 || da9052->chip_id == DA9053_AA) + DA9052_FIXME(); + + return IRQ_HANDLED; + +err: + return IRQ_NONE; +} + +static struct irq_chip da9052_irq_chip = { + .name = "da9052", + .irq_bus_lock = da9052_irq_lock, + .irq_bus_sync_unlock = da9052_irq_sync_unlock, + .irq_mask = da9052_irq_mask, + .irq_unmask = da9052_irq_unmask, +}; + +int da9052_irq_init(struct da9052 *da9052, struct da9052_pdata *pdata) +{ + int cur_irq; + int ret; + int events; + + da9052->chip_irq = pdata->irq; + da9052->irq_base = pdata->irq_base; + + if (!da9052->chip_irq) { + dev_err(da9052->dev, "No IRQ configured\n"); + return -EINVAL; + } + + mutex_init(&da9052->irq_lock); + + da9052_read_events(da9052, DA9052_IRQ_MASK_A_REG, &events); + da9052->events_mask = events; + + for (cur_irq = da9052->irq_base; cur_irq < 32 + da9052->irq_base; + cur_irq++) { + irq_set_chip_data(cur_irq, da9052); + irq_set_chip_and_handler(cur_irq, &da9052_irq_chip, + handle_simple_irq); + irq_set_nested_thread(cur_irq, 1); + + /* ARM needs us to explicitly flag the IRQ as valid + * and will set them noprobe when we do so. */ +#ifdef CONFIG_ARM + set_irq_flags(cur_irq, IRQF_VALID); +#else + set_irq_noprobe(cur_irq); +#endif + } + + ret = request_threaded_irq(da9052->chip_irq, NULL, da9052_irq_thread, + IRQF_TRIGGER_LOW | IRQF_ONESHOT, + "da9052", da9052); + if (ret != 0) { + dev_err(da9052->dev, "Failed to request IRQ %d: %d\n", + da9052->chip_irq, ret); + return ret; + } + + return 0; +} + +void da9052_irq_exit(struct da9052 *da9052) +{ + if (da9052->chip_irq) + free_irq(da9052->chip_irq, da9052); +} diff --git a/drivers/mfd/da9052-spi.c b/drivers/mfd/da9052-spi.c new file mode 100644 index 0000000..6025eb7 --- /dev/null +++ b/drivers/mfd/da9052-spi.c @@ -0,0 +1,166 @@ +/* + * SPI access for Dialog DA9052 PMICs. + * + * Copyright(c) 2011 Dialog Semiconductor Ltd. + * + * Author: David Dajun Chen <dchen(a)diasemi.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ + +#include <linux/device.h> +#include <linux/input.h> +#include <linux/mfd/core.h> +#include <linux/spi/spi.h> +#include <linux/err.h> + +#include <linux/mfd/da9052/da9052.h> +#include <linux/mfd/da9052/reg.h> + +static struct regmap_config da9052_regmap_config = { + .reg_bits = 8, + .val_bits = 8, +}; + +static int da9052_spi_probe(struct spi_device *spi) +{ + int ret; + u8 chip_id = 0; + struct da9052 *da9052_spi = kzalloc(sizeof(struct da9052), GFP_KERNEL); + + if (!da9052_spi) + return -ENOMEM; + + if (strcmp(spi->modalias, "da9052") == 0) + chip_id = DA9052; + else if (strcmp(spi->modalias, "da9053-aa") == 0) + chip_id = DA9053_AA; + else if (strcmp(spi->modalias, "da9053-ba") == 0) + chip_id = DA9053_BA; + else if (strcmp(spi->modalias, "da9053-bb") == 0) + chip_id = DA9053_BB; + + spi->mode = SPI_MODE_0 | SPI_CPOL; + spi->bits_per_word = 8; + spi_setup(spi); + + da9052_spi->bustype = BUS_SPI; + da9052_spi->dev = &spi->dev; + da9052_spi->spi_dev = spi; + + dev_set_drvdata(&spi->dev, da9052_spi); + + da9052_spi->regmap = regmap_init_spi(spi, &da9052_regmap_config); + if (IS_ERR(da9052_spi->regmap)) { + ret = PTR_ERR(da9052_spi->regmap); + dev_err(&spi->dev, "Failed to allocate register map: %d\n", + ret); + goto err; + } + + ret = da9052_device_init(da9052_spi, chip_id); + if (ret != 0) + goto err; + + return 0; + +err: + kfree(da9052_spi); + return ret; +} + +static int da9052_spi_remove(struct spi_device *spi) +{ + struct da9052 *da9052 = dev_get_drvdata(&spi->dev); + + da9052_device_exit(da9052); + kfree(da9052); + + return 0; +} + +static struct spi_driver da9052_spi_driver = { + .probe = da9052_spi_probe, + .remove = __devexit_p(da9052_spi_remove), + .driver = { + .name = "da9052", + .bus = &spi_bus_type, + .owner = THIS_MODULE, + }, +}; + +static struct spi_driver da9053_aa_spi_driver = { + .probe = da9052_spi_probe, + .remove = __devexit_p(da9052_spi_remove), + .driver = { + .name = "da9053-aa", + .bus = &spi_bus_type, + .owner = THIS_MODULE, + }, +}; + +static struct spi_driver da9053_ba_spi_driver = { + .probe = da9052_spi_probe, + .remove = __devexit_p(da9052_spi_remove), + .driver = { + .name = "da9053-ba", + .bus = &spi_bus_type, + .owner = THIS_MODULE, + }, +}; + +static struct spi_driver da9053_bb_spi_driver = { + .probe = da9052_spi_probe, + .remove = __devexit_p(da9052_spi_remove), + .driver = { + .name = "da9053-bb", + .bus = &spi_bus_type, + .owner = THIS_MODULE, + }, +}; + +static int __init da9052_spi_init(void) +{ + int ret; + + ret = spi_register_driver(&da9052_spi_driver); + if (ret != 0) { + pr_err("Failed to register DA9052 SPI driver, %d\n", ret); + return ret; + } + + ret = spi_register_driver(&da9053_aa_spi_driver); + if (ret != 0) { + pr_err("Failed to register DA9053-AA SPI driver, %d\n", ret); + return ret; + } + + ret = spi_register_driver(&da9053_ba_spi_driver); + if (ret != 0) { + pr_err("Failed to register DA9053-BA SPI driver, %d\n", ret); + return ret; + } + + ret = spi_register_driver(&da9053_bb_spi_driver); + if (ret != 0) { + pr_err("Failed to register DA9053-BB SPI driver, %d\n", ret); + return ret; + } + + return 0; +} +subsys_initcall(da9052_spi_init); + +static void __exit da9052_spi_exit(void) +{ + spi_unregister_driver(&da9052_spi_driver); +} +module_exit(da9052_spi_exit); + +MODULE_AUTHOR("David Dajun Chen <dchen(a)diasemi.com>"); +MODULE_DESCRIPTION("SPI driver for Dialog DA9052 PMIC"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/mfd/da9052/da9052.h b/include/linux/mfd/da9052/da9052.h new file mode 100644 index 0000000..0aee1a3 --- /dev/null +++ b/include/linux/mfd/da9052/da9052.h @@ -0,0 +1,93 @@ +/* + * da9052 declarations for DA952 PMICs. + * + * Copyright(c) 2011 Dialog Semiconductor Ltd. + * + * Author: David Dajun Chen <dchen(a)diasemi.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef __MFD_DA9052_DA9052_H +#define __MFD_DA9052_DA9052_H + +#include <linux/slab.h> +#include <linux/interrupt.h> +#include <linux/mfd/core.h> +#include <linux/regmap.h> + +/* HWMON Channel Definations */ +#define DA9052_ADC_VDDOUT 0 +#define DA9052_ADC_ICH 1 +#define DA9052_ADC_TBAT 2 +#define DA9052_ADC_VBAT 3 +#define DA9052_ADC_IN4 4 +#define DA9052_ADC_IN5 5 +#define DA9052_ADC_IN6 6 +#define DA9052_ADC_TSI 7 +#define DA9052_ADC_TJUNC 8 +#define DA9052_ADC_VBBAT 9 + +enum da9052_chip_id { + DA9052, + DA9053_AA, + DA9053_BA, + DA9053_BB, +}; + +struct da9052_pdata; + +struct da9052 { + struct mutex io_lock; + struct mutex irq_lock; + struct mutex auxadc_lock; + + struct device *dev; + struct spi_device *spi_dev; + struct i2c_client *i2c_client; + struct regmap *regmap; + + int irq_base; + u8 bustype; + u8 chip_id; + u32 events_mask; + + int chip_irq; +}; + +/* ADC API */ +int da9052_adc_manual_read(struct da9052 *da9052, + unsigned char channel); +int da9052_adc_temperature_read(struct da9052 *da9052); + +/* Device I/O API */ +int da9052_reg_read(struct da9052 *da9052, unsigned char reg); +int da9052_reg_write(struct da9052 *da9052, unsigned char reg, + unsigned char val); +int da9052_group_read(struct da9052 *da9052, unsigned char reg, + unsigned bytes, unsigned char *val); +int da9052_group_write(struct da9052 *da9052, unsigned char reg, + unsigned bytes, unsigned char *val); +int da9052_reg_update(struct da9052 *da9052, unsigned char reg, + unsigned char bit_mask, unsigned char reg_val); + +int da9052_device_init(struct da9052 *da9052, u8 chip_id); +void da9052_device_exit(struct da9052 *da9052); + +int da9052_irq_init(struct da9052 *da9052, struct da9052_pdata *pdata); +void da9052_irq_exit(struct da9052 *da9052); + +#endif /* __MFD_DA9052_DA9052_H */ diff --git a/include/linux/mfd/da9052/pdata.h b/include/linux/mfd/da9052/pdata.h new file mode 100644 index 0000000..b56aa7a --- /dev/null +++ b/include/linux/mfd/da9052/pdata.h @@ -0,0 +1,42 @@ +/* + * Platform data declarations for DA9052 PMICs. + * + * Copyright(c) 2011 Dialog Semiconductor Ltd. + * + * Author: David Dajun Chen <dchen(a)diasemi.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef __MFD_DA9052_PDATA_H__ +#define __MFD_DA9052_PDATA_H__ + +#define DA9052_MAX_REGULATORS 15 + +struct da9052; + +struct da9052_pdata { + struct led_platform_data *pled; + int (*init) (struct da9052 *da9052); + int irq; + int irq_base; + int num_regulators; + int gpio_base; + int use_for_apm; + struct regulator_init_data *regulators[DA9052_MAX_REGULATORS]; +}; + +#endif diff --git a/include/linux/mfd/da9052/reg.h b/include/linux/mfd/da9052/reg.h new file mode 100644 index 0000000..9cbd86f --- /dev/null +++ b/include/linux/mfd/da9052/reg.h @@ -0,0 +1,777 @@ +/* + * Register declarations for DA9052 PMICs. + * + * Copyright(c) 2011 Dialog Semiconductor Ltd. + * + * Author: David Dajun Chen <dchen(a)diasemi.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef __LINUX_MFD_DA9052_REG_H +#define __LINUX_MFD_DA9052_REG_H + +#define DA9052_MAX_REG_CNT 128 + +/*STATUS REGISTERS*/ +#define DA9052_STATUS_A_REG 1 +#define DA9052_STATUS_B_REG 2 +#define DA9052_STATUS_C_REG 3 +#define DA9052_STATUS_D_REG 4 + +/*EVENT REGISTERS*/ +#define DA9052_EVENT_A_REG 5 +#define DA9052_EVENT_B_REG 6 +#define DA9052_EVENT_C_REG 7 +#define DA9052_EVENT_D_REG 8 +#define DA9052_FAULTLOG_REG 9 + +/*IRQ REGISTERS*/ +#define DA9052_IRQ_MASK_A_REG 10 +#define DA9052_IRQ_MASK_B_REG 11 +#define DA9052_IRQ_MASK_C_REG 12 +#define DA9052_IRQ_MASK_D_REG 13 + +/*CONTROL REGISTERS*/ +#define DA9052_CONTROL_A_REG 14 +#define DA9052_CONTROL_B_REG 15 +#define DA9052_CONTROL_C_REG 16 +#define DA9052_CONTROL_D_REG 17 + +#define DA9052_PDDIS_REG 18 +#define DA9052_INTERFACE_REG 19 +#define DA9052_RESET_REG 20 + +/*GPIO REGISTERS*/ +#define DA9052_GPIO_0_1_REG 21 +#define DA9052_GPIO_2_3_REG 22 +#define DA9052_GPIO_4_5_REG 23 +#define DA9052_GPIO_6_7_REG 24 +#define DA9052_GPIO_14_15_REG 28 + +/*LDO AND BUCK REGISTERS*/ +#define DA9052_BUCKA_REG 44 +#define DA9052_BUCKB_REG 45 +#define DA9052_BUCKCORE_REG 46 +#define DA9052_BUCKPRO_REG 47 +#define DA9052_BUCKMEM_REG 48 +#define DA9052_BUCKPERI_REG 49 +#define DA9052_LDO1_REG 50 +#define DA9052_LDO2_REG 51 +#define DA9052_LDO3_REG 52 +#define DA9052_LDO4_REG 53 +#define DA9052_LDO5_REG 54 +#define DA9052_LDO6_REG 55 +#define DA9052_LDO7_REG 56 +#define DA9052_LDO8_REG 57 +#define DA9052_LDO9_REG 58 +#define DA9052_LDO10_REG 59 +#define DA9052_SUPPLY_REG 60 +#define DA9052_PULLDOWN_REG 61 +#define DA9052_CHGBUCK_REG 62 +#define DA9052_WAITCONT_REG 63 +#define DA9052_ISET_REG 64 +#define DA9052_BATCHG_REG 65 + +/*BATTERY CONTROL REGISTRS*/ +#define DA9052_CHG_CONT_REG 66 +#define DA9052_INPUT_CONT_REG 67 +#define DA9052_CHG_TIME_REG 68 +#define DA9052_BBAT_CONT_REG 69 + +/*LED CONTROL REGISTERS*/ +#define DA9052_BOOST_REG 70 +#define DA9052_LED_CONT_REG 71 +#define DA9052_LEDMIN123_REG 72 +#define DA9052_LED1_CONF_REG 73 +#define DA9052_LED2_CONF_REG 74 +#define DA9052_LED3_CONF_REG 75 +#define DA9052_LED1CONT_REG 76 +#define DA9052_LED2CONT_REG 77 +#define DA9052_LED3CONT_REG 78 +#define DA9052_LED_CONT_4_REG 79 +#define DA9052_LED_CONT_5_REG 80 + +/*ADC CONTROL REGISTERS*/ +#define DA9052_ADC_MAN_REG 81 +#define DA9052_ADC_CONT_REG 82 +#define DA9052_ADC_RES_L_REG 83 +#define DA9052_ADC_RES_H_REG 84 +#define DA9052_VDD_RES_REG 85 +#define DA9052_VDD_MON_REG 86 + +/*SM CONTROL REGISTERS*/ +#define DA9052_ICHG_AV_REG 87 +#define DA9052_ICHG_THD_REG 88 +#define DA9052_ICHG_END_REG 89 +#define DA9052_TBAT_RES_REG 90 +#define DA9052_TBAT_HIGHP_REG 91 +#define DA9052_TBAT_HIGHIN_REG 92 +#define DA9052_TBAT_LOW_REG 93 +#define DA9052_T_OFFSET_REG 94 + +/*TSI CONTROL REGISTERS*/ +#define DA9052_TJUNC_RES_REG 104 +#define DA9052_TSI_CONT_A_REG 105 +#define DA9052_TSI_CONT_B_REG 106 +#define DA9052_TSI_X_MSB_REG 107 +#define DA9052_TSI_Y_MSB_REG 108 +#define DA9052_TSI_LSB_REG 109 +#define DA9052_TSI_Z_MSB_REG 110 + +/*RTC COUNT REGISTERS*/ +#define DA9052_COUNT_S_REG 111 +#define DA9052_COUNT_MI_REG 112 +#define DA9052_COUNT_H_REG 113 +#define DA9052_COUNT_D_REG 114 +#define DA9052_COUNT_MO_REG 115 +#define DA9052_COUNT_Y_REG 116 + +/*RTC CONTROL REGISTERS*/ +#define DA9052_ALARM_MI_REG 117 +#define DA9052_ALARM_H_REG 118 +#define DA9052_ALARM_D_REG 119 +#define DA9052_ALARM_MO_REG 120 +#define DA9052_ALARM_Y_REG 121 + +/* Reg Page Configuration */ +#define DA9052_PAGECON0_REGPAGE 0x80 + +/* Onkey Event Registers */ +#define DA9052_M_nONKEY 0x0100 +#define DA9052_E_nONKEY 0x01 + +/* TSI Event Registers */ +#define DA9052_E_PEN_DOWN 0x4000 +#define DA9052_E_TSI_READY 0x8000 + +/* PAGE CONFIGURATION 128 REGISTER */ +#define DA9052_PAGECON128_REGPAGE 0x80 + +/* STATUS REGISTER A */ +#define DA9052_STATUSA_VDATDET 0x80 +#define DA9052_STATUSA_VBUSSEL 0x40 +#define DA9052_STATUSA_DCINSEL 0x20 +#define DA9052_STATUSA_VBUSDET 0x10 +#define DA9052_STATUSA_DCINDET 0x08 +#define DA9052_STATUSA_IDGND 0x04 +#define DA9052_STATUSA_IDFLOAT 0x02 +#define DA9052_STATUSA_NONKEY 0x01 + +/* STATUS REGISTER B */ +#define DA9052_STATUSB_COMPDET 0x80 +#define DA9052_STATUSB_SEQUENCING 0x40 +#define DA9052_STATUSB_GPFB2 0x20 +#define DA9052_STATUSB_CHGTO 0x10 +#define DA9052_STATUSB_CHGEND 0x08 +#define DA9052_STATUSB_CHGLIM 0x04 +#define DA9052_STATUSB_CHGPRE 0x02 +#define DA9052_STATUSB_CHGATT 0x01 + +/* STATUS REGISTER C */ +#define DA9052_STATUSC_GPI7 0x80 +#define DA9052_STATUSC_GPI6 0x40 +#define DA9052_STATUSC_GPI5 0x20 +#define DA9052_STATUSC_GPI4 0x10 +#define DA9052_STATUSC_GPI3 0x08 +#define DA9052_STATUSC_GPI2 0x04 +#define DA9052_STATUSC_GPI1 0x02 +#define DA9052_STATUSC_GPI0 0x01 + +/* STATUS REGISTER D */ +#define DA9052_STATUSD_GPI15 0x80 +#define DA9052_STATUSD_GPI14 0x40 +#define DA9052_STATUSD_GPI13 0x20 +#define DA9052_STATUSD_GPI12 0x10 +#define DA9052_STATUSD_GPI11 0x08 +#define DA9052_STATUSD_GPI10 0x04 +#define DA9052_STATUSD_GPI9 0x02 +#define DA9052_STATUSD_GPI8 0x01 + +/* EVENT REGISTER A */ +#define DA9052_EVENTA_ECOMP1V2 0x80 +#define DA9052_EVENTA_ESEQRDY 0x40 +#define DA9052_EVENTA_EALRAM 0x20 +#define DA9052_EVENTA_EVDDLOW 0x10 +#define DA9052_EVENTA_EVBUSREM 0x08 +#define DA9052_EVENTA_EDCINREM 0x04 +#define DA9052_EVENTA_EVBUSDET 0x02 +#define DA9052_EVENTA_EDCINDET 0x01 + +/* EVENT REGISTER B */ +#define DA9052_EVENTB_ETSIREADY 0x80 +#define DA9052_EVENTB_EPENDOWN 0x40 +#define DA9052_EVENTB_EADCEOM 0x20 +#define DA9052_EVENTB_ETBAT 0x10 +#define DA9052_EVENTB_ECHGEND 0x08 +#define DA9052_EVENTB_EIDGND 0x04 +#define DA9052_EVENTB_EIDFLOAT 0x02 +#define DA9052_EVENTB_ENONKEY 0x01 + +/* EVENT REGISTER C */ +#define DA9052_EVENTC_EGPI7 0x80 +#define DA9052_EVENTC_EGPI6 0x40 +#define DA9052_EVENTC_EGPI5 0x20 +#define DA9052_EVENTC_EGPI4 0x10 +#define DA9052_EVENTC_EGPI3 0x08 +#define DA9052_EVENTC_EGPI2 0x04 +#define DA9052_EVENTC_EGPI1 0x02 +#define DA9052_EVENTC_EGPI0 0x01 + +/* EVENT REGISTER D */ +#define DA9052_EVENTD_EGPI15 0x80 +#define DA9052_EVENTD_EGPI14 0x40 +#define DA9052_EVENTD_EGPI13 0x20 +#define DA9052_EVENTD_EGPI12 0x10 +#define DA9052_EVENTD_EGPI11 0x08 +#define DA9052_EVENTD_EGPI10 0x04 +#define DA9052_EVENTD_EGPI9 0x02 +#define DA9052_EVENTD_EGPI8 0x01 + +/* FAULT LOG REGISTER */ +#define DA9052_FAULTLOG_WAITSET 0x80 +#define DA9052_FAULTLOG_NSDSET 0x40 +#define DA9052_FAULTLOG_KEYSHUT 0x20 +#define DA9052_FAULTLOG_TEMPOVER 0x08 +#define DA9052_FAULTLOG_VDDSTART 0x04 +#define DA9052_FAULTLOG_VDDFAULT 0x02 +#define DA9052_FAULTLOG_TWDERROR 0x01 + +/* CONTROL REGISTER A */ +#define DA9052_CONTROLA_GPIV 0x80 +#define DA9052_CONTROLA_PMOTYPE 0x20 +#define DA9052_CONTROLA_PMOV 0x10 +#define DA9052_CONTROLA_PMIV 0x08 +#define DA9052_CONTROLA_PMIFV 0x08 +#define DA9052_CONTROLA_PWR1EN 0x04 +#define DA9052_CONTROLA_PWREN 0x02 +#define DA9052_CONTROLA_SYSEN 0x01 + +/* CONTROL REGISTER B */ +#define DA9052_CONTROLB_SHUTDOWN 0x80 +#define DA9052_CONTROLB_DEEPSLEEP 0x40 +#define DA9052_CONTROL_B_WRITEMODE 0x20 +#define DA9052_CONTROLB_BBATEN 0x10 +#define DA9052_CONTROLB_OTPREADEN 0x08 +#define DA9052_CONTROLB_AUTOBOOT 0x04 +#define DA9052_CONTROLB_ACTDIODE 0x02 +#define DA9052_CONTROLB_BUCKMERGE 0x01 + +/* CONTROL REGISTER C */ +#define DA9052_CONTROLC_BLINKDUR 0x80 +#define DA9052_CONTROLC_BLINKFRQ 0x60 +#define DA9052_CONTROLC_DEBOUNCING 0x1C +#define DA9052_CONTROLC_PMFB2PIN 0x02 +#define DA9052_CONTROLC_PMFB1PIN 0x01 + +/* CONTROL REGISTER D */ +#define DA9052_CONTROLD_WATCHDOG 0x80 +#define DA9052_CONTROLD_ACCDETEN 0x40 +#define DA9052_CONTROLD_GPI1415SD 0x20 +#define DA9052_CONTROLD_NONKEYSD 0x10 +#define DA9052_CONTROLD_KEEPACTEN 0x08 +#define DA9052_CONTROLD_TWDSCALE 0x07 +/* POWER DOWN DISABLE REGISTER */ +#define DA9052_PDDIS_PMCONTPD 0x80 +#define DA9052_PDDIS_OUT32KPD 0x40 +#define DA9052_PDDIS_CHGBBATPD 0x20 +#define DA9052_PDDIS_CHGPD 0x10 +#define DA9052_PDDIS_HS2WIREPD 0x08 +#define DA9052_PDDIS_PMIFPD 0x04 +#define DA9052_PDDIS_GPADCPD 0x02 +#define DA9052_PDDIS_GPIOPD 0x01 + +/* CONTROL REGISTER D */ +#define DA9052_INTERFACE_IFBASEADDR 0xE0 +#define DA9052_INTERFACE_NCSPOL 0x10 +#define DA9052_INTERFACE_RWPOL 0x08 +#define DA9052_INTERFACE_CPHA 0x04 +#define DA9052_INTERFACE_CPOL 0x02 +#define DA9052_INTERFACE_IFTYPE 0x01 + +/* CONTROL REGISTER D */ +#define DA9052_RESET_RESETEVENT 0xC0 +#define DA9052_RESET_RESETTIMER 0x3F + +/* GPIO REGISTERS */ + +/* GPIO control register */ +#define DA9052_GPIO_EVEN_PORT_PIN 0x03 +#define DA9052_GPIO_EVEN_PORT_TYPE 0x04 +#define DA9052_GPIO_EVEN_PORT_MODE 0x08 + +#define DA9052_GPIO_ODD_PORT_PIN 0x30 +#define DA9052_GPIO_ODD_PORT_TYPE 0x40 +#define DA9052_GPIO_ODD_PORT_MODE 0x80 + +/*POWER SEQUENCER REGISTER*/ + +/* SEQ control register for ID 0 and 1 */ +#define DA9052_ID01_LDO1STEP 0xF0 +#define DA9052_ID01_SYSPRE 0x04 +#define DA9052_ID01_DEFSUPPLY 0x02 +#define DA9052_ID01_nRESMODE 0x01 + +/* SEQ control register for ID 2 and 3 */ +#define DA9052_ID23_LDO3STEP 0xF0 +#define DA9052_ID23_LDO2STEP 0x0F + +/* SEQ control register for ID 4 and 5 */ +#define DA9052_ID45_LDO5STEP 0xF0 +#define DA9052_ID45_LDO4STEP 0x0F + +/* SEQ control register for ID 6 and 7 */ +#define DA9052_ID67_LDO7STEP 0xF0 +#define DA9052_ID67_LDO6STEP 0x0F + +/* SEQ control register for ID 8 and 9 */ +#define DA9052_ID89_LDO9STEP 0xF0 +#define DA9052_ID89_LDO8STEP 0x0F + +/* SEQ control register for ID 10 and 11 */ +#define DA9052_ID1011_PDDISSTEP 0xF0 +#define DA9052_ID1011_LDO10STEP 0x0F + +/* SEQ control register for ID 12 and 13 */ +#define DA9052_ID1213_VMEMSWSTEP 0xF0 +#define DA9052_ID1213_VPERISWSTEP 0x0F + +/* SEQ control register for ID 14 and 15 */ +#define DA9052_ID1415_BUCKPROSTEP 0xF0 +#define DA9052_ID1415_BUCKCORESTEP 0x0F + +/* SEQ control register for ID 16 and 17 */ +#define DA9052_ID1617_BUCKPERISTEP 0xF0 +#define DA9052_ID1617_BUCKMEMSTEP 0x0F + +/* SEQ control register for ID 18 and 19 */ +#define DA9052_ID1819_GPRISE2STEP 0xF0 +#define DA9052_ID1819_GPRISE1STEP 0x0F + +/* SEQ control register for ID 20 and 21 */ +#define DA9052_ID2021_GPFALL2STEP 0xF0 +#define DA9052_ID2021_GPFALL1STEP 0x0F + +/* Power SEQ Status register */ +#define DA9052_SEQSTATUS_SEQPOINTER 0xF0 +#define DA9052_SEQSTATUS_WAITSTEP 0x0F + +/* Power SEQ A register */ +#define DA9052_SEQA_POWEREND 0xF0 +#define DA9052_SEQA_SYSTEMEND 0x0F + +/* Power SEQ B register */ +#define DA9052_SEQB_PARTDOWN 0xF0 +#define DA9052_SEQB_MAXCOUNT 0x0F + +/* Power SEQ TIMER register */ +#define DA9052_SEQTIMER_SEQDUMMY 0xF0 +#define DA9052_SEQTIMER_SEQTIME 0x0F + +/*POWER SUPPLY CONTROL REGISTER*/ + +/* BUCK REGISTER A */ +#define DA9052_BUCKA_BPROILIM 0xC0 +#define DA9052_BUCKA_BPROMODE 0x30 +#define DA9052_BUCKA_BCOREILIM 0x0C +#define DA9052_BUCKA_BCOREMODE 0x03 + +/* BUCK REGISTER B */ +#define DA9052_BUCKB_BERIILIM 0xC0 +#define DA9052_BUCKB_BPERIMODE 0x30 +#define DA9052_BUCKB_BMEMILIM 0x0C +#define DA9052_BUCKB_BMEMMODE 0x03 + +/* BUCKCORE REGISTER */ +#define DA9052_BUCKCORE_BCORECONF 0x80 +#define DA9052_BUCKCORE_BCOREEN 0x40 +#define DA9052_BUCKCORE_VBCORE 0x3F + +/* BUCKPRO REGISTER */ +#define DA9052_BUCKPRO_BPROCONF 0x80 +#define DA9052_BUCKPRO_BPROEN 0x40 +#define DA9052_BUCKPRO_VBPRO 0x3F + +/* BUCKMEM REGISTER */ +#define DA9052_BUCKMEM_BMEMCONF 0x80 +#define DA9052_BUCKMEM_BMEMEN 0x40 +#define DA9052_BUCKMEM_VBMEM 0x3F + +/* BUCKPERI REGISTER */ +#define DA9052_BUCKPERI_BPERICONF 0x80 +#define DA9052_BUCKPERI_BPERIEN 0x40 +#define DA9052_BUCKPERI_BPERIHS 0x20 +#define DA9052_BUCKPERI_VBPERI 0x1F + +/* LDO1 REGISTER */ +#define DA9052_LDO1_LDO1CONF 0x80 +#define DA9052_LDO1_LDO1EN 0x40 +#define DA9052_LDO1_VLDO1 0x1F + +/* LDO2 REGISTER */ +#define DA9052_LDO2_LDO2CONF 0x80 +#define DA9052_LDO2_LDO2EN 0x40 +#define DA9052_LDO2_VLDO2 0x3F + +/* LDO3 REGISTER */ +#define DA9052_LDO3_LDO3CONF 0x80 +#define DA9052_LDO3_LDO3EN 0x40 +#define DA9052_LDO3_VLDO3 0x3F + +/* LDO4 REGISTER */ +#define DA9052_LDO4_LDO4CONF 0x80 +#define DA9052_LDO4_LDO4EN 0x40 +#define DA9052_LDO4_VLDO4 0x3F + +/* LDO5 REGISTER */ +#define DA9052_LDO5_LDO5CONF 0x80 +#define DA9052_LDO5_LDO5EN 0x40 +#define DA9052_LDO5_VLDO5 0x3F + +/* LDO6 REGISTER */ +#define DA9052_LDO6_LDO6CONF 0x80 +#define DA9052_LDO6_LDO6EN 0x40 +#define DA9052_LDO6_VLDO6 0x3F + +/* LDO7 REGISTER */ +#define DA9052_LDO7_LDO7CONF 0x80 +#define DA9052_LDO7_LDO7EN 0x40 +#define DA9052_LDO7_VLDO7 0x3F + +/* LDO8 REGISTER */ +#define DA9052_LDO8_LDO8CONF 0x80 +#define DA9052_LDO8_LDO8EN 0x40 +#define DA9052_LDO8_VLDO8 0x3F + +/* LDO9 REGISTER */ +#define DA9052_LDO9_LDO9CONF 0x80 +#define DA9052_LDO9_LDO9EN 0x40 +#define DA9052_LDO9_VLDO9 0x3F + +/* LDO10 REGISTER */ +#define DA9052_LDO10_LDO10CONF 0x80 +#define DA9052_LDO10_LDO10EN 0x40 +#define DA9052_LDO10_VLDO10 0x3F + +/* SUPPLY REGISTER */ +#define DA9052_SUPPLY_VLOCK 0x80 +#define DA9052_SUPPLY_VMEMSWEN 0x40 +#define DA9052_SUPPLY_VPERISWEN 0x20 +#define DA9052_SUPPLY_VLDO3GO 0x10 +#define DA9052_SUPPLY_VLDO2GO 0x08 +#define DA9052_SUPPLY_VBMEMGO 0x04 +#define DA9052_SUPPLY_VBPROGO 0x02 +#define DA9052_SUPPLY_VBCOREGO 0x01 + +/* PULLDOWN REGISTER */ +#define DA9052_PULLDOWN_LDO5PDDIS 0x20 +#define DA9052_PULLDOWN_LDO2PDDIS 0x10 +#define DA9052_PULLDOWN_LDO1PDDIS 0x08 +#define DA9052_PULLDOWN_MEMPDDIS 0x04 +#define DA9052_PULLDOWN_PROPDDIS 0x02 +#define DA9052_PULLDOWN_COREPDDIS 0x01 + +/* BAT CHARGER REGISTER */ + +/* CHARGER BUCK REGISTER */ +#define DA9052_CHGBUCK_CHGTEMP 0x80 +#define DA9052_CHGBUCK_CHGUSBILIM 0x40 +#define DA9052_CHGBUCK_CHGBUCKLP 0x20 +#define DA9052_CHGBUCK_CHGBUCKEN 0x10 +#define DA9052_CHGBUCK_ISETBUCK 0x0F + +/* WAIT COUNTER REGISTER */ +#define DA9052_WAITCONT_WAITDIR 0x80 +#define DA9052_WAITCONT_RTCCLOCK 0x40 +#define DA9052_WAITCONT_WAITMODE 0x20 +#define DA9052_WAITCONT_EN32KOUT 0x10 +#define DA9052_WAITCONT_DELAYTIME 0x0F + +/* ISET CONTROL REGISTER */ +#define DA9052_ISET_ISETDCIN 0xF0 +#define DA9052_ISET_ISETVBUS 0x0F + +/* BATTERY CHARGER CONTROL REGISTER */ +#define DA9052_BATCHG_ICHGPRE 0xC0 +#define DA9052_BATCHG_ICHGBAT 0x3F + +/* CHARGER COUNTER REGISTER */ +#define DA9052_CHG_CONT_VCHG_BAT 0xF8 +#define DA9052_CHG_CONT_TCTR 0x07 + +/* INPUT CONTROL REGISTER */ +#define DA9052_INPUT_CONT_TCTR_MODE 0x80 +#define DA9052_INPUT_CONT_VBUS_SUSP 0x10 +#define DA9052_INPUT_CONT_DCIN_SUSP 0x08 + +/* CHARGING TIME REGISTER */ +#define DA9052_CHGTIME_CHGTIME 0xFF + +/* BACKUP BATTERY CONTROL REGISTER */ +#define DA9052_BBATCONT_BCHARGERISET 0xF0 +#define DA9052_BBATCONT_BCHARGERVSET 0x0F + +/* LED REGISTERS */ +/* LED BOOST REGISTER */ +#define DA9052_BOOST_EBFAULT 0x80 +#define DA9052_BOOST_MBFAULT 0x40 +#define DA9052_BOOST_BOOSTFRQ 0x20 +#define DA9052_BOOST_BOOSTILIM 0x10 +#define DA9052_BOOST_LED3INEN 0x08 +#define DA9052_BOOST_LED2INEN 0x04 +#define DA9052_BOOST_LED1INEN 0x02 +#define DA9052_BOOST_BOOSTEN 0x01 + +/* LED CONTROL REGISTER */ +#define DA9052_LEDCONT_SELLEDMODE 0x80 +#define DA9052_LEDCONT_LED3ICONT 0x40 +#define DA9052_LEDCONT_LED3RAMP 0x20 +#define DA9052_LEDCONT_LED3EN 0x10 +#define DA9052_LEDCONT_LED2RAMP 0x08 +#define DA9052_LEDCONT_LED2EN 0x04 +#define DA9052_LEDCONT_LED1RAMP 0x02 +#define DA9052_LEDCONT_LED1EN 0x01 + +/* LEDMIN123 REGISTER */ +#define DA9052_LEDMIN123_LEDMINCURRENT 0xFF + +/* LED1CONF REGISTER */ +#define DA9052_LED1CONF_LED1CURRENT 0xFF + +/* LED2CONF REGISTER */ +#define DA9052_LED2CONF_LED2CURRENT 0xFF + +/* LED3CONF REGISTER */ +#define DA9052_LED3CONF_LED3CURRENT 0xFF + +/* LED COUNT REGISTER */ +#define DA9052_LED_CONT_DIM 0x80 + +/* ADC MAN registers */ +#define DA9052_ADC_MAN_MAN_CONV 0x10 +#define DA9052_ADC_MAN_MUXSEL_VDDOUT 0x0 +#define DA9052_ADC_MAN_MUXSEL_ICH 0x01 +#define DA9052_ADC_MAN_MUXSEL_TBAT 0x02 +#define DA9052_ADC_MAN_MUXSEL_VBAT 0x03 +#define DA9052_ADC_MAN_MUXSEL_AD4 0x04 +#define DA9052_ADC_MAN_MUXSEL_AD5 0x05 +#define DA9052_ADC_MAN_MUXSEL_AD6 0x06 +#define DA9052_ADC_MAN_MUXSEL_VBBAT 0x09 + +/* ADC CONTROL regsisters */ +#define DA9052_ADCCONT_COMP1V2EN 0x80 +#define DA9052_ADCCONT_ADCMODE 0x40 +#define DA9052_ADCCONT_TBATISRCEN 0x20 +#define DA9052_ADCCONT_AD4ISRCEN 0x10 +#define DA9052_ADCCONT_AUTOAD6EN 0x08 +#define DA9052_ADCCONT_AUTOAD5EN 0x04 +#define DA9052_ADCCONT_AUTOAD4EN 0x02 +#define DA9052_ADCCONT_AUTOVDDEN 0x01 + +/* ADC 10 BIT MANUAL CONVERSION RESULT LOW register */ +#define DA9052_ADC_RES_LSB 0x03 + +/* ADC 10 BIT MANUAL CONVERSION RESULT HIGH register */ +#define DA9052_ADCRESH_ADCRESMSB 0xFF + +/* VDD RES regsister*/ +#define DA9052_VDDRES_VDDOUTRES 0xFF + +/* VDD MON regsister*/ +#define DA9052_VDDMON_VDDOUTMON 0xFF + +/* ICHG_AV regsister*/ +#define DA9052_ICHGAV_ICHGAV 0xFF + +/* ICHG_THD regsister*/ +#define DA9052_ICHGTHD_ICHGTHD 0xFF + +/* ICHG_END regsister*/ +#define DA9052_ICHGEND_ICHGEND 0xFF + +/* TBAT_RES regsister*/ +#define DA9052_TBATRES_TBATRES 0xFF + +/* TBAT_HIGHP regsister*/ +#define DA9052_TBATHIGHP_TBATHIGHP 0xFF + +/* TBAT_HIGHN regsister*/ +#define DA9052_TBATHIGHN_TBATHIGHN 0xFF + +/* TBAT_LOW regsister*/ +#define DA9052_TBATLOW_TBATLOW 0xFF + +/* T_OFFSET regsister*/ +#define DA9052_TOFFSET_TOFFSET 0xFF + +/* ADCIN4_RES regsister*/ +#define DA9052_ADCIN4RES_ADCIN4RES 0xFF + +/* ADCIN4_HIGH regsister*/ +#define DA9052_AUTO4HIGH_AUTO4HIGH 0xFF + +/* ADCIN4_LOW regsister*/ +#define DA9052_AUTO4LOW_AUTO4LOW 0xFF + +/* ADCIN5_RES regsister*/ +#define DA9052_ADCIN5RES_ADCIN5RES 0xFF + +/* ADCIN5_HIGH regsister*/ +#define DA9052_AUTO5HIGH_AUTOHIGH 0xFF + +/* ADCIN5_LOW regsister*/ +#define DA9052_AUTO5LOW_AUTO5LOW 0xFF + +/* ADCIN6_RES regsister*/ +#define DA9052_ADCIN6RES_ADCIN6RES 0xFF + +/* ADCIN6_HIGH regsister*/ +#define DA9052_AUTO6HIGH_AUTO6HIGH 0xFF + +/* ADCIN6_LOW regsister*/ +#define DA9052_AUTO6LOW_AUTO6LOW 0xFF + +/* TJUNC_RES regsister*/ +#define DA9052_TJUNCRES_TJUNCRES 0xFF + +/* TSI REGISTER */ + +/* TSI Control Register A */ +#define DA9052_TSICONTA_TSIDELAY 0xC0 +#define DA9052_TSICONTA_TSISKIP 0x38 +#define DA9052_TSICONTA_TSIMODE 0x04 +#define DA9052_TSICONTA_PENDETEN 0x02 +#define DA9052_TSICONTA_AUTOTSIEN 0x01 + +/* TSI Control Register B */ +#define DA9052_TSICONTB_ADCREF 0x80 +#define DA9052_TSICONTB_TSIMAN 0x40 +#define DA9052_TSICONTB_TSIMUX 0x30 +#define DA9052_TSICONTB_TSISEL3 0x08 +#define DA9052_TSICONTB_TSISEL2 0x04 +#define DA9052_TSICONTB_TSISEL1 0x02 +#define DA9052_TSICONTB_TSISEL0 0x01 + +/* TSI X Co-ordinate MSB Result register */ +#define DA9052_TSIXMSB_TSIXM 0xFF + +/* TSI Y Co-ordinate MSB Result register */ +#define DA9052_TSIYMSB_TSIYM 0xFF + +/* TSI Co-ordinate LSB Result register */ +#define DA9052_TSILSB_PENDOWN 0x40 +#define DA9052_TSILSB_TSIZL 0x30 +#define DA9052_TSILSB_TSIYL 0x0C +#define DA9052_TSILSB_TSIXL 0x03 + +/* TSI Z Measurement MSB Result register */ +#define DA9052_TSIZMSB_TSIZM 0xFF + +/* RTC REGISTER */ + +/* RTC TIMER SECONDS REGISTER */ +#define DA9052_COUNTS_MONITOR 0x40 +#define DA9052_RTC_SEC 0x3F + +/* RTC TIMER MINUTES REGISTER */ +#define DA9052_RTC_MIN 0x3F + +/* RTC TIMER HOUR REGISTER */ +#define DA9052_RTC_HOUR 0x1F + +/* RTC TIMER DAYS REGISTER */ +#define DA9052_RTC_DAY 0x1F + +/* RTC TIMER MONTHS REGISTER */ +#define DA9052_RTC_MONTH 0x0F + +/* RTC TIMER YEARS REGISTER */ +#define DA9052_RTC_YEAR 0x3F + +/* RTC ALARM MINUTES REGISTER */ +#define DA9052_ALARMM_I_TICK_TYPE 0x80 +#define DA9052_ALARMMI_ALARMTYPE 0x40 + +/* RTC ALARM YEARS REGISTER */ +#define DA9052_ALARM_Y_TICK_ON 0x80 +#define DA9052_ALARM_Y_ALARM_ON 0x40 + +/* RTC SECONDS REGISTER A*/ +#define DA9052_SECONDA_SECONDSA 0xFF + +/* RTC SECONDS REGISTER B*/ +#define DA9052_SECONDB_SECONDSB 0xFF + +/* RTC SECONDS REGISTER C*/ +#define DA9052_SECONDC_SECONDSC 0xFF + +/* RTC SECONDS REGISTER D*/ +#define DA9052_SECONDD_SECONDSD 0xFF + +/* OTP REGISTER */ + +/* CHIP IDENTIFICATION REGISTER */ +#define DA9052_CHIPID_MRC 0xF0 +#define DA9052_CHIPID_TRC 0x0F + +/* CONFIGURATION IDENTIFICATION REGISTER */ +#define DA9052_CONFIGID_CUSTOMERID 0xF8 +#define DA9052_CONFIGID_CONFID 0x07 + +/* OTP CONTROL REGISTER */ +#define DA9052_OTPCONT_GPWRITEDIS 0x80 +#define DA9052_OTPCONT_OTPCONFLOCK 0x40 +#define DA9052_OTPCONT_OTPGPLOCK 0x20 +#define DA9052_OTPCONT_OTPCONFG 0x08 +#define DA9052_OTPCONT_OTPGP 0x04 +#define DA9052_OTPCONT_OTPRP 0x02 +#define DA9052_OTPCONT_OTPTRANSFER 0x01 + +/* RTC OSCILLATOR TRIM REGISTER */ +#define DA9052_OSCTRIM_TRIM32K 0xFF + +/* GP ID REGISTER 0 */ +#define DA9052_GPID0_GP0 0xFF + +/* GP ID REGISTER 1 */ +#define DA9052_GPID1_GP1 0xFF + +/* GP ID REGISTER 2 */ +#define DA9052_GPID2_GP2 0xFF + +/* GP ID REGISTER 3 */ +#define DA9052_GPID3_GP3 0xFF + +/* GP ID REGISTER 4 */ +#define DA9052_GPID4_GP4 0xFF + +/* GP ID REGISTER 5 */ +#define DA9052_GPID5_GP5 0xFF + +/* GP ID REGISTER 6 */ +#define DA9052_GPID6_GP6 0xFF + +/* GP ID REGISTER 7 */ +#define DA9052_GPID7_GP7 0xFF + +/* GP ID REGISTER 8 */ +#define DA9052_GPID8_GP8 0xFF + +/* GP ID REGISTER 9 */ +#define DA9052_GPID9_GP9 0xFF + +#endif +/* __LINUX_MFD_DA9052_REG_H */

13 years, 9 months

[PATCH 4/4 v4] mach-u300: activate pinmux driver, delete old padmux driver

by Linus Walleij

From: Linus Walleij <linus.walleij(a)linaro.org> This hooks the pinmux driver into the U300 platform and deletes the old machine-specific driver. Signed-off-by: Linus Walleij <linus.walleij(a)linaro.org> --- arch/arm/mach-u300/Kconfig | 2 + arch/arm/mach-u300/Makefile | 2 +- arch/arm/mach-u300/core.c | 12 +- arch/arm/mach-u300/include/mach/syscon.h | 136 ----------- arch/arm/mach-u300/mmc.c | 16 -- arch/arm/mach-u300/padmux.c | 367 ------------------------------ arch/arm/mach-u300/padmux.h | 39 ---- arch/arm/mach-u300/spi.c | 20 -- drivers/pinctrl/pinmux-u300.c | 25 +- 9 files changed, 25 insertions(+), 594 deletions(-) delete mode 100644 arch/arm/mach-u300/padmux.c delete mode 100644 arch/arm/mach-u300/padmux.h diff --git a/arch/arm/mach-u300/Kconfig b/arch/arm/mach-u300/Kconfig index 32a7b0f..449fd6a 100644 --- a/arch/arm/mach-u300/Kconfig +++ b/arch/arm/mach-u300/Kconfig @@ -6,6 +6,8 @@ comment "ST-Ericsson Mobile Platform Products" config MACH_U300 bool "U300" + select PINCTRL + select PINMUX_U300 comment "ST-Ericsson U300/U330/U335/U365 Feature Selections" diff --git a/arch/arm/mach-u300/Makefile b/arch/arm/mach-u300/Makefile index 8fd354a..2855381 100644 --- a/arch/arm/mach-u300/Makefile +++ b/arch/arm/mach-u300/Makefile @@ -2,7 +2,7 @@ # Makefile for the linux kernel, U300 machine. # -obj-y := core.o clock.o timer.o padmux.o +obj-y := core.o clock.o timer.o obj-m := obj-n := obj- := diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c index b0c45c3..c916575 100644 --- a/arch/arm/mach-u300/core.c +++ b/arch/arm/mach-u300/core.c @@ -1536,6 +1536,14 @@ static struct coh901318_platform coh901318_platform = { .max_channels = U300_DMA_CHANNELS, }; +static struct resource pinmux_resources[] = { + { + .start = U300_SYSCON_BASE, + .end = U300_SYSCON_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + static struct platform_device wdog_device = { .name = "coh901327_wdog", .id = -1, @@ -1658,10 +1666,10 @@ static struct platform_device *platform_devs[] __initdata = { &gpio_device, &nand_device, &wdog_device, - &ave_device + &ave_device, + &pinmux_device, }; - /* * Interrupts: the U300 platforms have two pl190 ARM PrimeCells connected * together so some interrupts are connected to the first one and some diff --git a/arch/arm/mach-u300/include/mach/syscon.h b/arch/arm/mach-u300/include/mach/syscon.h index 7444f5c..6e84f07 100644 --- a/arch/arm/mach-u300/include/mach/syscon.h +++ b/arch/arm/mach-u300/include/mach/syscon.h @@ -234,91 +234,6 @@ #define U300_SYSCON_ECCR_EMIF_1_RET_OUT_CLK_EN_N_DISABLE (0x0004) #define U300_SYSCON_ECCR_EMIF_MEMCLK_RET_EN_N_DISABLE (0x0002) #define U300_SYSCON_ECCR_EMIF_SDRCLK_RET_EN_N_DISABLE (0x0001) -/* PAD MUX Control register 1 (LOW) 16bit (R/W) */ -#define U300_SYSCON_PMC1LR (0x007C) -#define U300_SYSCON_PMC1LR_MASK (0xFFFF) -#define U300_SYSCON_PMC1LR_CDI_MASK (0xC000) -#define U300_SYSCON_PMC1LR_CDI_CDI (0x0000) -#define U300_SYSCON_PMC1LR_CDI_EMIF (0x4000) -#ifdef CONFIG_MACH_U300_BS335 -#define U300_SYSCON_PMC1LR_CDI_CDI2 (0x8000) -#define U300_SYSCON_PMC1LR_CDI_WCDMA_APP_GPIO (0xC000) -#elif CONFIG_MACH_U300_BS365 -#define U300_SYSCON_PMC1LR_CDI_GPIO (0x8000) -#define U300_SYSCON_PMC1LR_CDI_WCDMA (0xC000) -#endif -#define U300_SYSCON_PMC1LR_PDI_MASK (0x3000) -#define U300_SYSCON_PMC1LR_PDI_PDI (0x0000) -#define U300_SYSCON_PMC1LR_PDI_EGG (0x1000) -#define U300_SYSCON_PMC1LR_PDI_WCDMA (0x3000) -#define U300_SYSCON_PMC1LR_MMCSD_MASK (0x0C00) -#define U300_SYSCON_PMC1LR_MMCSD_MMCSD (0x0000) -#define U300_SYSCON_PMC1LR_MMCSD_MSPRO (0x0400) -#define U300_SYSCON_PMC1LR_MMCSD_DSP (0x0800) -#define U300_SYSCON_PMC1LR_MMCSD_WCDMA (0x0C00) -#define U300_SYSCON_PMC1LR_ETM_MASK (0x0300) -#define U300_SYSCON_PMC1LR_ETM_ACC (0x0000) -#define U300_SYSCON_PMC1LR_ETM_APP (0x0100) -#define U300_SYSCON_PMC1LR_EMIF_1_CS2_MASK (0x00C0) -#define U300_SYSCON_PMC1LR_EMIF_1_CS2_STATIC (0x0000) -#define U300_SYSCON_PMC1LR_EMIF_1_CS2_NFIF (0x0040) -#define U300_SYSCON_PMC1LR_EMIF_1_CS2_SDRAM (0x0080) -#define U300_SYSCON_PMC1LR_EMIF_1_CS2_STATIC_2GB (0x00C0) -#define U300_SYSCON_PMC1LR_EMIF_1_CS1_MASK (0x0030) -#define U300_SYSCON_PMC1LR_EMIF_1_CS1_STATIC (0x0000) -#define U300_SYSCON_PMC1LR_EMIF_1_CS1_NFIF (0x0010) -#define U300_SYSCON_PMC1LR_EMIF_1_CS1_SDRAM (0x0020) -#define U300_SYSCON_PMC1LR_EMIF_1_CS1_SEMI (0x0030) -#define U300_SYSCON_PMC1LR_EMIF_1_CS0_MASK (0x000C) -#define U300_SYSCON_PMC1LR_EMIF_1_CS0_STATIC (0x0000) -#define U300_SYSCON_PMC1LR_EMIF_1_CS0_NFIF (0x0004) -#define U300_SYSCON_PMC1LR_EMIF_1_CS0_SDRAM (0x0008) -#define U300_SYSCON_PMC1LR_EMIF_1_CS0_SEMI (0x000C) -#define U300_SYSCON_PMC1LR_EMIF_1_MASK (0x0003) -#define U300_SYSCON_PMC1LR_EMIF_1_STATIC (0x0000) -#define U300_SYSCON_PMC1LR_EMIF_1_SDRAM0 (0x0001) -#define U300_SYSCON_PMC1LR_EMIF_1_SDRAM1 (0x0002) -#define U300_SYSCON_PMC1LR_EMIF_1 (0x0003) -/* PAD MUX Control register 2 (HIGH) 16bit (R/W) */ -#define U300_SYSCON_PMC1HR (0x007E) -#define U300_SYSCON_PMC1HR_MASK (0xFFFF) -#define U300_SYSCON_PMC1HR_MISC_2_MASK (0xC000) -#define U300_SYSCON_PMC1HR_MISC_2_APP_GPIO (0x0000) -#define U300_SYSCON_PMC1HR_MISC_2_MSPRO (0x4000) -#define U300_SYSCON_PMC1HR_MISC_2_DSP (0x8000) -#define U300_SYSCON_PMC1HR_MISC_2_AAIF (0xC000) -#define U300_SYSCON_PMC1HR_APP_GPIO_2_MASK (0x3000) -#define U300_SYSCON_PMC1HR_APP_GPIO_2_APP_GPIO (0x0000) -#define U300_SYSCON_PMC1HR_APP_GPIO_2_NFIF (0x1000) -#define U300_SYSCON_PMC1HR_APP_GPIO_2_DSP (0x2000) -#define U300_SYSCON_PMC1HR_APP_GPIO_2_AAIF (0x3000) -#define U300_SYSCON_PMC1HR_APP_GPIO_1_MASK (0x0C00) -#define U300_SYSCON_PMC1HR_APP_GPIO_1_APP_GPIO (0x0000) -#define U300_SYSCON_PMC1HR_APP_GPIO_1_MMC (0x0400) -#define U300_SYSCON_PMC1HR_APP_GPIO_1_DSP (0x0800) -#define U300_SYSCON_PMC1HR_APP_GPIO_1_AAIF (0x0C00) -#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_MASK (0x0300) -#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_APP_GPIO (0x0000) -#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_SPI (0x0100) -#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_AAIF (0x0300) -#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_MASK (0x00C0) -#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_APP_GPIO (0x0000) -#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_SPI (0x0040) -#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_AAIF (0x00C0) -#define U300_SYSCON_PMC1HR_APP_SPI_2_MASK (0x0030) -#define U300_SYSCON_PMC1HR_APP_SPI_2_APP_GPIO (0x0000) -#define U300_SYSCON_PMC1HR_APP_SPI_2_SPI (0x0010) -#define U300_SYSCON_PMC1HR_APP_SPI_2_DSP (0x0020) -#define U300_SYSCON_PMC1HR_APP_SPI_2_AAIF (0x0030) -#define U300_SYSCON_PMC1HR_APP_UART0_2_MASK (0x000C) -#define U300_SYSCON_PMC1HR_APP_UART0_2_APP_GPIO (0x0000) -#define U300_SYSCON_PMC1HR_APP_UART0_2_UART0 (0x0004) -#define U300_SYSCON_PMC1HR_APP_UART0_2_NFIF_CS (0x0008) -#define U300_SYSCON_PMC1HR_APP_UART0_2_AAIF (0x000C) -#define U300_SYSCON_PMC1HR_APP_UART0_1_MASK (0x0003) -#define U300_SYSCON_PMC1HR_APP_UART0_1_APP_GPIO (0x0000) -#define U300_SYSCON_PMC1HR_APP_UART0_1_UART0 (0x0001) -#define U300_SYSCON_PMC1HR_APP_UART0_1_AAIF (0x0003) /* Step one for killing the applications system 16bit (-/W) */ #define U300_SYSCON_KA1R (0x0080) #define U300_SYSCON_KA1R_MASK (0xFFFF) @@ -357,57 +272,6 @@ #define U300_SYSCON_PUCR_EMIF_1_16BIT_PU_ENABLE (0x0080) #define U300_SYSCON_PUCR_EMIF_1_8BIT_PU_ENABLE (0x0040) #define U300_SYSCON_PUCR_KEY_IN_PU_EN_MASK (0x003F) -/* Padmux 2 control */ -#define U300_SYSCON_PMC2R (0x100) -#define U300_SYSCON_PMC2R_APP_MISC_0_MASK (0x00C0) -#define U300_SYSCON_PMC2R_APP_MISC_0_APP_GPIO (0x0000) -#define U300_SYSCON_PMC2R_APP_MISC_0_EMIF_SDRAM (0x0040) -#define U300_SYSCON_PMC2R_APP_MISC_0_MMC (0x0080) -#define U300_SYSCON_PMC2R_APP_MISC_0_CDI2 (0x00C0) -#define U300_SYSCON_PMC2R_APP_MISC_1_MASK (0x0300) -#define U300_SYSCON_PMC2R_APP_MISC_1_APP_GPIO (0x0000) -#define U300_SYSCON_PMC2R_APP_MISC_1_EMIF_SDRAM (0x0100) -#define U300_SYSCON_PMC2R_APP_MISC_1_MMC (0x0200) -#define U300_SYSCON_PMC2R_APP_MISC_1_CDI2 (0x0300) -#define U300_SYSCON_PMC2R_APP_MISC_2_MASK (0x0C00) -#define U300_SYSCON_PMC2R_APP_MISC_2_APP_GPIO (0x0000) -#define U300_SYSCON_PMC2R_APP_MISC_2_EMIF_SDRAM (0x0400) -#define U300_SYSCON_PMC2R_APP_MISC_2_MMC (0x0800) -#define U300_SYSCON_PMC2R_APP_MISC_2_CDI2 (0x0C00) -#define U300_SYSCON_PMC2R_APP_MISC_3_MASK (0x3000) -#define U300_SYSCON_PMC2R_APP_MISC_3_APP_GPIO (0x0000) -#define U300_SYSCON_PMC2R_APP_MISC_3_EMIF_SDRAM (0x1000) -#define U300_SYSCON_PMC2R_APP_MISC_3_MMC (0x2000) -#define U300_SYSCON_PMC2R_APP_MISC_3_CDI2 (0x3000) -#define U300_SYSCON_PMC2R_APP_MISC_4_MASK (0xC000) -#define U300_SYSCON_PMC2R_APP_MISC_4_APP_GPIO (0x0000) -#define U300_SYSCON_PMC2R_APP_MISC_4_EMIF_SDRAM (0x4000) -#define U300_SYSCON_PMC2R_APP_MISC_4_MMC (0x8000) -#define U300_SYSCON_PMC2R_APP_MISC_4_ACC_GPIO (0xC000) -/* TODO: More SYSCON registers missing */ -#define U300_SYSCON_PMC3R (0x10c) -#define U300_SYSCON_PMC3R_APP_MISC_11_MASK (0xc000) -#define U300_SYSCON_PMC3R_APP_MISC_11_SPI (0x4000) -#define U300_SYSCON_PMC3R_APP_MISC_10_MASK (0x3000) -#define U300_SYSCON_PMC3R_APP_MISC_10_SPI (0x1000) -/* TODO: Missing other configs */ -#define U300_SYSCON_PMC4R (0x168) -#define U300_SYSCON_PMC4R_APP_MISC_12_MASK (0x0003) -#define U300_SYSCON_PMC4R_APP_MISC_12_APP_GPIO (0x0000) -#define U300_SYSCON_PMC4R_APP_MISC_13_MASK (0x000C) -#define U300_SYSCON_PMC4R_APP_MISC_13_CDI (0x0000) -#define U300_SYSCON_PMC4R_APP_MISC_13_SMIA (0x0004) -#define U300_SYSCON_PMC4R_APP_MISC_13_SMIA2 (0x0008) -#define U300_SYSCON_PMC4R_APP_MISC_13_APP_GPIO (0x000C) -#define U300_SYSCON_PMC4R_APP_MISC_14_MASK (0x0030) -#define U300_SYSCON_PMC4R_APP_MISC_14_CDI (0x0000) -#define U300_SYSCON_PMC4R_APP_MISC_14_SMIA (0x0010) -#define U300_SYSCON_PMC4R_APP_MISC_14_CDI2 (0x0020) -#define U300_SYSCON_PMC4R_APP_MISC_14_APP_GPIO (0x0030) -#define U300_SYSCON_PMC4R_APP_MISC_16_MASK (0x0300) -#define U300_SYSCON_PMC4R_APP_MISC_16_APP_GPIO_13 (0x0000) -#define U300_SYSCON_PMC4R_APP_MISC_16_APP_UART1_CTS (0x0100) -#define U300_SYSCON_PMC4R_APP_MISC_16_EMIF_1_STATIC_CS5_N (0x0200) /* SYS_0_CLK_CONTROL first clock control 16bit (R/W) */ #define U300_SYSCON_S0CCR (0x120) #define U300_SYSCON_S0CCR_FIELD_MASK (0x43FF) diff --git a/arch/arm/mach-u300/mmc.c b/arch/arm/mach-u300/mmc.c index 677ccef..d5e4a98 100644 --- a/arch/arm/mach-u300/mmc.c +++ b/arch/arm/mach-u300/mmc.c @@ -21,7 +21,6 @@ #include <mach/dma_channels.h> #include "mmc.h" -#include "padmux.h" static struct mmci_platform_data mmc0_plat_data = { /* @@ -45,24 +44,9 @@ static struct mmci_platform_data mmc0_plat_data = { int __devinit mmc_init(struct amba_device *adev) { struct device *mmcsd_device = &adev->dev; - struct pmx *pmx; int ret = 0; mmcsd_device->platform_data = &mmc0_plat_data; - /* - * Setup padmuxing for MMC. Since this must always be - * compiled into the kernel, pmx is never released. - */ - pmx = pmx_get(mmcsd_device, U300_APP_PMX_MMC_SETTING); - - if (IS_ERR(pmx)) - pr_warning("Could not get padmux handle\n"); - else { - ret = pmx_activate(mmcsd_device, pmx); - if (IS_ERR_VALUE(ret)) - pr_warning("Could not activate padmuxing\n"); - } - return ret; } diff --git a/arch/arm/mach-u300/padmux.c b/arch/arm/mach-u300/padmux.c deleted file mode 100644 index 4c93c6c..0000000 --- a/arch/arm/mach-u300/padmux.c +++ /dev/null @@ -1,367 +0,0 @@ -/* - * - * arch/arm/mach-u300/padmux.c - * - * - * Copyright (C) 2009 ST-Ericsson AB - * License terms: GNU General Public License (GPL) version 2 - * U300 PADMUX functions - * Author: Martin Persson <martin.persson(a)stericsson.com> - */ - -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/device.h> -#include <linux/err.h> -#include <linux/errno.h> -#include <linux/io.h> -#include <linux/mutex.h> -#include <linux/string.h> -#include <linux/bug.h> -#include <linux/debugfs.h> -#include <linux/seq_file.h> -#include <mach/u300-regs.h> -#include <mach/syscon.h> -#include "padmux.h" - -static DEFINE_MUTEX(pmx_mutex); - -const u32 pmx_registers[] = { - (U300_SYSCON_VBASE + U300_SYSCON_PMC1LR), - (U300_SYSCON_VBASE + U300_SYSCON_PMC1HR), - (U300_SYSCON_VBASE + U300_SYSCON_PMC2R), - (U300_SYSCON_VBASE + U300_SYSCON_PMC3R), - (U300_SYSCON_VBASE + U300_SYSCON_PMC4R) -}; - -/* High level functionality */ - -/* Lazy dog: - * onmask = { - * {"PMC1LR" mask, "PMC1LR" value}, - * {"PMC1HR" mask, "PMC1HR" value}, - * {"PMC2R" mask, "PMC2R" value}, - * {"PMC3R" mask, "PMC3R" value}, - * {"PMC4R" mask, "PMC4R" value} - * } - */ -static struct pmx mmc_setting = { - .setting = U300_APP_PMX_MMC_SETTING, - .default_on = false, - .activated = false, - .name = "MMC", - .onmask = { - {U300_SYSCON_PMC1LR_MMCSD_MASK, - U300_SYSCON_PMC1LR_MMCSD_MMCSD}, - {0, 0}, - {0, 0}, - {0, 0}, - {U300_SYSCON_PMC4R_APP_MISC_12_MASK, - U300_SYSCON_PMC4R_APP_MISC_12_APP_GPIO} - }, -}; - -static struct pmx spi_setting = { - .setting = U300_APP_PMX_SPI_SETTING, - .default_on = false, - .activated = false, - .name = "SPI", - .onmask = {{0, 0}, - {U300_SYSCON_PMC1HR_APP_SPI_2_MASK | - U300_SYSCON_PMC1HR_APP_SPI_CS_1_MASK | - U300_SYSCON_PMC1HR_APP_SPI_CS_2_MASK, - U300_SYSCON_PMC1HR_APP_SPI_2_SPI | - U300_SYSCON_PMC1HR_APP_SPI_CS_1_SPI | - U300_SYSCON_PMC1HR_APP_SPI_CS_2_SPI}, - {0, 0}, - {0, 0}, - {0, 0} - }, -}; - -/* Available padmux settings */ -static struct pmx *pmx_settings[] = { - &mmc_setting, - &spi_setting, -}; - -static void update_registers(struct pmx *pmx, bool activate) -{ - u16 regval, val, mask; - int i; - - for (i = 0; i < ARRAY_SIZE(pmx_registers); i++) { - if (activate) - val = pmx->onmask[i].val; - else - val = 0; - - mask = pmx->onmask[i].mask; - if (mask != 0) { - regval = readw(pmx_registers[i]); - regval &= ~mask; - regval |= val; - writew(regval, pmx_registers[i]); - } - } -} - -struct pmx *pmx_get(struct device *dev, enum pmx_settings setting) -{ - int i; - struct pmx *pmx = ERR_PTR(-ENOENT); - - if (dev == NULL) - return ERR_PTR(-EINVAL); - - mutex_lock(&pmx_mutex); - for (i = 0; i < ARRAY_SIZE(pmx_settings); i++) { - - if (setting == pmx_settings[i]->setting) { - - if (pmx_settings[i]->dev != NULL) { - WARN(1, "padmux: required setting " - "in use by another consumer\n"); - } else { - pmx = pmx_settings[i]; - pmx->dev = dev; - dev_dbg(dev, "padmux: setting nr %d is now " - "bound to %s and ready to use\n", - setting, dev_name(dev)); - break; - } - } - } - mutex_unlock(&pmx_mutex); - - return pmx; -} -EXPORT_SYMBOL(pmx_get); - -int pmx_put(struct device *dev, struct pmx *pmx) -{ - int i; - int ret = -ENOENT; - - if (pmx == NULL || dev == NULL) - return -EINVAL; - - mutex_lock(&pmx_mutex); - for (i = 0; i < ARRAY_SIZE(pmx_settings); i++) { - - if (pmx->setting == pmx_settings[i]->setting) { - - if (dev != pmx->dev) { - WARN(1, "padmux: cannot release handle as " - "it is bound to another consumer\n"); - ret = -EINVAL; - break; - } else { - pmx_settings[i]->dev = NULL; - ret = 0; - break; - } - } - } - mutex_unlock(&pmx_mutex); - - return ret; -} -EXPORT_SYMBOL(pmx_put); - -int pmx_activate(struct device *dev, struct pmx *pmx) -{ - int i, j, ret; - ret = 0; - - if (pmx == NULL || dev == NULL) - return -EINVAL; - - mutex_lock(&pmx_mutex); - - /* Make sure the required bits are not used */ - for (i = 0; i < ARRAY_SIZE(pmx_settings); i++) { - - if (pmx_settings[i]->dev == NULL || pmx_settings[i] == pmx) - continue; - - for (j = 0; j < ARRAY_SIZE(pmx_registers); j++) { - - if (pmx_settings[i]->onmask[j].mask & pmx-> - onmask[j].mask) { - /* More than one entry on the same bits */ - WARN(1, "padmux: cannot activate " - "setting. Bit conflict with " - "an active setting\n"); - - ret = -EUSERS; - goto exit; - } - } - } - update_registers(pmx, true); - pmx->activated = true; - dev_dbg(dev, "padmux: setting nr %d is activated\n", - pmx->setting); - -exit: - mutex_unlock(&pmx_mutex); - return ret; -} -EXPORT_SYMBOL(pmx_activate); - -int pmx_deactivate(struct device *dev, struct pmx *pmx) -{ - int i; - int ret = -ENOENT; - - if (pmx == NULL || dev == NULL) - return -EINVAL; - - mutex_lock(&pmx_mutex); - for (i = 0; i < ARRAY_SIZE(pmx_settings); i++) { - - if (pmx_settings[i]->dev == NULL) - continue; - - if (pmx->setting == pmx_settings[i]->setting) { - - if (dev != pmx->dev) { - WARN(1, "padmux: cannot deactivate " - "pmx setting as it was activated " - "by another consumer\n"); - - ret = -EBUSY; - continue; - } else { - update_registers(pmx, false); - pmx_settings[i]->dev = NULL; - pmx->activated = false; - ret = 0; - dev_dbg(dev, "padmux: setting nr %d is deactivated", - pmx->setting); - break; - } - } - } - mutex_unlock(&pmx_mutex); - - return ret; -} -EXPORT_SYMBOL(pmx_deactivate); - -/* - * For internal use only. If it is to be exported, - * it should be reentrant. Notice that pmx_activate - * (i.e. runtime settings) always override default settings. - */ -static int pmx_set_default(void) -{ - /* Used to identify several entries on the same bits */ - u16 modbits[ARRAY_SIZE(pmx_registers)]; - - int i, j; - - memset(modbits, 0, ARRAY_SIZE(pmx_registers) * sizeof(u16)); - - for (i = 0; i < ARRAY_SIZE(pmx_settings); i++) { - - if (!pmx_settings[i]->default_on) - continue; - - for (j = 0; j < ARRAY_SIZE(pmx_registers); j++) { - - /* Make sure there is only one entry on the same bits */ - if (modbits[j] & pmx_settings[i]->onmask[j].mask) { - BUG(); - return -EUSERS; - } - modbits[j] |= pmx_settings[i]->onmask[j].mask; - } - update_registers(pmx_settings[i], true); - } - return 0; -} - -#if (defined(CONFIG_DEBUG_FS) && defined(CONFIG_U300_DEBUG)) -static int pmx_show(struct seq_file *s, void *data) -{ - int i; - seq_printf(s, "-------------------------------------------------\n"); - seq_printf(s, "SETTING BOUND TO DEVICE STATE\n"); - seq_printf(s, "-------------------------------------------------\n"); - mutex_lock(&pmx_mutex); - for (i = 0; i < ARRAY_SIZE(pmx_settings); i++) { - /* Format pmx and device name nicely */ - char cdp[33]; - int chars; - - chars = snprintf(&cdp[0], 17, "%s", pmx_settings[i]->name); - while (chars < 16) { - cdp[chars] = ' '; - chars++; - } - chars = snprintf(&cdp[16], 17, "%s", pmx_settings[i]->dev ? - dev_name(pmx_settings[i]->dev) : "N/A"); - while (chars < 16) { - cdp[chars+16] = ' '; - chars++; - } - cdp[32] = '\0'; - - seq_printf(s, - "%s\t%s\n", - &cdp[0], - pmx_settings[i]->activated ? - "ACTIVATED" : "DEACTIVATED" - ); - - } - mutex_unlock(&pmx_mutex); - return 0; -} - -static int pmx_open(struct inode *inode, struct file *file) -{ - return single_open(file, pmx_show, NULL); -} - -static const struct file_operations pmx_operations = { - .owner = THIS_MODULE, - .open = pmx_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; - -static int __init init_pmx_read_debugfs(void) -{ - /* Expose a simple debugfs interface to view pmx settings */ - (void) debugfs_create_file("padmux", S_IFREG | S_IRUGO, - NULL, NULL, - &pmx_operations); - return 0; -} - -/* - * This needs to come in after the core_initcall(), - * because debugfs is not available until - * the subsystems come up. - */ -module_init(init_pmx_read_debugfs); -#endif - -static int __init pmx_init(void) -{ - int ret; - - ret = pmx_set_default(); - - if (IS_ERR_VALUE(ret)) - pr_crit("padmux: default settings could not be set\n"); - - return 0; -} - -/* Should be initialized before consumers */ -core_initcall(pmx_init); diff --git a/arch/arm/mach-u300/padmux.h b/arch/arm/mach-u300/padmux.h deleted file mode 100644 index 6e8b860..0000000 --- a/arch/arm/mach-u300/padmux.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * - * arch/arm/mach-u300/padmux.h - * - * - * Copyright (C) 2009 ST-Ericsson AB - * License terms: GNU General Public License (GPL) version 2 - * U300 PADMUX API - * Author: Martin Persson <martin.persson(a)stericsson.com> - */ - -#ifndef __MACH_U300_PADMUX_H -#define __MACH_U300_PADMUX_H - -enum pmx_settings { - U300_APP_PMX_MMC_SETTING, - U300_APP_PMX_SPI_SETTING -}; - -struct pmx_onmask { - u16 mask; /* Mask bits */ - u16 val; /* Value when active */ -}; - -struct pmx { - struct device *dev; - enum pmx_settings setting; - char *name; - bool activated; - bool default_on; - struct pmx_onmask onmask[]; -}; - -struct pmx *pmx_get(struct device *dev, enum pmx_settings setting); -int pmx_put(struct device *dev, struct pmx *pmx); -int pmx_activate(struct device *dev, struct pmx *pmx); -int pmx_deactivate(struct device *dev, struct pmx *pmx); - -#endif diff --git a/arch/arm/mach-u300/spi.c b/arch/arm/mach-u300/spi.c index 7b597e2..a1affac 100644 --- a/arch/arm/mach-u300/spi.c +++ b/arch/arm/mach-u300/spi.c @@ -14,8 +14,6 @@ #include <mach/coh901318.h> #include <mach/dma_channels.h> -#include "padmux.h" - /* * The following is for the actual devices on the SSP/SPI bus */ @@ -95,25 +93,7 @@ static struct pl022_ssp_controller ssp_platform_data = { void __init u300_spi_init(struct amba_device *adev) { - struct pmx *pmx; - adev->dev.platform_data = &ssp_platform_data; - /* - * Setup padmuxing for SPI. Since this must always be - * compiled into the kernel, pmx is never released. - */ - pmx = pmx_get(&adev->dev, U300_APP_PMX_SPI_SETTING); - - if (IS_ERR(pmx)) - dev_warn(&adev->dev, "Could not get padmux handle\n"); - else { - int ret; - - ret = pmx_activate(&adev->dev, pmx); - if (IS_ERR_VALUE(ret)) - dev_warn(&adev->dev, "Could not activate padmuxing\n"); - } - } void __init u300_spi_register_board_devices(void) diff --git a/drivers/pinctrl/pinmux-u300.c b/drivers/pinctrl/pinmux-u300.c index c0cefb6..524f7c3 100644 --- a/drivers/pinctrl/pinmux-u300.c +++ b/drivers/pinctrl/pinmux-u300.c @@ -117,7 +117,7 @@ const struct pinctrl_pin_desc __refdata u300_pads[] = { */ struct u300_pmx { struct device *dev; - struct pinmux_dev *pmx; + struct pinctrl_dev *pctl; u32 phybase; u32 physize; void __iomem *virtbase; @@ -254,36 +254,36 @@ static void u300_pmx_endisable(struct u300_pmx *upmx, unsigned selector, } } -static int u300_pmx_enable(struct pinmux_dev *pmxdev, unsigned selector) +static int u300_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector) { struct u300_pmx *upmx; if (selector >= ARRAY_SIZE(u300_pmx_funcs)) return -EINVAL; - upmx = pmxdev_get_drvdata(pmxdev); + upmx = pctldev_get_drvdata(pctldev); u300_pmx_endisable(upmx, selector, true); return 0; } -static void u300_pmx_disable(struct pinmux_dev *pmxdev, unsigned selector) +static void u300_pmx_disable(struct pinctrl_dev *pctldev, unsigned selector) { struct u300_pmx *upmx; if (selector >= ARRAY_SIZE(u300_pmx_funcs)) return; - upmx = pmxdev_get_drvdata(pmxdev); + upmx = pctldev_get_drvdata(pctldev); u300_pmx_endisable(upmx, selector, false); } -static int u300_pmx_list(struct pinmux_dev *pmxdev, unsigned selector) +static int u300_pmx_list(struct pinctrl_dev *pctldev, unsigned selector) { if (selector >= ARRAY_SIZE(u300_pmx_funcs)) return -EINVAL; return 0; } -static const char *u300_pmx_get_fname(struct pinmux_dev *pmxdev, +static const char *u300_pmx_get_fname(struct pinctrl_dev *pctldev, unsigned selector) { if (selector >= ARRAY_SIZE(u300_pmx_funcs)) @@ -291,7 +291,7 @@ static const char *u300_pmx_get_fname(struct pinmux_dev *pmxdev, return u300_pmx_funcs[selector].name; } -static int u300_pmx_get_pins(struct pinmux_dev *pmxdev, unsigned selector, +static int u300_pmx_get_pins(struct pinctrl_dev *pctldev, unsigned selector, unsigned ** const pins, unsigned * const num_pins) { if (selector >= ARRAY_SIZE(u300_pmx_funcs)) @@ -301,7 +301,7 @@ static int u300_pmx_get_pins(struct pinmux_dev *pmxdev, unsigned selector, return 0; } -static void u300_dbg_show(struct pinmux_dev *pmxdev, struct seq_file *s, +static void u300_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, unsigned offset) { seq_printf(s, " " DRIVER_NAME); @@ -316,7 +316,7 @@ static struct pinmux_ops u300_pmx_ops = { .dbg_show = u300_dbg_show, }; -static struct pinmux_desc u300_pmx_desc = { +static struct pinctrl_desc u300_pmx_desc = { .name = DRIVER_NAME, .pins = u300_pads, .npins = ARRAY_SIZE(u300_pads), @@ -358,11 +358,10 @@ static int __init u300_pmx_probe(struct platform_device *pdev) goto out_no_remap; } - /* Now register the pin controller and all pins it handles */ upmx->pctl = pinctrl_register(&u300_pmx_desc, &pdev->dev, upmx); if (IS_ERR(upmx->pctl)) { dev_err(&pdev->dev, "could not register U300 pinmux driver\n"); - ret = PTR_ERR(upmx->pmx); + ret = PTR_ERR(upmx->pctl); goto out_no_pmx; } platform_set_drvdata(pdev, upmx); @@ -387,7 +386,7 @@ static int __exit u300_pmx_remove(struct platform_device *pdev) struct u300_pmx *upmx = platform_get_drvdata(pdev); if (upmx) { - pinmux_unregister(upmx->pmx); + pinctrl_unregister(upmx->pctl); iounmap(upmx->virtbase); release_mem_region(upmx->phybase, upmx->physize); platform_set_drvdata(pdev, NULL); -- 1.7.3.2

13 years, 9 months

[PATCH 3/4 v4] amba: request muxing for PrimeCell devices

by Linus Walleij

From: Linus Walleij <linus.walleij(a)linaro.org> This makes the AMBA PrimeCell drivers request padmuxing for themselves in the same manner as clocks and voltage is currently requested. Signed-off-by: Linus Walleij <linus.walleij(a)linaro.org> --- drivers/amba/bus.c | 49 ++++++++++++++++++++++++++++++++++++++++++++- include/linux/amba/bus.h | 2 + 2 files changed, 49 insertions(+), 2 deletions(-) diff --git a/drivers/amba/bus.c b/drivers/amba/bus.c index d74926e..bd0516c 100644 --- a/drivers/amba/bus.c +++ b/drivers/amba/bus.c @@ -474,6 +474,40 @@ static void amba_put_disable_vcore(struct amba_device *pcdev) } } +static int amba_get_enable_pinmux(struct amba_device *pcdev) +{ + struct pinmux *pmx = pinmux_get(&pcdev->dev, NULL); + int ret; + + pcdev->pmx = pmx; + + if (IS_ERR(pmx)) { + /* It is OK not to supply a pinmux regulator */ + if (PTR_ERR(pmx) == -ENODEV) + return 0; + return PTR_ERR(pmx); + } + + ret = pinmux_enable(pmx); + if (ret) { + pinmux_put(pmx); + pcdev->pmx = ERR_PTR(-ENODEV); + } + + return ret; +} + +static void amba_put_disable_pinmux(struct amba_device *pcdev) +{ + struct pinmux *pmx = pcdev->pmx; + + if (!IS_ERR(pmx)) { + pinmux_disable(pmx); + pinmux_put(pmx); + } +} + + /* * These are the device model conversion veneers; they convert the * device model structures to our more specific structures. @@ -486,13 +520,22 @@ static int amba_probe(struct device *dev) int ret; do { - ret = amba_get_enable_vcore(pcdev); + ret = amba_get_enable_pinmux(pcdev); if (ret) break; + ret = amba_get_enable_vcore(pcdev); + if (ret) { + amba_put_disable_pinmux(pcdev); + break; + } + ret = amba_get_enable_pclk(pcdev); - if (ret) + if (ret) { + amba_put_disable_pinmux(pcdev); + amba_put_disable_vcore(pcdev); break; + } ret = pcdrv->probe(pcdev, id); if (ret == 0) @@ -500,6 +543,7 @@ static int amba_probe(struct device *dev) amba_put_disable_pclk(pcdev); amba_put_disable_vcore(pcdev); + amba_put_disable_pinmux(pcdev); } while (0); return ret; @@ -513,6 +557,7 @@ static int amba_remove(struct device *dev) amba_put_disable_pclk(pcdev); amba_put_disable_vcore(pcdev); + amba_put_disable_pinmux(pcdev); return ret; } diff --git a/include/linux/amba/bus.h b/include/linux/amba/bus.h index fcbbe71..35f1193 100644 --- a/include/linux/amba/bus.h +++ b/include/linux/amba/bus.h @@ -19,6 +19,7 @@ #include <linux/err.h> #include <linux/resource.h> #include <linux/regulator/consumer.h> +#include <linux/pinctrl/pinmux.h> #define AMBA_NR_IRQS 2 #define AMBA_CID 0xb105f00d @@ -30,6 +31,7 @@ struct amba_device { struct resource res; struct clk *pclk; struct regulator *vcore; + struct pinmux *pmx; u64 dma_mask; unsigned int periphid; unsigned int irq[AMBA_NR_IRQS]; -- 1.7.3.2

13 years, 9 months

Linux kernel review tags (Re: [PATCH 0/3] Fix Thumb-2 undef handling for mixed-arch kernels)

by Dave Martin

On Tue, Aug 16, 2011 at 05:43:08PM +0100, Tixy wrote: > On Tue, 2011-08-16 at 17:06 +0100, Dave Martin wrote: > > On Tue, Aug 16, 2011 at 3:58 PM, Tixy <tixy(a)yxit.co.uk> wrote: [...] > I've been re-reading Documentation/SubmittingPatches to try and work out > when it's appropriate to use Acked-by, but it seems a bit woolly - > mostly for maintainers? Actually I asked the question semi-automatically since you are CC'd on this series -- because I was originally touching kprobes code, which you have in-depth understanding of. But now the series doesn't touch that code any more, reviewed-by makes more sense. Here's my own interpretation of the tags, based on how they appear to be used (obviously, this doesn't override SubmittingPatches; it's my additional interpretation) I could of course be wrong in some aspects. Any comments on this from the more experienced kernel developers out there? Signed-off-by = I take full responsibility for this patch, and can maintain it in the author's absence if required. In practice, this implies Acked-by. Acked-by = This patch is definitely right, or I fully agree with the patch and trust the author's judgement ("I will share responsibility for the correctness and appropriateness of this patch"). This implies Reviewed-by. Normally an ack shouldn't get added unless the acker is confident that the patch is adequately tested (where the level of testing deemed adequate depends on the complexity of the patch) Again, this may rely on judgement of the comptence of the author and the other reviewers. Reviewed-by = This patch looks correct and appropriate and I judge it ok to merge, but I assume the author knows what they're doing, and I don't necessarily take responsibility for the change. Tested-by = I have built and tested the patch, and saw reasonable evidence that it achieves the intended result and has no harmful effects. I make no comment about contents of the patch, and I don't necessarily take responsibility for the change. In all cases, the tag may influence upstreams' judgement about whether to merge the patch: adding a tag implies understanding of this, and takes responsibility for the effect this has (wise or unwise) on the decision to merge. NA(C)K = Informal indication that this patch is definitely wrong (not listed in SubmittingPatches, because if someone is that convinced the patch is wrong, it isn't normally going to get merged without rework... or the NACKer is themselves known by upstream to be reliably untrustworthy, biased, or wrong. In that case, the upstream maintainter effectively overrides the NACKer. An Ack is normally not useful unless it comes from someone who is themselves known to and trusted by the maintainer of the tree where the patch will get merged, or unless it comes from the original author or a maintainer of the code that was modified (since they are normally the best people to judge). Acked-by: randomnewbie(a)hotmail.com isn't likely to carry much weight. In fact, including blatantly frivolous or fraudulent acks from people in your upstream patch submissions may harm their chance of merging (and your reputation). So for now, I don't often ack patches -- I generally do so when someone touches code I modified/added, to indicate that I understand their change well enough, and am confident enough that it is correct, that I would be happy to share some responsiibility for their change and any resulting impacts on the maintenance of the code I added. In areas where I know I have and am known to have a good understanding (such as Thumb-2 related issues), I may ack patches touching code that is nothing to do with me, because in such cases the Ack has a useful meaning for the upstream maintainer. Cheers ---Dave

13 years, 9 months

Re: 3D Demo at ARM

by Zach Pfeffer

Ramin, Thanks for the email. I've added linaro-dev to my response. The demo consisted of two identical PandaBoards with identical SD cards running the 3D benchmark of 0xbench using software 3D to amplify compiler and kernel improvements. 0xbench is a benchmarking program we ship with our Android images from 0xlab. Each build ran the same Android userspace, 2.3.4, but one was using the 2.6.36 Linux kernel and GCC 4.4 from the stock AOSP distribution and one was using an upgraded Linaro 3.0 Linux kernel with Linaro GCC 4.5. We ran the board in 640x480 mode so that we wouldn't be memory bound. Users can use and recreate the builds easily. To program the builds visit 2.6.36 https://android-build.linaro.org/builds/~linaro-android/panda-11.05-release/ and 3.0 https://android-build.linaro.org/builds/~linaro-android/panda-11.07-release/ To recreate the builds from scratch visit: https://wiki.linaro.org/Platform/Android/GetSource https://wiki.linaro.org/Platform/Android/BuildSource Here's a video of demo running: https://plus.google.com/104422661029399872488/posts/Rjmo5HCHQxZ (this is running in 720P mode not 640x480) I'm happy to help you reproduce the demos. Feel free to drop by #linaro-android on freenode. -Zach On 10 August 2011 06:24, Ramin Zaghi <Ramin.Zaghi(a)arm.com> wrote: > Hi Zach > > > > I didn’t get a chance to see you yesterday so got your card from the table. > I was one of the first > employees of our Multimedia Division who was from a game-dev background. > > Your demos were interesting so I was wondering if I could ask for a bit of > explanation, and what they were? > > I also like to know what engine they were running or was it a custom bit of > code that you wrote? > > > > > > Thanks > > > > Ramin > > > > > > ------------------------------ > > Ramin Zaghi > > Software Engineer > > Processor Division / PDSW > > ------------------------------ > > ARM Ltd. > > 110 Fulbourn Road > > Cambridge > > CB1 9NJ, UK > > ------------------------------ > > Tel: +44 1223 406347 > > [Extn 22347] > > ------------------------------ > > > > > > > > -- IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended > recipient, please notify the sender immediately and do not disclose the > contents to any other person, use it for any purpose, or store or copy the > information in any medium. Thank you. >

13 years, 9 months

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