Hi
here is the status for Graphics WG for wk20.
https://wiki.linaro.org/WorkingGroups/Middleware/Graphics/Status/2011-05-18
Highlights:
- Working on 11.11 blueprint specs
- Finishing off tasks for 11.05:
# Cairo maintainer has committed the patches provided by Alexandros upstream
# Compositor work mostly done, just waiting to do final validation
(based on chromium build - pending from Tom Gall)
# GLEW patches to be sent for review
# Compiz (nux) work underway
# Skia: feedback from the maintainer being reviewed,
# Benchmarking blueprint also progressing, but needs some clarification
(actions taken by Jesse, Alexandros)
BR,
--
Ilias Biris,
Aallonkohina 2D 19, 02320 Espoo, Finland
Tel: +358 50 4839608 (mobile)
Email: ilias dot biris at linaro dot org
Skype: ilias_biris
Enclosed you'll find a link to the agenda, notes and actions from the
Linaro Developer Platforms Weekly Status meeting held on May 18th
in #linaro-meeting on irc.freenode.net at 15:00 UTC.
https://wiki.linaro.org/Platform/DevPlatform/Meetings/2011-05-18
New Actions:
* None
Regards,
Tom
Developer Platforms Team
"We want great men who, when fortune frowns will not be discouraged."
- Colonel Henry Knox
w) tom.gall att linaro.org
w) tom_gall att vnet.ibm.com
h) tom_gall att mac.com
IRC) Dr_Who, tgall_foo
We currently use a feature branch / merge request / merge / test /
push approach in gcc-linaro. This works fine for a reasonable cost
but can mean that patches sit unreviewed and unmerged for up to a
month. Ramana, Andrew, and I had a talk about this earlier in the
week and I've written up the ideas here:
https://wiki.linaro.org/MichaelHope/Sandbox/ReviewThoughts
We're a bit unique as gcc-linaro started from a mature base, running
the testsuite takes days, and the product is so big that bzr takes a
long time to work on it.
If you have experience in running a master branch or ideas on
continious integration please have a read.
-- Michael
SROM config code is made common for S5P series of boards.
smdkc100.c now refers to s5p-common/sromc.c for SROM related
subroutines.
Signed-off-by: Chander Kashyap <chander.kashyap(a)linaro.org>
---
arch/arm/cpu/armv7/s5p-common/Makefile | 3 +-
arch/arm/cpu/armv7/s5p-common/sromc.c | 49 ++++++++++++++++++++++++++
arch/arm/cpu/armv7/s5pc1xx/Makefile | 1 -
arch/arm/cpu/armv7/s5pc1xx/sromc.c | 49 --------------------------
arch/arm/include/asm/arch-s5pc1xx/smc.h | 53 -----------------------------
arch/arm/include/asm/arch-s5pc1xx/sromc.h | 53 +++++++++++++++++++++++++++++
board/samsung/smdkc100/smdkc100.c | 4 +-
7 files changed, 106 insertions(+), 106 deletions(-)
create mode 100644 arch/arm/cpu/armv7/s5p-common/sromc.c
delete mode 100644 arch/arm/cpu/armv7/s5pc1xx/sromc.c
delete mode 100644 arch/arm/include/asm/arch-s5pc1xx/smc.h
create mode 100644 arch/arm/include/asm/arch-s5pc1xx/sromc.h
diff --git a/arch/arm/cpu/armv7/s5p-common/Makefile b/arch/arm/cpu/armv7/s5p-common/Makefile
index ce0a41e..1705399 100644
--- a/arch/arm/cpu/armv7/s5p-common/Makefile
+++ b/arch/arm/cpu/armv7/s5p-common/Makefile
@@ -27,7 +27,8 @@ LIB = $(obj)libs5p-common.o
COBJS-y += cpu_info.o
COBJS-y += timer.o
-COBJS-$(CONFIG_PWM) += pwm.o
+COBJS-y += sromc.o
+COBJS-$(CONFIG_PWM) += pwm.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS))
diff --git a/arch/arm/cpu/armv7/s5p-common/sromc.c b/arch/arm/cpu/armv7/s5p-common/sromc.c
new file mode 100644
index 0000000..091e8d1
--- /dev/null
+++ b/arch/arm/cpu/armv7/s5p-common/sromc.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2010 Samsung Electronics
+ * Naveen Krishna Ch <ch.naveen(a)samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sromc.h>
+
+/*
+ * s5p_config_sromc() - select the proper SROMC Bank and configure the
+ * band width control and bank control registers
+ * srom_bank - SROM
+ * srom_bw_conf - SMC Band witdh reg configuration value
+ * srom_bc_conf - SMC Bank Control reg configuration value
+ */
+void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf)
+{
+ u32 tmp;
+ struct s5p_sromc *srom =
+ (struct s5p_sromc *)samsung_get_base_sromc();
+
+ /* Configure SMC_BW register to handle proper SROMC bank */
+ tmp = srom->bw;
+ tmp &= ~(0xF << (srom_bank * 4));
+ tmp |= srom_bw_conf;
+ srom->bw = tmp;
+
+ /* Configure SMC_BC register */
+ srom->bc[srom_bank] = srom_bc_conf;
+}
diff --git a/arch/arm/cpu/armv7/s5pc1xx/Makefile b/arch/arm/cpu/armv7/s5pc1xx/Makefile
index b182bf5..d66314e 100644
--- a/arch/arm/cpu/armv7/s5pc1xx/Makefile
+++ b/arch/arm/cpu/armv7/s5pc1xx/Makefile
@@ -32,7 +32,6 @@ SOBJS = cache.o
SOBJS += reset.o
COBJS += clock.o
-COBJS += sromc.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/arch/arm/cpu/armv7/s5pc1xx/sromc.c b/arch/arm/cpu/armv7/s5pc1xx/sromc.c
deleted file mode 100644
index 044d122..0000000
--- a/arch/arm/cpu/armv7/s5pc1xx/sromc.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * Copyright (C) 2010 Samsung Electronics
- * Naveen Krishna Ch <ch.naveen(a)samsung.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/smc.h>
-
-/*
- * s5pc1xx_config_sromc() - select the proper SROMC Bank and configure the
- * band width control and bank control registers
- * srom_bank - SROM Bank 0 to 5
- * smc_bw_conf - SMC Band witdh reg configuration value
- * smc_bc_conf - SMC Bank Control reg configuration value
- */
-void s5pc1xx_config_sromc(u32 srom_bank, u32 smc_bw_conf, u32 smc_bc_conf)
-{
- u32 tmp;
- struct s5pc1xx_smc *srom =
- (struct s5pc1xx_smc *)samsung_get_base_sromc();
-
- /* Configure SMC_BW register to handle proper SROMC bank */
- tmp = srom->bw;
- tmp &= ~(0xF << (srom_bank * 4));
- tmp |= smc_bw_conf;
- srom->bw = tmp;
-
- /* Configure SMC_BC register */
- srom->bc[srom_bank] = smc_bc_conf;
-}
diff --git a/arch/arm/include/asm/arch-s5pc1xx/smc.h b/arch/arm/include/asm/arch-s5pc1xx/smc.h
deleted file mode 100644
index 88f4ffe..0000000
--- a/arch/arm/include/asm/arch-s5pc1xx/smc.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * (C) Copyright 2010 Samsung Electronics
- * Naveen Krishna Ch <ch.naveen(a)samsung.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * Note: This file contains the register description for Memory subsystem
- * (SROM, NAND Flash, OneNand, DDR, OneDRAM) on S5PC1XX.
- *
- * Only SROMC is defined as of now
- */
-
-#ifndef __ASM_ARCH_SMC_H_
-#define __ASM_ARCH_SMC_H_
-
-#define SMC_DATA16_WIDTH(x) (1<<((x*4)+0))
-#define SMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/
- /* 1-> Byte base address*/
-#define SMC_WAIT_ENABLE(x) (1<<((x*4)+2))
-#define SMC_BYTE_ENABLE(x) (1<<((x*4)+3))
-
-#define SMC_BC_TACS(x) (x << 28) /* 0clk address set-up */
-#define SMC_BC_TCOS(x) (x << 24) /* 4clk chip selection set-up */
-#define SMC_BC_TACC(x) (x << 16) /* 14clk access cycle */
-#define SMC_BC_TCOH(x) (x << 12) /* 1clk chip selection hold */
-#define SMC_BC_TAH(x) (x << 8) /* 4clk address holding time */
-#define SMC_BC_TACP(x) (x << 4) /* 6clk page mode access cycle */
-#define SMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */
-
-#ifndef __ASSEMBLY__
-struct s5pc1xx_smc {
- unsigned int bw;
- unsigned int bc[6];
-};
-#endif /* __ASSEMBLY__ */
-
-/* Configure the Band Width and Bank Control Regs for required SROMC Bank */
-void s5pc1xx_config_sromc(u32 srom_bank, u32 smc_bw_conf, u32 smc_bc_conf);
-
-#endif /* __ASM_ARCH_SMC_H_ */
diff --git a/arch/arm/include/asm/arch-s5pc1xx/sromc.h b/arch/arm/include/asm/arch-s5pc1xx/sromc.h
new file mode 100644
index 0000000..3800a8d
--- /dev/null
+++ b/arch/arm/include/asm/arch-s5pc1xx/sromc.h
@@ -0,0 +1,53 @@
+/*
+ * (C) Copyright 2010 Samsung Electronics
+ * Naveen Krishna Ch <ch.naveen(a)samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Note: This file contains the register description for Memory subsystem
+ * (SROM, NAND Flash, OneNand, DDR, OneDRAM) on S5PC1XX.
+ *
+ * Only SROMC is defined as of now
+ */
+
+#ifndef __ASM_ARCH_SROMC_H_
+#define __ASM_ARCH_SROMC_H_
+
+#define SMC_DATA16_WIDTH(x) (1<<((x*4)+0))
+#define SMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/
+ /* 1-> Byte base address*/
+#define SMC_WAIT_ENABLE(x) (1<<((x*4)+2))
+#define SMC_BYTE_ENABLE(x) (1<<((x*4)+3))
+
+#define SMC_BC_TACS(x) (x << 28) /* 0clk address set-up */
+#define SMC_BC_TCOS(x) (x << 24) /* 4clk chip selection set-up */
+#define SMC_BC_TACC(x) (x << 16) /* 14clk access cycle */
+#define SMC_BC_TCOH(x) (x << 12) /* 1clk chip selection hold */
+#define SMC_BC_TAH(x) (x << 8) /* 4clk address holding time */
+#define SMC_BC_TACP(x) (x << 4) /* 6clk page mode access cycle */
+#define SMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */
+
+#ifndef __ASSEMBLY__
+struct s5p_sromc {
+ unsigned int bw;
+ unsigned int bc[6];
+};
+#endif /* __ASSEMBLY__ */
+
+/* Configure the Band Width and Bank Control Regs for required SROMC Bank */
+void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf);
+
+#endif /* __ASM_ARCH_SMC_H_ */
diff --git a/board/samsung/smdkc100/smdkc100.c b/board/samsung/smdkc100/smdkc100.c
index d3189f6..1ad68b9 100644
--- a/board/samsung/smdkc100/smdkc100.c
+++ b/board/samsung/smdkc100/smdkc100.c
@@ -24,7 +24,7 @@
#include <common.h>
#include <asm/io.h>
-#include <asm/arch/smc.h>
+#include <asm/arch/sromc.h>
#include <asm/arch/gpio.h>
#include <netdev.h>
@@ -50,7 +50,7 @@ static void smc9115_pre_init(void)
| SMC_BC_TACP(0x6) | SMC_BC_PMC(0x0);
/* Select and configure the SROMC bank */
- s5pc1xx_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf);
+ s5p_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf);
}
int board_init(void)
--
1.7.1
Reference results of the experiments on TI OMAP3430 at 600 MHz
$ bench_strcmp -N "strcmp_1k" -s 1k -I 200
[original C code]
prc thr usecs/call samples errors cnt/samp size
strcmp_1k 1 1 10.38000 102 0 15000 1024
[ARM optimized code]
prc thr usecs/call samples errors cnt/samp size
strcmp_1k 1 1 3.08840 88 0 15000 1024
The work was derived from ARM Ltd, contributed to newlib, and reworked
for Android by Linaro.
Code Review:
https://review.source.android.com/#change,22419
Hi
I am using Linaro gcc on Ubuntu/ARM. I am having a problem in building
a package that does not support thumb nor thumb2. When I typed "gcc -v"
I saw that "–with-mode=thumb" and I assume that means my gcc compiler
will try to optimize some code in thumb. So I assume I need to make my
Linaro compiler knows that no thumb! Please correct me if I were wrong.
What flag I have to pass in making? I mean what to type in after CCFLAGS=
in make or what to be added in Makefile. Thanks!
Tegra's board files currently contain quite a number of tables, with
board-specific content. For example, (in mainline) arch/arm/mach-tegra/
board-seaboard-pinmux.c contains a table of pinmux settings, a table of
pin drive strengths, and a list of all GPIOs that must be enabled. In
the ChromeOS kernel, there are a number of additional tables for DVFS
limits on various clocks and regulators, memory controller timing
settings, etc. etc.
In a devicetree-enabled kernel, it seems like these could simply be
pushed into the Tegra SoC/CPU DT node as custom fields holding many-
valued tuples that contain the raw table data.
Does this seem like a reasonable thing to do?
--
nvpublic
Hi Russell,
Here's the current state of the device tree patches for basic
infrastructure support. It's pretty much the same as the last series
I sent to you, except I've dropped the patches that add .dts files and
board support simply because the final location for storing .dtb files
is still up in the air.
After hearing from multiple people this week at UDS, and specifically
having a long conversation about it with tglx, I'd really think it's
time to start getting some wider testing in linux-next since it has
seemed to be quite stable for a while now. In fact, I want to put it
in right now so that there is the /option/ of getting it into 2.6.40
with a separate pull request near the end of the merge window (I'm not
asking you to commit to merging it, but it isn't even an option if it
isn't in linux-next).
Right now it merges cleanly with linux-next and the resulting tree
builds and boots at least on qemu. Unless you really object, I'm
going to ask Stephen to add the following branch to the /end/ of the
list of trees for linux-next so it can easily be dropped it if it
causes any problems.
git://git.secretlab.ca/git/linux-2.6 devicetree/arm-next
g.
---
Grant Likely (5):
arm/dt: Make __vet_atags also accept a dtb image
arm/dt: Allow CONFIG_OF on ARM
arm/dt: consolidate atags setup into setup_machine_atags
arm/dt: probe for platforms via the device tree
dt: add documentation of ARM dt boot interface
Documentation/arm/Booting | 33 +++++
Documentation/devicetree/booting-without-of.txt | 48 +++++++-
arch/arm/Kconfig | 7 +
arch/arm/include/asm/mach/arch.h | 9 +
arch/arm/include/asm/prom.h | 37 ++++++
arch/arm/include/asm/setup.h | 4 +
arch/arm/kernel/Makefile | 1-
arch/arm/kernel/devtree.c | 145 +++++++++++++++++++++++
arch/arm/kernel/head-common.S | 24 +++-
arch/arm/kernel/head.S | 8 +
arch/arm/kernel/setup.c | 90 +++++++++-----
arch/arm/mm/init.c | 11 ++
12 files changed, 367 insertions(+), 50 deletions(-)
create mode 100644 arch/arm/include/asm/prom.h
create mode 100644 arch/arm/kernel/devtree.c
