Hi,
I tried booting linux-linaro-2.6.37 kernel on my beagle board C4. I executed
following:
1. Installed linaro on a 4 GB SD card using linaro-image-tools 0.4.1 with
hwpack daily snapshot hwpack_linaro-omap3_20110125-0_armel_supported.tar.gz
and linaro-natty-headless-tar-20101202-1.tar.gz. It was booting properly on
my BB.
2. Cloned linux-linaro-2.6.37. Changed to source directory
3. make ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- omap2plus_defconfig
4. make ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- menuconfig (enabled
EARLY_PRINTK)
5. make ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- uImage
6. make ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- modules
7. make ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- modules_install
INSTALL_MOD_PATH=/media/rootfs
8. cp arch/arm/boot/uImage /media/boot; sync
Everything went on smoothly. Then I put the SD card on BB and powered it on.
I got a kernel panic: http://paste.ubuntu.com/560562
Please help me figuring out the problem. Is it because I didn't create
uInitrd? If so, then how to create it for ARM?
Regards,
Avik
Hi,
I have an interesting observation that I thought might be interesting
to the tool-chain team.
I was trying to build u-boot in Thumb2 for OMAP4. Everything was fine
until I added some patches recently. One of these patches introduced an
API (let's say foo()) that has a weakly linked alias(let's say
__foo()) and a strongly linked implementation(the real foo()) in an
assembly file.
Although I give -mthumb and -mthumb-interwork for all the files,
apparently GCC generates ARM code for assembly files. In the final
image foobar() calls foo() using a BL. Since foobar() is in Thumb and
foo() in ARM, it ends up crashing. Looks like foobar() assumed foo()
to be Thumb because __foo() is Thumb.
Also I see that 'objdump -S' aborts when it tries to parse foo().
I could workaround this problem by having foo() also in a C file that
in turn calls into the assembly file.
I tried Linaro GCC 4.5.2 and Codesourcery Lite GCC 4.4.1. Both seem to
have the issue.
Isn't this an issue with GCC or am I missing something?
-Aneesh
We currently use a feature branch / merge request / merge / test /
push approach in gcc-linaro. This works fine for a reasonable cost
but can mean that patches sit unreviewed and unmerged for up to a
month. Ramana, Andrew, and I had a talk about this earlier in the
week and I've written up the ideas here:
https://wiki.linaro.org/MichaelHope/Sandbox/ReviewThoughts
We're a bit unique as gcc-linaro started from a mature base, running
the testsuite takes days, and the product is so big that bzr takes a
long time to work on it.
If you have experience in running a master branch or ideas on
continious integration please have a read.
-- Michael
SROM config code is made common for S5P series of boards.
smdkc100.c now refers to s5p-common/sromc.c for SROM related
subroutines.
Signed-off-by: Chander Kashyap <chander.kashyap(a)linaro.org>
---
arch/arm/cpu/armv7/s5p-common/Makefile | 3 +-
arch/arm/cpu/armv7/s5p-common/sromc.c | 49 ++++++++++++++++++++++++++
arch/arm/cpu/armv7/s5pc1xx/Makefile | 1 -
arch/arm/cpu/armv7/s5pc1xx/sromc.c | 49 --------------------------
arch/arm/include/asm/arch-s5pc1xx/smc.h | 53 -----------------------------
arch/arm/include/asm/arch-s5pc1xx/sromc.h | 53 +++++++++++++++++++++++++++++
board/samsung/smdkc100/smdkc100.c | 4 +-
7 files changed, 106 insertions(+), 106 deletions(-)
create mode 100644 arch/arm/cpu/armv7/s5p-common/sromc.c
delete mode 100644 arch/arm/cpu/armv7/s5pc1xx/sromc.c
delete mode 100644 arch/arm/include/asm/arch-s5pc1xx/smc.h
create mode 100644 arch/arm/include/asm/arch-s5pc1xx/sromc.h
diff --git a/arch/arm/cpu/armv7/s5p-common/Makefile b/arch/arm/cpu/armv7/s5p-common/Makefile
index ce0a41e..1705399 100644
--- a/arch/arm/cpu/armv7/s5p-common/Makefile
+++ b/arch/arm/cpu/armv7/s5p-common/Makefile
@@ -27,7 +27,8 @@ LIB = $(obj)libs5p-common.o
COBJS-y += cpu_info.o
COBJS-y += timer.o
-COBJS-$(CONFIG_PWM) += pwm.o
+COBJS-y += sromc.o
+COBJS-$(CONFIG_PWM) += pwm.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS))
diff --git a/arch/arm/cpu/armv7/s5p-common/sromc.c b/arch/arm/cpu/armv7/s5p-common/sromc.c
new file mode 100644
index 0000000..091e8d1
--- /dev/null
+++ b/arch/arm/cpu/armv7/s5p-common/sromc.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2010 Samsung Electronics
+ * Naveen Krishna Ch <ch.naveen(a)samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sromc.h>
+
+/*
+ * s5p_config_sromc() - select the proper SROMC Bank and configure the
+ * band width control and bank control registers
+ * srom_bank - SROM
+ * srom_bw_conf - SMC Band witdh reg configuration value
+ * srom_bc_conf - SMC Bank Control reg configuration value
+ */
+void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf)
+{
+ u32 tmp;
+ struct s5p_sromc *srom =
+ (struct s5p_sromc *)samsung_get_base_sromc();
+
+ /* Configure SMC_BW register to handle proper SROMC bank */
+ tmp = srom->bw;
+ tmp &= ~(0xF << (srom_bank * 4));
+ tmp |= srom_bw_conf;
+ srom->bw = tmp;
+
+ /* Configure SMC_BC register */
+ srom->bc[srom_bank] = srom_bc_conf;
+}
diff --git a/arch/arm/cpu/armv7/s5pc1xx/Makefile b/arch/arm/cpu/armv7/s5pc1xx/Makefile
index b182bf5..d66314e 100644
--- a/arch/arm/cpu/armv7/s5pc1xx/Makefile
+++ b/arch/arm/cpu/armv7/s5pc1xx/Makefile
@@ -32,7 +32,6 @@ SOBJS = cache.o
SOBJS += reset.o
COBJS += clock.o
-COBJS += sromc.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/arch/arm/cpu/armv7/s5pc1xx/sromc.c b/arch/arm/cpu/armv7/s5pc1xx/sromc.c
deleted file mode 100644
index 044d122..0000000
--- a/arch/arm/cpu/armv7/s5pc1xx/sromc.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * Copyright (C) 2010 Samsung Electronics
- * Naveen Krishna Ch <ch.naveen(a)samsung.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/smc.h>
-
-/*
- * s5pc1xx_config_sromc() - select the proper SROMC Bank and configure the
- * band width control and bank control registers
- * srom_bank - SROM Bank 0 to 5
- * smc_bw_conf - SMC Band witdh reg configuration value
- * smc_bc_conf - SMC Bank Control reg configuration value
- */
-void s5pc1xx_config_sromc(u32 srom_bank, u32 smc_bw_conf, u32 smc_bc_conf)
-{
- u32 tmp;
- struct s5pc1xx_smc *srom =
- (struct s5pc1xx_smc *)samsung_get_base_sromc();
-
- /* Configure SMC_BW register to handle proper SROMC bank */
- tmp = srom->bw;
- tmp &= ~(0xF << (srom_bank * 4));
- tmp |= smc_bw_conf;
- srom->bw = tmp;
-
- /* Configure SMC_BC register */
- srom->bc[srom_bank] = smc_bc_conf;
-}
diff --git a/arch/arm/include/asm/arch-s5pc1xx/smc.h b/arch/arm/include/asm/arch-s5pc1xx/smc.h
deleted file mode 100644
index 88f4ffe..0000000
--- a/arch/arm/include/asm/arch-s5pc1xx/smc.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * (C) Copyright 2010 Samsung Electronics
- * Naveen Krishna Ch <ch.naveen(a)samsung.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * Note: This file contains the register description for Memory subsystem
- * (SROM, NAND Flash, OneNand, DDR, OneDRAM) on S5PC1XX.
- *
- * Only SROMC is defined as of now
- */
-
-#ifndef __ASM_ARCH_SMC_H_
-#define __ASM_ARCH_SMC_H_
-
-#define SMC_DATA16_WIDTH(x) (1<<((x*4)+0))
-#define SMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/
- /* 1-> Byte base address*/
-#define SMC_WAIT_ENABLE(x) (1<<((x*4)+2))
-#define SMC_BYTE_ENABLE(x) (1<<((x*4)+3))
-
-#define SMC_BC_TACS(x) (x << 28) /* 0clk address set-up */
-#define SMC_BC_TCOS(x) (x << 24) /* 4clk chip selection set-up */
-#define SMC_BC_TACC(x) (x << 16) /* 14clk access cycle */
-#define SMC_BC_TCOH(x) (x << 12) /* 1clk chip selection hold */
-#define SMC_BC_TAH(x) (x << 8) /* 4clk address holding time */
-#define SMC_BC_TACP(x) (x << 4) /* 6clk page mode access cycle */
-#define SMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */
-
-#ifndef __ASSEMBLY__
-struct s5pc1xx_smc {
- unsigned int bw;
- unsigned int bc[6];
-};
-#endif /* __ASSEMBLY__ */
-
-/* Configure the Band Width and Bank Control Regs for required SROMC Bank */
-void s5pc1xx_config_sromc(u32 srom_bank, u32 smc_bw_conf, u32 smc_bc_conf);
-
-#endif /* __ASM_ARCH_SMC_H_ */
diff --git a/arch/arm/include/asm/arch-s5pc1xx/sromc.h b/arch/arm/include/asm/arch-s5pc1xx/sromc.h
new file mode 100644
index 0000000..3800a8d
--- /dev/null
+++ b/arch/arm/include/asm/arch-s5pc1xx/sromc.h
@@ -0,0 +1,53 @@
+/*
+ * (C) Copyright 2010 Samsung Electronics
+ * Naveen Krishna Ch <ch.naveen(a)samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Note: This file contains the register description for Memory subsystem
+ * (SROM, NAND Flash, OneNand, DDR, OneDRAM) on S5PC1XX.
+ *
+ * Only SROMC is defined as of now
+ */
+
+#ifndef __ASM_ARCH_SROMC_H_
+#define __ASM_ARCH_SROMC_H_
+
+#define SMC_DATA16_WIDTH(x) (1<<((x*4)+0))
+#define SMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/
+ /* 1-> Byte base address*/
+#define SMC_WAIT_ENABLE(x) (1<<((x*4)+2))
+#define SMC_BYTE_ENABLE(x) (1<<((x*4)+3))
+
+#define SMC_BC_TACS(x) (x << 28) /* 0clk address set-up */
+#define SMC_BC_TCOS(x) (x << 24) /* 4clk chip selection set-up */
+#define SMC_BC_TACC(x) (x << 16) /* 14clk access cycle */
+#define SMC_BC_TCOH(x) (x << 12) /* 1clk chip selection hold */
+#define SMC_BC_TAH(x) (x << 8) /* 4clk address holding time */
+#define SMC_BC_TACP(x) (x << 4) /* 6clk page mode access cycle */
+#define SMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */
+
+#ifndef __ASSEMBLY__
+struct s5p_sromc {
+ unsigned int bw;
+ unsigned int bc[6];
+};
+#endif /* __ASSEMBLY__ */
+
+/* Configure the Band Width and Bank Control Regs for required SROMC Bank */
+void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf);
+
+#endif /* __ASM_ARCH_SMC_H_ */
diff --git a/board/samsung/smdkc100/smdkc100.c b/board/samsung/smdkc100/smdkc100.c
index d3189f6..1ad68b9 100644
--- a/board/samsung/smdkc100/smdkc100.c
+++ b/board/samsung/smdkc100/smdkc100.c
@@ -24,7 +24,7 @@
#include <common.h>
#include <asm/io.h>
-#include <asm/arch/smc.h>
+#include <asm/arch/sromc.h>
#include <asm/arch/gpio.h>
#include <netdev.h>
@@ -50,7 +50,7 @@ static void smc9115_pre_init(void)
| SMC_BC_TACP(0x6) | SMC_BC_PMC(0x0);
/* Select and configure the SROMC bank */
- s5pc1xx_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf);
+ s5p_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf);
}
int board_init(void)
--
1.7.1
Reference results of the experiments on TI OMAP3430 at 600 MHz
$ bench_strcmp -N "strcmp_1k" -s 1k -I 200
[original C code]
prc thr usecs/call samples errors cnt/samp size
strcmp_1k 1 1 10.38000 102 0 15000 1024
[ARM optimized code]
prc thr usecs/call samples errors cnt/samp size
strcmp_1k 1 1 3.08840 88 0 15000 1024
The work was derived from ARM Ltd, contributed to newlib, and reworked
for Android by Linaro.
Code Review:
https://review.source.android.com/#change,22419
Tegra's board files currently contain quite a number of tables, with
board-specific content. For example, (in mainline) arch/arm/mach-tegra/
board-seaboard-pinmux.c contains a table of pinmux settings, a table of
pin drive strengths, and a list of all GPIOs that must be enabled. In
the ChromeOS kernel, there are a number of additional tables for DVFS
limits on various clocks and regulators, memory controller timing
settings, etc. etc.
In a devicetree-enabled kernel, it seems like these could simply be
pushed into the Tegra SoC/CPU DT node as custom fields holding many-
valued tuples that contain the raw table data.
Does this seem like a reasonable thing to do?
--
nvpublic
On Tue, Apr 19, 2011 at 12:33 PM, Wolfgang Denk <wd(a)denx.de> wrote:
> Dear Jim Huang,
>
> In message <BANLkTi=yNnA9nBxWNG_1mfwfd6G_O09GOA(a)mail.gmail.com> you wrote:
>>
>> My idea is that we require abstract 'bootloader' component in Android
>> device/linaro/common, and (patched) 'u-boot' would be the provider of
>> 'bootloader' component in
>> device/linaro/Linaro-Evaluation-Build-Hardware. Also, supporting
>
> If you are discussing requirements for U-Boot, and plan to get these
> merged in to mainlineU-Boot one day, it would probably be a good idea
> to discuss these plans on the U-Boot mailing list as well - ideally
> before any design is cast in iron.
>
> Best regards,
>
> Wolfgang Denk
>
> --
> DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de
> The management question ... is not _whether_ to build a pilot system
> and throw it away. You _will_ do that. The only question is whether
> to plan in advance to build a throwaway, or to promise to deliver the
> throwaway to customers. - Fred Brooks, "The Mythical Man Month"
>
> _______________________________________________
> linaro-dev mailing list
> linaro-dev(a)lists.linaro.org
> http://lists.linaro.org/mailman/listinfo/linaro-dev
>
Wolfgang,
As you can see from this discussion, Linaro is considering applying
resources (probably me) to upstreaming Android Fastboot features into
mainline u-boot. What suggestions do you have for making this process
as painless as possible?
The topic came up briefly here last year:
http://lists.denx.de/pipermail/u-boot/2010-August/076343.html
An implementation exists for omap4/panda on gitorious:
git://gitorious.org/pandaboard/u-boot.git in the omap4_panda_es2.0
branch. There is also a version for omap3 somewhere else on
gitorious.
To bring this to mainline one would have to:
1) Bring code up to current mainline revision.
2) Fix any coding standards issues.
3) Document the new features.
What else? I know one issue maybe why does this need to exist when
other solutions exist. I think that since Android uses it, it is
somewhat of a de facto standard.
All comments welcome,
John
Andy Green has worked on a set of patches adding many features to OMAP4
such as HDMI audio/video, FM receiver, etc. Before I merge that into
the Linaro kernel tree I need some assurance that this won't break
existing OMAP3 support, especially video. The branch is available in
the linux-linaro-2.6.38 Git repository on git.linaro.org, in the
"testing" branch.
So please if you have an OMAP3 board and can perform some testing that
would be appreciated.
Nicolas
On behalf of the Linaro Infrastructure team I'm pleased to announce the
release of Linaro Image Tools 0.4.4.
Linaro Image Tools offer a set of tools for use with Linaro images.
Highlights of this release:
* Support for EfikaMX boards has been added
* Support for i.MX53 LOCO board has been added
* Support for SMDKV310 board has been added
* Usage of sudo has been made optional
* Changes to partition alignment
* The original boot script is stored in the boot partition
* Improvements to the btrfs support
* Support for multiple kernel have been added, in particular
for i.MX53, i.MX51 and OMAP4; also properly fixes U8500
* RAM size on Panda has been increased
* Support for device tree binaries has been added
The source tarball is available from:
https://launchpad.net/linaro-image-tools/trunk/0.4.4
Thanks,
Mattias Backman
