CoreSight May 2025

coresight@lists.linaro.org

8 participants
38 discussions

[PATCH v5 0/5] coresight: Add remote etm support

by Mao Jinlong

The system on chip (SoC) consists of main APSS(Applications processor subsytem) and additional processors like modem, lpass. There is coresight-etm driver for etm trace of APSS. Coresight remote etm driver is for enabling and disabling the etm trace of remote processors. It uses QMI interface to communicate with remote processors' software and uses coresight framework to configure the connection from remote etm source to TMC sinks. Example to capture the remote etm trace: Enable source: echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink echo 1 > /sys/bus/coresight/devices/remote_etm0/enable_source Capture the trace: cat /dev/tmc_etf0 > /data/remote_etm.bin Disable source: echo 0 > /sys/bus/coresight/devices/remote_etm0/enable_source Changes since V4: 1. Add coresight QMI driver 2. Add coresight qmi node and qcom,qmi-id of modem-etm in msm8996 dtsi Changes since V3: 1. Use different compatible for different remote etms in dt. 2. Get qmi instance id from the match table data in driver. Change since V2: 1. Change qcom,inst-id to qcom,qmi-id 2. Fix the error in code for type of remote_etm_remove 3. Depend on QMI helper in Kconfig Changes since V1: 1. Remove unused content 2. Use CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS as remote etm source type. 3. Use enabled instead of enable in driver data. 4. Validate instance id value where it's read from the DT. Mao Jinlong (5): dt-bindings: arm: Add CoreSight QMI component description coresight: Add coresight QMI driver dt-bindings: arm: Add qcom,qmi-id for remote etm coresight: Add remote etm support arm64: dts: qcom: msm8996: Add coresight qmi node .../bindings/arm/qcom,coresight-qmi.yaml | 65 +++++ .../arm/qcom,coresight-remote-etm.yaml | 10 + arch/arm64/boot/dts/qcom/msm8996.dtsi | 11 + drivers/hwtracing/coresight/Kconfig | 24 ++ drivers/hwtracing/coresight/Makefile | 2 + drivers/hwtracing/coresight/coresight-qmi.c | 209 +++++++++++++++ drivers/hwtracing/coresight/coresight-qmi.h | 107 ++++++++ .../coresight/coresight-remote-etm.c | 252 ++++++++++++++++++ 8 files changed, 680 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/qcom,coresight-qmi.yaml create mode 100644 drivers/hwtracing/coresight/coresight-qmi.c create mode 100644 drivers/hwtracing/coresight/coresight-qmi.h create mode 100644 drivers/hwtracing/coresight/coresight-remote-etm.c -- 2.25.1

2 days, 2 hours

[PATCH] arm: coresight: Finish removal of Coresight support in arch/arm/kernel

by James Clark

Commit 184901a06a36 ("ARM: removing support for etb/etm in "arch/arm/kernel/"") removed asm/hardware/coresight.h which is included by this file. Therefore this is dead code so delete it. Signed-off-by: James Clark <james.clark(a)linaro.org> --- arch/arm/include/asm/cti.h | 160 ------------------------------------- 1 file changed, 160 deletions(-) delete mode 100644 arch/arm/include/asm/cti.h diff --git a/arch/arm/include/asm/cti.h b/arch/arm/include/asm/cti.h deleted file mode 100644 index f8500e5d6ea8..000000000000 --- a/arch/arm/include/asm/cti.h +++ /dev/null @@ -1,160 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ASMARM_CTI_H -#define __ASMARM_CTI_H - -#include <asm/io.h> -#include <asm/hardware/coresight.h> - -/* The registers' definition is from section 3.2 of - * Embedded Cross Trigger Revision: r0p0 - */ -#define CTICONTROL 0x000 -#define CTISTATUS 0x004 -#define CTILOCK 0x008 -#define CTIPROTECTION 0x00C -#define CTIINTACK 0x010 -#define CTIAPPSET 0x014 -#define CTIAPPCLEAR 0x018 -#define CTIAPPPULSE 0x01c -#define CTIINEN 0x020 -#define CTIOUTEN 0x0A0 -#define CTITRIGINSTATUS 0x130 -#define CTITRIGOUTSTATUS 0x134 -#define CTICHINSTATUS 0x138 -#define CTICHOUTSTATUS 0x13c -#define CTIPERIPHID0 0xFE0 -#define CTIPERIPHID1 0xFE4 -#define CTIPERIPHID2 0xFE8 -#define CTIPERIPHID3 0xFEC -#define CTIPCELLID0 0xFF0 -#define CTIPCELLID1 0xFF4 -#define CTIPCELLID2 0xFF8 -#define CTIPCELLID3 0xFFC - -/* The below are from section 3.6.4 of - * CoreSight v1.0 Architecture Specification - */ -#define LOCKACCESS 0xFB0 -#define LOCKSTATUS 0xFB4 - -/** - * struct cti - cross trigger interface struct - * @base: mapped virtual address for the cti base - * @irq: irq number for the cti - * @trig_out_for_irq: triger out number which will cause - * the @irq happen - * - * cti struct used to operate cti registers. - */ -struct cti { - void __iomem *base; - int irq; - int trig_out_for_irq; -}; - -/** - * cti_init - initialize the cti instance - * @cti: cti instance - * @base: mapped virtual address for the cti base - * @irq: irq number for the cti - * @trig_out: triger out number which will cause - * the @irq happen - * - * called by machine code to pass the board dependent - * @base, @irq and @trig_out to cti. - */ -static inline void cti_init(struct cti *cti, - void __iomem *base, int irq, int trig_out) -{ - cti->base = base; - cti->irq = irq; - cti->trig_out_for_irq = trig_out; -} - -/** - * cti_map_trigger - use the @chan to map @trig_in to @trig_out - * @cti: cti instance - * @trig_in: trigger in number - * @trig_out: trigger out number - * @channel: channel number - * - * This function maps one trigger in of @trig_in to one trigger - * out of @trig_out using the channel @chan. - */ -static inline void cti_map_trigger(struct cti *cti, - int trig_in, int trig_out, int chan) -{ - void __iomem *base = cti->base; - unsigned long val; - - val = __raw_readl(base + CTIINEN + trig_in * 4); - val |= BIT(chan); - __raw_writel(val, base + CTIINEN + trig_in * 4); - - val = __raw_readl(base + CTIOUTEN + trig_out * 4); - val |= BIT(chan); - __raw_writel(val, base + CTIOUTEN + trig_out * 4); -} - -/** - * cti_enable - enable the cti module - * @cti: cti instance - * - * enable the cti module - */ -static inline void cti_enable(struct cti *cti) -{ - __raw_writel(0x1, cti->base + CTICONTROL); -} - -/** - * cti_disable - disable the cti module - * @cti: cti instance - * - * enable the cti module - */ -static inline void cti_disable(struct cti *cti) -{ - __raw_writel(0, cti->base + CTICONTROL); -} - -/** - * cti_irq_ack - clear the cti irq - * @cti: cti instance - * - * clear the cti irq - */ -static inline void cti_irq_ack(struct cti *cti) -{ - void __iomem *base = cti->base; - unsigned long val; - - val = __raw_readl(base + CTIINTACK); - val |= BIT(cti->trig_out_for_irq); - __raw_writel(val, base + CTIINTACK); -} - -/** - * cti_unlock - unlock cti module - * @cti: cti instance - * - * unlock the cti module, or else any writes to the cti - * module is not allowed. - */ -static inline void cti_unlock(struct cti *cti) -{ - __raw_writel(CS_LAR_KEY, cti->base + LOCKACCESS); -} - -/** - * cti_lock - lock cti module - * @cti: cti instance - * - * lock the cti module, so any writes to the cti - * module will be not allowed. - */ -static inline void cti_lock(struct cti *cti) -{ - __raw_writel(~CS_LAR_KEY, cti->base + LOCKACCESS); -} -#endif -- 2.34.1

2 weeks, 2 days

[PATCH v1 00/11] CoreSight: Refactor CPU PM and hotplug

by Leo Yan

Besides managing tracers (ETM) in CPU PM and hotplug flows, the CoreSight framework is found the issues below: Firstly, on some hardware platforms, CoreSight links (e.g., funnels and replicators, etc) reside in a cluster power domain. If the cluster is powered off, the link components also will lose their context. In this case, Arm CoreSight drivers report errors when detect unpaired self-host claim tags. Secondly, if a path has been activated from per CPU's tracer (ETM) to links and a sink in Sysfs mode, then when the CPU is hot-plugged off, only the associated ETM will be disabled. Afterwards, the links and the sink always keep on and no chance to be disabled. The last issue was reported by Yabin Cui (Google) that the TRBE driver misses to save and restore context during CPU low power states. As a result, it may cause hardware lockup issue on some devices. To resolve the power management issues, this series extends CPU power management to cover the entire activated path, including links and sinks. It moves CPU PM and hotplug notifiers from the ETMv4 driver to the CoreSight core layer. The core layer has sufficient info to maintain activated paths and can traverse the entire path to manipulate CoreSight modules accordingly. Patch 01 is to fix a bug in ETMv4 save and restore callbacks. Patches 02 ~ 06 move CPU PM code from ETMv4 driver to the core layer, and extends to maintain activated paths and control links. Patches 07 and 08 support save and restore context for per-CPU sink (TRBE). Note, for avoid long latency, system level's sinks in an activated path are not touched during CPU suspend and resume. Patches 09 ~ 11 move CPU hotplug notifier from ETMv4 driver to the core layer. The entire path will be controlled if the corresponding CPU is hot-plugged on or off. This series has been verified on Hikey960 for CPUIdle and hotplug. And it is tested on FVP for verifying TRBE with idle states. Leo Yan (10): coresight: etm4x: Control the trace unit in CPU suspend coresight: Set per CPU source pointer coresight: Register CPU PM notifier in core layer coresight: etm4x: Hook CPU PM callbacks coresight: Save activated path into source device coresight: Control path during CPU PM coresight: Add PM callbacks in sink operation coresight: Take hotplug lock in enable_source_store() for Sysfs mode coresight: Move CPU hotplug callbacks to core layer coresight: Manage activated paths during CPU hotplug Yabin Cui (1): coresight: trbe: Save and restore state across CPU low power state drivers/hwtracing/coresight/coresight-core.c | 252 +++++++++++++++++++++++++++++++++++++++++ drivers/hwtracing/coresight/coresight-etm3x-core.c | 2 + drivers/hwtracing/coresight/coresight-etm4x-core.c | 133 ++++++---------------- drivers/hwtracing/coresight/coresight-priv.h | 1 + drivers/hwtracing/coresight/coresight-sysfs.c | 12 +- drivers/hwtracing/coresight/coresight-trbe.c | 65 +++++++++++ include/linux/coresight.h | 11 ++ 7 files changed, 375 insertions(+), 101 deletions(-) -- 2.34.1

2 weeks, 5 days

[PATCH v6 0/2] coresight: Add Coresight Trace Network On Chip driver

by Yuanfang Zhang

The Trace Network On Chip (TNOC) is an integration hierarchy which is a hardware component that integrates the functionalities of TPDA and funnels. It collects trace from subsystems and transfers it to coresight sink. In addition to the generic TNOC mentioned above, there is also a special type of TNOC called Interconnect TNOC. Unlike the generic TNOC, the Interconnect TNOC doesn't need ATID. Its primary function is to connect the source of subsystems to the Aggregator TNOC. Its driver is different from this patch and will describe it and upstream its driver separately. Signed-off-by: Yuanfang Zhang <quic_yuanfang(a)quicinc.com> --- Changes in v6: - Add a newline after return statements. - Use 'x &= foo' to replace 'x = x & foo'. - Use 'x |= foo' to replace 'x = x | foo'. - Link to v5: https://lore.kernel.org/r/20250512-trace-noc-v5-0-f2ef070baee5@quicinc.com Changes in v5: - update cover-letter to describe the Interconnect TNOC. - Link to v4: https://lore.kernel.org/r/20250415-trace-noc-v4-0-979938fedfd8@quicinc.com Changes in v4: - Fix dt_binding warning. - update mask of trace_noc amba_id. - Modify driver comments. - rename TRACE_NOC_SYN_VAL to TRACE_NOC_SYNC_INTERVAL. - Link to v3: https://lore.kernel.org/r/20250411-trace-noc-v3-0-1f19ddf7699b@quicinc.com Changes in v3: - Remove unnecessary sysfs nodes. - update commit messages. - Use 'writel' instead of 'write_relaxed' when writing to the register for the last time. - Add trace_id ops. - Link to v2: https://lore.kernel.org/r/20250226-trace-noc-driver-v2-0-8afc6584afc5@quici… Changes in v2: - Modified the format of DT binging file. - Fix compile warnings. - Link to v1: https://lore.kernel.org/r/46643089-b88d-49dc-be05-7bf0bb21f847@quicinc.com --- Yuanfang Zhang (2): dt-bindings: arm: Add device Trace Network On Chip definition coresight: add coresight Trace Network On Chip driver .../bindings/arm/qcom,coresight-tnoc.yaml | 111 ++++++++++++ drivers/hwtracing/coresight/Kconfig | 13 ++ drivers/hwtracing/coresight/Makefile | 1 + drivers/hwtracing/coresight/coresight-tnoc.c | 192 +++++++++++++++++++++ drivers/hwtracing/coresight/coresight-tnoc.h | 34 ++++ 5 files changed, 351 insertions(+) --- base-commit: a2cc6ff5ec8f91bc463fd3b0c26b61166a07eb11 change-id: 20250403-trace-noc-f8286b30408e Best regards, -- Yuanfang Zhang <quic_yuanfang(a)quicinc.com>

1 month, 1 week

[PATCH] coresight-tpdm: add trace_id sysfs node

by Yuanfang Zhang

The trace ID of TPMD is the trace ID of the TPDA or TNOC which it is connected to, this change adds trace_id sysfs node to expose this trace id to userspace. Signed-off-by: Yuanfang Zhang <quic_yuanfang(a)quicinc.com> --- drivers/hwtracing/coresight/coresight-tpdm.c | 16 ++++++++++++++++ drivers/hwtracing/coresight/coresight-tpdm.h | 2 ++ 2 files changed, 18 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index 7214e65097ec9ac69f6c7c9278bcd28d25945c9e..8a5d115157924f39b09f8e3005827d7d64aa376c 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -497,6 +497,9 @@ static int tpdm_enable(struct coresight_device *csdev, struct perf_event *event, __tpdm_enable(drvdata); drvdata->enable = true; + + if (path) + drvdata->traceid = path->trace_id; spin_unlock(&drvdata->spinlock); dev_dbg(drvdata->dev, "TPDM tracing enabled\n"); @@ -554,6 +557,7 @@ static void tpdm_disable(struct coresight_device *csdev, __tpdm_disable(drvdata); coresight_set_mode(csdev, CS_MODE_DISABLED); drvdata->enable = false; + drvdata->traceid = 0; spin_unlock(&drvdata->spinlock); dev_dbg(drvdata->dev, "TPDM tracing disabled\n"); @@ -655,9 +659,21 @@ static ssize_t integration_test_store(struct device *dev, } static DEVICE_ATTR_WO(integration_test); +static ssize_t traceid_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + unsigned long val; + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->traceid; + return sprintf(buf, "%#lx\n", val); +} +static DEVICE_ATTR_RO(traceid); + static struct attribute *tpdm_attrs[] = { &dev_attr_reset_dataset.attr, &dev_attr_integration_test.attr, + &dev_attr_traceid.attr, NULL, }; diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h index b117543897344b689f666f6890cabb59c8ee4869..e12a64f265daa86f1b82fa3640e271e8386f99af 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -300,6 +300,7 @@ struct cmb_dataset { * @cmb Specifics associated to TPDM CMB. * @dsb_msr_num Number of MSR supported by DSB TPDM * @cmb_msr_num Number of MSR supported by CMB TPDM + * @traceid: Value of the current ID for this component. */ struct tpdm_drvdata { @@ -313,6 +314,7 @@ struct tpdm_drvdata { struct cmb_dataset *cmb; u32 dsb_msr_num; u32 cmb_msr_num; + u8 traceid; }; /* Enumerate members of various datasets */ --- base-commit: 94305e83eccb3120c921cd3a015cd74731140bac change-id: 20250523-showtraceid-2df91c89be8f Best regards, -- Yuanfang Zhang <quic_yuanfang(a)quicinc.com>

1 month, 2 weeks

Possibility of using Coresight STM - ETR as console for System Control Processor

by Linu Cherian

Hi, We are looking for console options( output only) for the SCP(system control processor)cores in our SOC other than UART and was considering STM as an option. Something like this, SCP ----> STM ---> ETR ---> DDR <--- Linux On the Linux system, some user space scripts can retrieve the ETR trace buffers and move it to a file on a periodic basis. Do you see any basic issue with this approach or have better alternatives to suggest ? Few issues we could think of, 1. SCP wont be able to route the messages to the STM -> ETR path until those are initialized by the Linux user space. Hence any messages until Linux comes up need to be buffered in the SCP local memory and should get flushed once the STM - ETR path is ready. 2. Possible message loss due to buffer overwrite We might have to reserve the ETR trace buffers only to the SCP and keep sufficiently large buffers to reduce the message loss. Assume that reserving a STM port for use by an external core can be achieved from the Linux STM sysfs interface. Thanks, Linu Cherian.

1 month, 2 weeks

[PATCH v7 0/2] coresight: Add Coresight Trace Network On Chip driver

by Yuanfang Zhang

The Trace Network On Chip (TNOC) is an integration hierarchy which is a hardware component that integrates the functionalities of TPDA and funnels. It collects trace from subsystems and transfers it to coresight sink. In addition to the generic TNOC mentioned above, there is also a special type of TNOC called Interconnect TNOC. Unlike the generic TNOC, the Interconnect TNOC doesn't need ATID. Its primary function is to connect the source of subsystems to the Aggregator TNOC. Its driver is different from this patch and will describe it and upstream its driver separately. Signed-off-by: Yuanfang Zhang <quic_yuanfang(a)quicinc.com> --- Changes in v7: - Move the content in header file into coresight-tnoc.c. - Use scoped_guard() to replace spin_lock(). - Invoke coresight_trace_id_put_system_id() for registration failure. - Link to v6: https://lore.kernel.org/r/20250522-trace-noc-v6-0-f5a9bcae90ee@quicinc.com Changes in v6: - Add a newline after return statements. - Use 'x &= foo' to replace 'x = x & foo'. - Use 'x |= foo' to replace 'x = x | foo'. - Link to v5: https://lore.kernel.org/r/20250512-trace-noc-v5-0-f2ef070baee5@quicinc.com Changes in v5: - update cover-letter to describe the Interconnect TNOC. - Link to v4: https://lore.kernel.org/r/20250415-trace-noc-v4-0-979938fedfd8@quicinc.com Changes in v4: - Fix dt_binding warning. - update mask of trace_noc amba_id. - Modify driver comments. - rename TRACE_NOC_SYN_VAL to TRACE_NOC_SYNC_INTERVAL. - Link to v3: https://lore.kernel.org/r/20250411-trace-noc-v3-0-1f19ddf7699b@quicinc.com Changes in v3: - Remove unnecessary sysfs nodes. - update commit messages. - Use 'writel' instead of 'write_relaxed' when writing to the register for the last time. - Add trace_id ops. - Link to v2: https://lore.kernel.org/r/20250226-trace-noc-driver-v2-0-8afc6584afc5@quici… Changes in v2: - Modified the format of DT binging file. - Fix compile warnings. - Link to v1: https://lore.kernel.org/r/46643089-b88d-49dc-be05-7bf0bb21f847@quicinc.com --- Yuanfang Zhang (2): dt-bindings: arm: Add device Trace Network On Chip definition coresight: add coresight Trace Network On Chip driver .../bindings/arm/qcom,coresight-tnoc.yaml | 111 +++++++++++ drivers/hwtracing/coresight/Kconfig | 13 ++ drivers/hwtracing/coresight/Makefile | 1 + drivers/hwtracing/coresight/coresight-tnoc.c | 216 +++++++++++++++++++++ 4 files changed, 341 insertions(+) --- base-commit: a2cc6ff5ec8f91bc463fd3b0c26b61166a07eb11 change-id: 20250403-trace-noc-f8286b30408e Best regards, -- Yuanfang Zhang <quic_yuanfang(a)quicinc.com>

1 month, 3 weeks

[GIT PULL] coresight: updates for Linux v6.16

by Suzuki K Poulose

Hi Greg, Please find the CoreSight self-hosted tracing subsystem updates for Linux v6.16. Kindly pull, Suzuki --- The following changes since commit 9c32cda43eb78f78c73aee4aa344b777714e259b: Linux 6.15-rc3 (2025-04-20 13:43:47 -0700) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git tags/coresight-next-v6.16 for you to fetch changes up to 408c97c4a5e0b634dcd15bf8b8808b382e888164: coresight: prevent deactivate active config while enabling the config (2025-05-20 16:38:54 +0100) ---------------------------------------------------------------- coresight: updates for Linux v6.16 CoreSight self-hosted trace driver subsystem updates for Linux v6.16 includes: - Clear CLAIM tags on device probe if self-hosted tags are set. - Support for perf AUX pause/resume for CoreSight ETM PMU driver, with trace collection at pause. - Miscellaneous fixes for the subsystem Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> ---------------------------------------------------------------- Andy Shevchenko (1): coresight: cti: Replace inclusion by struct fwnode_handle forward declaration Dmitry Baryshkov (1): dt-bindings: arm: arm,coresight-static-replicator: add optional clocks James Clark (8): coresight: Convert tag clear function to take a struct csdev_access coresight: Only check bottom two claim bits coresight: Add claim tag warnings and debug messages coresight: etm3x: Convert raw base pointer to struct coresight access coresight: Clear self hosted claim tag on probe coresight: Remove inlines from static function definitions coresight: Remove extern from function declarations coresight: Add a KUnit test for coresight_find_default_sink() Junhao He (1): coresight: Fixes device's owner field for registered using coresight_init_driver() Leo Yan (9): coresight: replicator: Fix panic for clearing claim tag coresight: etm4x: Extract the trace unit controlling coresight: Introduce pause and resume APIs for source coresight: etm4x: Hook pause and resume callbacks coresight: perf: Support AUX trace pause and resume coresight: tmc: Re-enable sink after buffer update coresight: perf: Update buffer on AUX pause Documentation: coresight: Document AUX pause and resume coresight: etm4x: Fix timestamp bit field handling Mao Jinlong (2): coresight: Disable MMIO logging for coresight stm driver coresight: tmc: fix failure to disable/enable ETF after reading Yabin Cui (2): coresight: catu: Introduce refcount and spinlock for enabling/disabling coresight: core: Disable helpers for devices that fail to enable Yeoreum Yun (3): coresight/etm4: fix missing disable active config coresight: holding cscfg_csdev_lock while removing cscfg from csdev coresight: prevent deactivate active config while enabling the config .../arm/arm,coresight-static-replicator.yaml | 13 ++ Documentation/trace/coresight/coresight-perf.rst | 31 ++++ drivers/hwtracing/coresight/Kconfig | 9 ++ drivers/hwtracing/coresight/Makefile | 3 + drivers/hwtracing/coresight/coresight-catu.c | 39 +++-- drivers/hwtracing/coresight/coresight-catu.h | 1 + drivers/hwtracing/coresight/coresight-config.h | 2 +- drivers/hwtracing/coresight/coresight-core.c | 131 ++++++++++++----- drivers/hwtracing/coresight/coresight-cpu-debug.c | 3 +- drivers/hwtracing/coresight/coresight-cti-core.c | 2 + drivers/hwtracing/coresight/coresight-cti.h | 3 +- drivers/hwtracing/coresight/coresight-etb10.c | 4 +- drivers/hwtracing/coresight/coresight-etm-perf.c | 84 ++++++++++- drivers/hwtracing/coresight/coresight-etm.h | 6 +- drivers/hwtracing/coresight/coresight-etm3x-core.c | 28 ++-- .../hwtracing/coresight/coresight-etm3x-sysfs.c | 8 +- drivers/hwtracing/coresight/coresight-etm4x-core.c | 158 +++++++++++++++------ .../hwtracing/coresight/coresight-etm4x-sysfs.c | 8 +- drivers/hwtracing/coresight/coresight-etm4x.h | 2 + drivers/hwtracing/coresight/coresight-funnel.c | 4 +- .../hwtracing/coresight/coresight-kunit-tests.c | 74 ++++++++++ drivers/hwtracing/coresight/coresight-platform.c | 26 ++-- drivers/hwtracing/coresight/coresight-priv.h | 22 +-- drivers/hwtracing/coresight/coresight-replicator.c | 6 +- drivers/hwtracing/coresight/coresight-stm.c | 8 +- .../coresight/coresight-syscfg-configfs.c | 2 +- drivers/hwtracing/coresight/coresight-syscfg.c | 51 +++++-- drivers/hwtracing/coresight/coresight-tmc-core.c | 11 +- drivers/hwtracing/coresight/coresight-tmc-etf.c | 20 ++- drivers/hwtracing/coresight/coresight-tmc-etr.c | 26 ++-- drivers/hwtracing/coresight/coresight-tpiu.c | 2 +- drivers/hwtracing/coresight/coresight-trbe.c | 18 +-- include/linux/coresight.h | 44 +++--- 33 files changed, 624 insertions(+), 225 deletions(-) create mode 100644 drivers/hwtracing/coresight/coresight-kunit-tests.c

1 month, 3 weeks

[PATCH v3 0/2] coresight: etm4x: Refactor trace filter

by Leo Yan

This series is minor refactoring for trace filter and comes from the previous patch set [1]. The first patch introduces a new helper has_feat_trf() for detecing if FEAT_TRF is implemented. This is more readable. The second patch refactors the ts_source_show() function. It simplifies to directly return the TS value when FEAT_TRF is implemented. [1] https://lore.kernel.org/linux-arm-kernel/20250519174945.2245271-1-leo.yan@a… Changes from v2: - Added the has_feat_trf() helper for more readable (James Clark) Leo Yan (2): coresight: etm4x: Introduce has_feat_trf() helper coresight: etm4x: Refactor returning TS field drivers/hwtracing/coresight/coresight-etm4x-core.c | 8 ++++---- drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 18 +++--------------- drivers/hwtracing/coresight/coresight-etm4x.h | 9 +++++++++ 3 files changed, 16 insertions(+), 19 deletions(-) -- 2.34.1

1 month, 3 weeks

Re: [PATCH v6 0/3] coresight: prevent deactivate active config while enabling the config

by Suzuki K Poulose

On Wed, 14 May 2025 17:19:48 +0100, Yeoreum Yun wrote: > While enable active config via cscfg_csdev_enable_active_config(), > active config could be deactivated via configfs' sysfs interface. > This could make UAF issue in below scenario: > > CPU0 CPU1 > (sysfs enable) load module > cscfg_load_config_sets() > activate config. // sysfs > (sys_active_cnt == 1) > ... > cscfg_csdev_enable_active_config() > lock(csdev->cscfg_csdev_lock) > // here load config activate by CPU1 > unlock(csdev->cscfg_csdev_lock) > > [...] Applied, thanks! [1/3] coresight/etm4: fix missing disable active config https://git.kernel.org/coresight/c/895b12b7 [2/3] coresight: holding cscfg_csdev_lock while removing cscfg from csdev https://git.kernel.org/coresight/c/53b9e265 [3/3] coresight: prevent deactivate active config while enabling the config https://git.kernel.org/coresight/c/408c97c4 Best regards, -- Suzuki K Poulose <suzuki.poulose(a)arm.com>

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CoreSight May 2025